CN203787413U - Wafer level chip TSV (Through Silicon Via) packaging structure - Google Patents
Wafer level chip TSV (Through Silicon Via) packaging structure Download PDFInfo
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- CN203787413U CN203787413U CN201420006299.7U CN201420006299U CN203787413U CN 203787413 U CN203787413 U CN 203787413U CN 201420006299 U CN201420006299 U CN 201420006299U CN 203787413 U CN203787413 U CN 203787413U
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- China
- Prior art keywords
- tsv
- deep hole
- layer
- metallic circuit
- insulating barrier
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- Expired - Lifetime
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 30
- 239000010703 silicon Substances 0.000 title claims abstract description 30
- 238000004806 packaging method and process Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000002184 metal Substances 0.000 claims abstract description 66
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 52
- 239000010949 copper Substances 0.000 claims description 19
- 229910052802 copper Inorganic materials 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000005260 corrosion Methods 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000013461 design Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 abstract 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 13
- 230000006872 improvement Effects 0.000 description 5
- 238000005538 encapsulation Methods 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 238000001311 chemical methods and process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a wafer level chip TSV (Through Silicon Via) packaging structure comprising a plurality of chip units each including a silicon layer. A plurality of TSV deep holes are formed in each silicon layer, a metal bonding pad is formed under the bottom of each TSV deep hole, and the maximal diameter of the TSV deep hole is smaller than the minimal edge length of the metal bonding pad. Each silicon layer, and the bottom and the sidewall of each TSV deep hole are covered by an insulation layer. The insulation layer covering the bottom of one TSV deep hole is provided with a window. Each insulation layer the each window are covered by a metal layer which is corroded to form a designed metal line, and each metal bonding pad is electrically connected with the outside through the metal line. The wafer level chip TSV packaging structure can reduce cost, and improves coverage of metal at positions of the TSV deep holes, so that the packaging yield rate of high aspect ratio TSV deep holes.
Description
Technical field
The utility model relates to a kind of wafer level packaging structure of semiconductor chip, relates in particular to a kind of wafer stage chip TSV encapsulating structure that utilizes copper metal to do UNICOM's circuit and pad.
Background technology
Wafer-level packaging (Wafer Level Packaging; WLP) being a kind of of IC packaged type, is, after full wafer wafer production completes, directly on wafer, to encapsulate, and is just cut into single IC after completing.
At present, in the wafer-level packaging process of semiconductor chip, conventionally adopt aluminium as the material of metallic circuit and pad, but need to form the smooth conducting of certain thickness aluminum metal layer guarantee circuit.In the encapsulation of some high-aspect-ratio TSV deep holes, because the spreadability of aluminum metal is not good, after sputtering aluminum metal, on the metal pad of the dark bottom of TSV, still without aluminum metal, cover, cause metal pad circuit to carry out electrical UNICOM with the external world.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model proposes a kind of wafer stage chip TSV encapsulating structure, can reduce cost, improve the spreadability of TSV deep hole position metal, thereby improve the encapsulation yield of high-aspect-ratio TSV deep hole.
The technical solution of the utility model is achieved in that
A kind of TSV encapsulating structure of wafer stage chip, comprise several chip units, each chip unit comprises silicon layer, on described silicon layer, be formed with several TSV deep holes, the below, bottom of each TSV deep hole is formed with metal pad, and the maximum gauge of described TSV deep hole is less than the minimum length of side of described metal pad, described silicon layer, on the bottom of described TSV deep hole and sidewall, be all coated with a layer insulating, on the insulating barrier covering on the bottom of described TSV deep hole, offer a window, on described insulating barrier and described window, cover and form a metal level, described metal level corrosion forms the metallic circuit of design, described metal pad carries out electrical UNICOM by described metallic circuit and the external world.
As further improvement of the utility model, described TSV deep hole runs through described silicon layer, described TSV deep hole is equal a kind of in equal straight hole of the inclined hole that diminishes gradually to the diameter of its opening along its bottom and the diameter along its bottom to its opening, and the degree of depth of described TSV deep hole is not more than the thickness of described silicon layer.
As further improvement of the utility model, the diameter of described window is not more than the diameter of the bottom of described TSV deep hole; The degree of depth of described window is not less than the thickness of described insulating barrier.
As further improvement of the utility model, described metal level comprises one deck barrier layer and layer of copper metal level, and described copper metal layer is positioned at a described barrier layer side of described insulating barrier dorsad.
As further improvement of the utility model, described metallic circuit is included in the first metallic circuit of forming on the insulating barrier of described silicon surface, the second metallic circuit forming on the insulating barrier of the sidewall of described TSV deep hole and the 3rd metallic circuit forming in described window; Described the first metallic circuit extends to form sets big or small circular contact point, described the second metallic circuit covers the insulating barrier on described sidewall, described the 3rd metallic circuit covers the insulating barrier on described bottom, and penetrate and cover described window, described metal pad carries out electrical UNICOM by described first, second, third metallic circuit and the external world.
As further improvement of the utility model, described barrier layer is titanium coating or CTB alloy layer.
The beneficial effects of the utility model are: the utility model provides a kind of wafer stage chip TSV encapsulating structure, first, on the silicon layer of chip wafer unit, the bottom of TSV deep hole and sidewall, are all coated with a layer insulating; Then, on the insulating barrier covering, offer a window on the bottom of TSV deep hole, on insulating barrier and window, cover to form a metal level, metal level comprise barrier layer and and copper metal layer, barrier layer can be a kind of in titanium coating and CTB alloy layer; Finally, metal level corrosion is formed to the metallic circuit designing, thereby make metal pad carry out electrical UNICOM by metallic circuit and the external world.In said structure, because the conductivity of copper is better than aluminium, the needed copper metal layer thickness of turning circuit will, much smaller than aluminum metal layer, therefore be used the integrated cost of copper metal to be less than aluminum metal.In addition, for the sputter of the larger TSV deep hole of the degree of depth, the spreadability of copper metal is better than aluminum metal, thereby has also improved the encapsulation yield of high-aspect-ratio TSV deep hole.
Accompanying drawing explanation
Fig. 1 is the utility model structural representation;
Fig. 2 is A place structure for amplifying schematic diagram in Fig. 1;
Fig. 3 be in Fig. 2 B-B to cross-sectional view;
Fig. 4 is C place structure for amplifying schematic diagram in Fig. 3.
By reference to the accompanying drawings, make the following instructions:
1---chip unit 2---TSV deep hole
3---metal pad 4---insulating barrier
5---window 6---barrier layer
7---copper metal layer 8---metallic circuit
9---contact point 10---silicon layer
Embodiment
As Fig. 1, Fig. 2, shown in Fig. 3 and Fig. 4, a kind of TSV encapsulating structure of wafer stage chip, comprise several chip units 1, each chip unit comprises silicon layer 10, on described silicon layer, be formed with several TSV deep holes 2, the below, bottom of each TSV deep hole is formed with metal pad 3, and the maximum gauge of described TSV deep hole is less than the minimum length of side of described metal pad, described silicon layer, on the bottom of described TSV deep hole and sidewall, be all coated with a layer insulating 4, on the insulating barrier covering on the bottom of described TSV deep hole, offer a window 5, on described insulating barrier and described window, cover and form a metal level, described metal level corrosion forms the metallic circuit 8 of design, described metal pad carries out electrical UNICOM by described metallic circuit and the external world.
Preferably, described TSV deep hole runs through described silicon layer, described TSV deep hole is equal a kind of in equal straight hole of the inclined hole that diminishes gradually to the diameter of its opening along its bottom and the diameter along its bottom to its opening, and the degree of depth of described TSV deep hole is not more than the thickness of described silicon layer.
Preferably, the diameter of described window is not more than the diameter of the bottom of described TSV deep hole; The degree of depth of described window is not less than the thickness of described insulating barrier.
Preferably, described metal level comprises one deck barrier layer 6 and layer of copper metal level 7, and described copper metal layer is positioned at a described barrier layer side of described insulating barrier dorsad.
Preferably, described metallic circuit is included in the first metallic circuit of forming on the insulating barrier of described silicon surface, the second metallic circuit forming on the insulating barrier of the sidewall of described TSV deep hole and the 3rd metallic circuit forming in described window; Described the first metallic circuit extends to form sets big or small circular contact point 9, described the second metallic circuit covers the insulating barrier on described sidewall, described the 3rd metallic circuit covers the insulating barrier on described bottom, and penetrate and cover described window, described metal pad carries out electrical UNICOM by described first, second, third metallic circuit and the external world.
Preferably, described barrier layer is titanium coating or CTB alloy layer.
The method for packing of the TSV encapsulating structure of the utility model wafer stage chip, comprises the steps:
1) provide the wafer that comprises chip unit described in several, each chip unit comprises silicon layer, on the surface of described silicon layer, be formed with several TSV deep holes, and below, the bottom of each TSV deep hole is formed with metal pad, and the minimum edge of described metal pad is grown up in the maximum gauge of described TSV deep hole;
2), by a kind of in physics and chemistry method, at described silicon layer, touch on the surface of outside air and cover a layer insulating, and described insulating barrier cover bottom and the sidewall of described TSV deep hole;
3) pass through at least one in physics and chemistry method, on the insulating barrier covering, offer a window on the bottom of described TSV deep hole, described metal pad can be contacted with the external world;
4) pass through at least one in physics and chemistry method, on the surface of the insulating barrier forming in step 3 and described window, deposition forms metal level, and described metal level comprises one deck barrier layer that first deposition forms and the layer of copper metal level that deposition forms on described barrier layer;
5) the formed metal level of step 4 is corroded into the metallic circuit of design, described metallic circuit is included in the first metallic circuit of forming on the insulating barrier of described silicon surface, the second metallic circuit forming on the insulating barrier of the sidewall of described TSV deep hole and the 3rd metallic circuit forming in described window; Described the first metallic circuit extends to form sets big or small circular contact point, described the second metallic circuit covers the insulating barrier on described sidewall, described the 3rd metallic circuit covers the insulating barrier on described bottom, and penetrate and cover described window, described metal pad carries out electrical UNICOM by described first, second, third metallic circuit and the external world;
Preferably, described barrier layer is titanium coating or CTB alloy layer.
Preferably, by the corrosion of photoetching development, liquid, with at least one in dry etching metal mode, the formed metal level of step 4 is corroded into the metallic circuit of design.
To sum up, the TSV encapsulating structure of the utility model wafer stage chip first, is all coated with a layer insulating on the silicon layer of chip wafer unit, the bottom of TSV deep hole and sidewall; Then, on the insulating barrier covering, offer a window on the bottom of TSV deep hole, on insulating barrier and window, cover to form a metal level, metal level comprise barrier layer and and copper metal layer, barrier layer can be a kind of in titanium coating and CTB alloy layer; Finally, metal level corrosion is formed to the metallic circuit designing, thereby make metal pad carry out electrical UNICOM by metallic circuit and the external world.In said structure, because the conductivity of copper is better than aluminium, the needed copper metal layer thickness of turning circuit will, much smaller than aluminum metal layer, therefore be used the integrated cost of copper metal to be less than aluminum metal.In addition, for the sputter of the larger TSV deep hole of the degree of depth, the spreadability of copper metal is better than aluminum metal, thereby has also improved the encapsulation yield of high-aspect-ratio TSV deep hole.
Above embodiment is with reference to accompanying drawing, and preferred embodiment of the present utility model is elaborated.Those skilled in the art is by above-described embodiment being carried out to modification or the change on various forms, but do not deviate from the situation of essence of the present utility model, within all dropping on protection range of the present utility model.
Claims (6)
1. the TSV encapsulating structure of a wafer stage chip, comprise several chip units (1), each chip unit comprises silicon layer (10), on described silicon layer, be formed with several TSV deep holes (2), the below, bottom of each TSV deep hole is formed with metal pad (3), and the maximum gauge of described TSV deep hole is less than the minimum length of side of described metal pad, described silicon layer, on the bottom of described TSV deep hole and sidewall, be all coated with a layer insulating (4), it is characterized in that: on the insulating barrier covering on the bottom of described TSV deep hole, offer a window (5), on described insulating barrier and described window, cover and form a metal level, described metal level corrosion forms the metallic circuit (8) of design, described metal pad carries out electrical UNICOM by described metallic circuit and the external world.
2. wafer stage chip TSV encapsulating structure according to claim 1, it is characterized in that: described TSV deep hole runs through described silicon layer, described TSV deep hole is equal a kind of in equal straight hole of the inclined hole that diminishes gradually to the diameter of its opening along its bottom and the diameter along its bottom to its opening, and the degree of depth of described TSV deep hole is not more than the thickness of described silicon layer.
3. wafer stage chip TSV encapsulating structure according to claim 2, is characterized in that: the diameter of described window is not more than the diameter of the bottom of described TSV deep hole; The degree of depth of described window is not less than the thickness of described insulating barrier.
4. wafer stage chip TSV encapsulating structure according to claim 3, is characterized in that: described metal level comprises one deck barrier layer (6) and layer of copper metal level (7), and described copper metal layer is positioned at a described barrier layer side of described insulating barrier dorsad.
5. wafer stage chip TSV encapsulating structure according to claim 4, is characterized in that: described metallic circuit is included in the first metallic circuit of forming on the insulating barrier of described silicon surface, the second metallic circuit forming on the insulating barrier of the sidewall of described TSV deep hole and the 3rd metallic circuit forming in described window; Described the first metallic circuit extends to form sets big or small circular contact point (9), described the second metallic circuit covers the insulating barrier on described sidewall, described the 3rd metallic circuit covers the insulating barrier on described bottom, and penetrate and cover described window, described metal pad carries out electrical UNICOM by described first, second, third metallic circuit and the external world.
6. wafer stage chip TSV encapsulating structure according to claim 4, is characterized in that: described barrier layer is titanium coating or CTB alloy layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420006299.7U CN203787413U (en) | 2014-01-06 | 2014-01-06 | Wafer level chip TSV (Through Silicon Via) packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420006299.7U CN203787413U (en) | 2014-01-06 | 2014-01-06 | Wafer level chip TSV (Through Silicon Via) packaging structure |
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| Publication Number | Publication Date |
|---|---|
| CN203787413U true CN203787413U (en) | 2014-08-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420006299.7U Expired - Lifetime CN203787413U (en) | 2014-01-06 | 2014-01-06 | Wafer level chip TSV (Through Silicon Via) packaging structure |
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| Country | Link |
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| CN (1) | CN203787413U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047628A (en) * | 2015-06-05 | 2015-11-11 | 苏州迈瑞微电子有限公司 | Wafer-level chip TSV packaging structure and packaging method thereof |
-
2014
- 2014-01-06 CN CN201420006299.7U patent/CN203787413U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105047628A (en) * | 2015-06-05 | 2015-11-11 | 苏州迈瑞微电子有限公司 | Wafer-level chip TSV packaging structure and packaging method thereof |
| CN105047628B (en) * | 2015-06-05 | 2017-08-22 | 苏州迈瑞微电子有限公司 | Wafer stage chip TSV encapsulating structures and its method for packing |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140820 |
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| CX01 | Expiry of patent term |