CN204022464U - Three-dimensional MEMS encapsulating structure - Google Patents
Three-dimensional MEMS encapsulating structure Download PDFInfo
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- CN204022464U CN204022464U CN201420357894.5U CN201420357894U CN204022464U CN 204022464 U CN204022464 U CN 204022464U CN 201420357894 U CN201420357894 U CN 201420357894U CN 204022464 U CN204022464 U CN 204022464U
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 148
- 239000002184 metal Substances 0.000 claims abstract description 148
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 78
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 78
- 239000010703 silicon Substances 0.000 claims abstract description 78
- 238000007789 sealing Methods 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- 238000002161 passivation Methods 0.000 claims abstract description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 6
- 238000003860 storage Methods 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 229910018503 SF6 Inorganic materials 0.000 claims description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 claims description 3
- 229960000909 sulfur hexafluoride Drugs 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 24
- 238000005538 encapsulation Methods 0.000 abstract description 17
- 230000008569 process Effects 0.000 abstract description 17
- 238000004806 packaging method and process Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 39
- 239000000463 material Substances 0.000 description 7
- 238000005260 corrosion Methods 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
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- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 2
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- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
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- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
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Abstract
The utility model discloses a kind of three-dimensional MEMS encapsulating structure, comprise MEMS chip, cover silicon plate and multiple functional chip, realized covering silicon plate is connected with the bonding of MEMS chip by metal salient point with sealing ring, encapsulation process is transplanted to and is covered on silicon plate, simultaneously by forming successively wired circuit at covering silicon backboard face, passivation layer, wired circuit and the first insulating barrier and form on wired circuit again and outwards penetrate the first insulating barrier and inwardly penetrate passivation layer and be electrically connected multiple metal guide pillars of wired circuit again, and by functional chip face-down bonding on corresponding metal guide pillar, the functional chip with difference in functionality can be carried out to vertical stacking encapsulation, form a kind of three-dimensional MEMS encapsulating structure, thereby reach the overall size that greatly reduces chip package, improve packaging efficiency, further shorten and postpone, reduce the object of noise and power consumption.
Description
Technical field
The utility model relates to a kind of semiconductor MEMS encapsulating structure, specifically relates to a kind of three-dimensional MEMS encapsulating structure.
Background technology
Along with social development, electronic product is tending towards miniaturization, multifunction, make product to encapsulation requirement also more and more higher, by original simplified package gradually to high density, high integrated future development.In MEMS chip package process, general structure is to adopt glass or silicon as overlay, grind at MEMS chip back, punching, make circuit, plant the encapsulation flow processs such as ball, like this in follow-up encapsulation journey, chip back can operating space limited, make this encapsulating structure be confined to circuit less, the simple chip of function, cannot realize three-dimension packaging structure, therefore, in the urgent need to a kind of overall package that can realize MEMS chip and difference in functionality chip of development and Design, and encapsulation volume reduces greatly, packaging efficiency is higher, postpone further to shorten, noise further reduces, power consumption reduces, the three-dimensional MEMS encapsulating structure that speed is faster and bandwidth strengthens.
Summary of the invention
In order to solve the problems of the technologies described above, the utility model proposes a kind of three-dimensional MEMS encapsulating structure, can realize covering silicon plate by metal salient point and sealing ring is connected with the bonding of MEMS chip, encapsulation process is transplanted to and is covered on silicon plate, carry out bonding by the wired circuit again and the functional chip that cover on silicon plate again, the functional chip with difference in functionality can be carried out to vertical stacking encapsulation, greatly reduce the overall size of chip package, improve packaging efficiency, further shorten and postpone, reduce noise and power consumption.
The technical solution of the utility model is achieved in that
A kind of three-dimensional MEMS encapsulating structure, comprise MEMS chip, cover silicon plate and multiple functional chip, the front of the front of described MEMS chip and described covering silicon plate is connected with a sealing ring and several metal salient point bondings for the PIN pin that is electrically connected described MEMS chip that are intervally arranged; The back side of described covering silicon plate is coated with one deck wired circuit, one deck passivation layer, one deck wired circuit and one deck the first insulating barrier more from inside to outside successively, described wired circuit is again provided with and outwards penetrates described the first insulating barrier and inwardly penetrate described passivation layer and be electrically connected multiple metal guide pillars of described wired circuit, and described functional chip face-down bonding is on corresponding metal guide pillar; The periphery of described covering silicon plate is provided with the conductive through hole corresponding with described metal salient point, and described conductive through hole is between described sealing ring and described metal salient point, and described conductive through hole is electrically connected described metal salient point and described wired circuit.
As further improvement of the utility model, described functional chip is at least one driving in class chip, storage class chip and logical calculated class chip, between described functional chip and described metal guide pillar, is filled with underfill.
As further improvement of the utility model, on the described metal guide pillar of part, be implanted with the ball for being electrically connected with the external world.
As further improvement of the utility model, described passivation layer is negative photoresist.
As further improvement of the utility model, described wired circuit again and described metal guide pillar are multiple layer metal, first layer metal is wherein the alloy of a kind of or at least two kinds of metals in titanium, aluminium, copper and gold, and the second metal level being covered on this first layer metal is the alloy of a kind of or at least two kinds of metals in nickel, silver, titanium, cobalt, copper and metal.
As further improvement of the utility model, the front of the front of described MEMS chip and described covering silicon plate with a sealing ring and be intervally arranged several for the structure that is electrically connected the metal salient point bonding of PIN pin of described MEMS chip and is connected be: in the middle part of described MEMS chip positive, there is cavity, the positive perimeter rows of described MEMS chip is furnished with several PIN pin, the front of described MEMS chip is coated with first insulating layer on the region except cavity and PIN pin, described the second insulating barrier is provided with the first sealing ring of setting width and setting height that has that is positioned at described cavity periphery, on each described PIN pin, be manufactured with the first metal salient point, the front correspondence position of described covering silicon plate is provided with has the second sealing ring of setting width and setting height, on the front correspondence position of described covering silicon plate, be manufactured with the second metal salient point, between described the first sealing ring and described the second sealing ring, bonded seal is connected, and between described the first metal salient point and described the second metal salient point, bonding is electrically connected.
As further improvement of the utility model, described conductive through hole is included in one deck the 3rd insulating barrier and the layer of metal layer on the perforate forming on described covering silicon plate and the hole wall that covers successively described perforate, and described the 3rd insulating barrier and described metal level extend to the front and back of described covering silicon plate; The part that described metal level extends on the back side of described covering silicon plate forms described wired circuit; The part that described metal level extends on the front of described covering silicon plate conducts with described the second metal salient point; Cover in the described perforate after described metal level and be filled with organic insulation.
As further improvement of the utility model, the straight hole that is shaped as upper and lower opening equal diameters of described conductive through hole or upper and lower opening inclined hole not etc., and the radial section of described conductive through hole is circular square or oval.
As further improvement of the utility model, the positive middle part of described covering silicon plate inside contracts and forms an indent, and described indent is positioned at described the second sealing ring, and described indent is trapezoidal or rectangle or semicircle along the axial cross section of described conductive through hole.
As further improvement of the utility model, described indent and described cavity form a cavity, are vacuum or the gas that is filled with setting pressure in described cavity; While being filled with gas in described cavity, described gas is the one in nitrogen, helium, sulfur hexafluoride and silane.
The beneficial effects of the utility model are: the utility model provides a kind of three-dimensional MEMS encapsulating structure and method for packing thereof, be connected with the bonding of the first metal salient point in MEMS chip front side by the second metal salient point covering on silicon plate front, and the second sealing ring covering on silicon plate front is connected with the bonded seal of the first sealing ring in MEMS chip front side, can realize the bonding packaging that covers silicon plate and MEMS chip, by covering the conductive through hole that forms this wired circuit of electrical connection and the second metal salient point on silicon plate, can realize the object that electrical connection covers the wired circuit on silicon plate and the PIN pin on MEMS chip, simultaneously by forming successively wired circuit, passivation layer, wired circuit, the first insulating barrier and form and outwards penetrate the first insulating barrier and inwardly penetrate passivation layer and be electrically connected multiple metal guide pillars of wired circuit again covering silicon backboard face on wired circuit again, and by functional chip face-down bonding on corresponding metal guide pillar, can realize the object of electrical connection functional chip and metal level, hence one can see that, the utility model has been avoided processing at MEMS chip back, can realize covering silicon plate by metal salient point and sealing ring is connected with the bonding of MEMS chip, encapsulation process is transplanted to and is covered on silicon plate, again by form passivation layer on covering silicon backboard face, on passivation layer, form again wired circuit and metal guide pillar, face-down bonding functional chip on metal guide pillar, the functional chip with difference in functionality can be carried out to vertical stacking encapsulation, after realizing wafer scale MEMS encapsulation, with subsequent logic computing chip, storage chip, drive the integration of the functional chips such as chip, improve a kind of three-dimensional MEMS encapsulating structure, thereby reach the overall size that greatly reduces chip package, improve packaging efficiency, further shorten and postpone, reduce the object of noise and power consumption.
Brief description of the drawings
Fig. 1 is MEMS chip cross section structure schematic diagram in the utility model;
Fig. 2 covers silicon plate cross section structure schematic diagram in the utility model;
Fig. 3 is the front view that in Fig. 2, arrow S points to;
Fig. 4 is functional chip cross section structure schematic diagram in the utility model;
Fig. 5 is that the utility model covers the cross section structure schematic diagram after silicon plate, MEMS chip, the connection of functional chip bonding.
By reference to the accompanying drawings, make the following instructions:
A---MEMS chip; B---cover silicon plate;
C---functional chip;
1---indent; 2---perforate;
3---the 3rd insulating barrier; 4---metal level;
5---passivation layer; 6---the first metal salient point;
6 '---the second metal salient point; 7---PIN pin;
8---organic insulation; 9---metal guide pillar;
10---the first sealing ring; 10 '---the second sealing ring;
11---the first insulating barrier; 12---gas;
13---ball; 14---underfill;
15---the second insulating barrier; 16---cavity.
Detailed description of the invention
A kind of exemplary embodiments of the present utility model, as shown in Figure 5, Fig. 1, Fig. 2 are respectively the structural representations of covering silicon plate, MEMS chip and functional chip before pressing is connected with Fig. 4, Fig. 5 is the overall three-dimensional structure of three after pressing and Flip Chip Bond Technique, and Fig. 3 is the front view that in Fig. 2, arrow S points to.Before pressing, need MEMS chip and cover silicon plate to do some PROCESS FOR TREATMENT.
As shown in Figure 5, a kind of three-dimensional MEMS encapsulating structure, comprises MEMS chip A, covers silicon plate B and multiple functional chip C.
Referring to Fig. 1, the positive middle part of described MEMS chip has cavity 16, the positive perimeter rows of described MEMS chip is furnished with several PIN pin 7, the front of described MEMS chip is coated with first insulating layer 15 on the region except cavity and PIN pin, and this second insulating barrier is used for isolating the silicon on MEMS chip, prevents short circuit, the material of the second insulating barrier can be Inorganic Non-metallic Materials, as silica, can be also insulating polymeric material, as photoresist etc.Described the second insulating barrier is provided with the first sealing ring 10 of setting width and setting height that has that is positioned at described cavity periphery, on each described PIN pin, is manufactured with the first metal salient point 6; Conventionally this first sealing ring width is more than 10 μ m, and first metal salient point at this first sealing ring and edge will separate certain distance, and concrete width is formulated according to MEMS die size.
Referring to Fig. 2 and Fig. 3, the position of corresponding the first sealing ring 10 in the front of described covering silicon plate be provided with have set the second sealing ring 10 of width and setting height ', on corresponding the first metal salient point 6 positions, the front of described covering silicon plate, be manufactured with the second metal salient point 6 ', the back side of described covering silicon plate is coated with one deck wired circuit, one deck passivation layer 5, one deck wired circuit and one deck the first insulating barrier 11 more from inside to outside successively, by covering one deck the first insulating barrier 11 on wired circuit again, to prevent the metal oxidized corrosion of wired circuit again.Described wired circuit is again provided with and outwards penetrates described the first insulating barrier and inwardly penetrate described passivation layer and be electrically connected multiple metal guide pillars 9 of described wired circuit, the periphery of described covering silicon plate is provided with the conductive through hole corresponding with described metal salient point, and described conductive through hole is between described sealing ring and described metal salient point, and described conductive through hole is electrically connected described metal salient point and described wired circuit.
Referring to Fig. 5, covering silicon plate B and the MEMS chip A with conductive through hole carry out pressing in gas 12 atmosphere with setting pressure, make the first sealing ring 10 and the second sealing ring 10 ' between be tightly connected, the first metal salient point 6 and the second metal salient point 6 ' between bonding be electrically connected.This process is guided to the circuit of MEMS chip A at the back side that covers silicon plate after PIN pin 7 is connected with metal level 4 by metal salient point (6,6 '); Described functional chip C face-down bonding, on corresponding metal guide pillar, forms a kind of three-dimensional MEMS encapsulating structure, and this encapsulating structure has reduced encapsulated space greatly, and the chip of formation is also more complicated, and function is also more diversified.
Referring to Fig. 4, preferred, described functional chip is at least one driving in class chip, storage class chip and logical calculated class chip, between described functional chip and described metal guide pillar, is filled with underfill 14.
Preferably, on the described metal guide pillar of part, be implanted with the ball 13 for being electrically connected with the external world.Complete by planting ball the signal of telecommunication window being connected with the external world afterwards as follow-up whole three-dimensional MEMS chip package, realize wired circuit and extraneous being electrically connected.
Preferably, described passivation layer is negative photoresist.
Preferably, described wired circuit again and described metal guide pillar are multiple layer metal, first layer metal is wherein the alloy of a kind of or at least two kinds of metals in titanium, aluminium, copper and gold, and the second metal level being covered on this first layer metal is the alloy of a kind of or at least two kinds of metals in nickel, silver, titanium, cobalt, copper and metal.
Preferably, described conductive through hole is included in one deck the 3rd insulating barrier 3 and the layer of metal layer 4 on the perforate 2 forming on described covering silicon plate and the hole wall that covers successively described perforate, and described the 3rd insulating barrier and described metal level extend to the front and back of described covering silicon plate; Cause short circuit or open circuit to prevent the oxidized corrosion of metal level 4 by cover one deck the 3rd insulating barrier on metal level.The part that described metal level extends on the back side of described covering silicon plate forms described wired circuit; The part that described metal level extends on the front of described covering silicon plate conducts with described the second metal salient point; Cover in the described perforate after described metal level and be filled with organic insulation 8, protect the not oxidized corrosion of metal level 4 on the hole wall of perforate with this.Concrete implementing process is the layer of metal layer 4 covering on the 3rd insulating barrier 3, and through gluing, photoetching, develops, and the series of process steps such as etching are by this metal layer pattern processing.After forming pattern, carry out chemical plating, after chemical plating completes, with organic insulation 8, perforate 2 is filled, protect the not oxidized corrosion of metal level on hole wall with this.
Preferably, the straight hole that is shaped as upper and lower opening equal diameters of described conductive through hole or upper and lower opening inclined hole not etc., and the radial section of described conductive through hole is circular square or oval.
Preferably, described metal level 4 is single-layer metal, and the material of described metal level 4 is aluminium or copper.
Preferably, described metal level 4 is multiple layer metal, wherein, the material of first layer metal is the alloy of a kind of in titanium, aluminium and copper or at least two kinds, and the material that is covered in the second layer metal on first layer metal is the alloy of a kind of in nickel, gold, silver, titanium, cobalt and copper or at least two kinds.
Preferably, described the first metal salient point 6 and described the second metal salient point 6 ' material be the alloy of a kind of in copper, tin, gold, silver, nickel and aluminium or at least two kinds.
Preferably, described the first sealing ring 10 and described the second sealing ring 10 ' material be to there is the metal of intensity of setting, this metal is copper or gold.
Preferably, between described the first sealing ring 10 and described the first metal salient point 6, and described the second sealing ring 10 ' and described the second metal salient point 6 ' between be filled with underfill.
Preferably, the positive middle part of described covering silicon plate inside contracts and forms an indent 1, described indent 1 be positioned at described the second sealing ring 10 ', and described indent 1 is trapezoidal or rectangle or semicircle along the axial cross section of described conductive through hole.
Preferably, described indent 1 forms a cavity with described cavity 16, in described cavity, be vacuum or the gas 12 that is filled with setting pressure, while being filled with the gas 12 of setting pressure in described cavity, described gas is the one in nitrogen, helium, sulfur hexafluoride and silane.
Referring to Fig. 5, when the front bonding of the front of described MEMS chip A and described covering silicon plate B, by reflow soldering process or or flip chip bonding hot pressing or ultrasonic technique by described the first metal salient point 6 and described the second metal salient point 6 ', and described the first sealing ring 10 and described the second sealing ring 10 ' weld; Described functional chip C is welded on the pad on corresponding metal guide pillar 9 by upside-down mounting reflow soldering process, and fills the gap between functional chip and the first insulating barrier with underfill 14.
Referring to Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5, a kind of method for packing of three-dimensional MEMS encapsulating structure, comprises the steps:
A, provide a MEMS chip A, the positive middle part of described MEMS chip has cavity 16, the positive perimeter rows of described MEMS chip is furnished with several PIN pin 7, the front of described MEMS chip is coated with first insulating layer 15 on the region except cavity and PIN pin, described the second insulating barrier is provided with the first sealing ring 10 of setting width and setting height that has that is positioned at described cavity periphery, is manufactured with the first metal salient point 6 on described PIN pin;
B, provide one for covering the covering silicon plate B of described MEMS chip, by photoetching process, on described covering silicon plate, etch perforate 2;
On c, the hole wall of perforate that forms at step b, cover one deck the 3rd insulating barrier 3, and extend to the front and back that covers silicon plate;
D, form at step c the 3rd above insulating barrier, cover layer of metal layer 4, and the part that described metal level is positioned on described covering silicon backboard face carries out patterned process, forms described wired circuit;
E, the perforate after steps d covering metal layer is filled with organic insulation 8, form conductive through hole;
F, the metal level forming in steps d are positioned in the part on described covering silicon backboard face and cover one deck passivation layer 5;
On g, the passivation layer that forms at step f, form one deck wired circuit and multiple metal guide pillar 9 that penetrates described passivation layer and be electrically connected described metal level again by electroplating rewiring;
On h, the wired circuit again that forms in step g, cover one deck the first insulating barrier 11, for preventing the oxidized corrosion of circuit.
I, the metal level forming in steps d be positioned in the part on the front of described covering silicon plate, make second metal salient point 6 corresponding with described the first metal salient point ';
Around j, the perforate that forms at step b, make have set second sealing ring 10 corresponding with described the first sealing ring of width and height ';
K, described MEMS chip is carried out to bonding with described covering silicon chip be connected, by reflow soldering process or or flip chip bonding hot pressing or ultrasonic technique by described the first metal salient point and described the second metal salient point, and described the first sealing ring and described the second sealing ring weld;
L, by upside-down mounting reflow soldering process, functional chip is welded on corresponding metal guide pillar, and fills the gap between described functional chip and described the first insulating barrier with underfill 14;
M, step g form metal guide pillar on pad on, plant ball 13.
Preferably, the front-side etch that is also included in described covering silicon plate goes out to have the step of setting volume indent 1.
To sum up, the utility model provides a kind of three-dimensional MEMS encapsulating structure and method for packing thereof, be connected with the bonding of the first metal salient point in MEMS chip front side by the second metal salient point covering on silicon plate front, and the second sealing ring covering on silicon plate front is connected with the bonded seal of the first sealing ring in MEMS chip front side, can realize the bonding packaging that covers silicon plate and MEMS chip, by covering the conductive through hole that forms this wired circuit of electrical connection and the second metal salient point on silicon plate, can realize the object that electrical connection covers the wired circuit on silicon plate and the PIN pin on MEMS chip, simultaneously by forming successively wired circuit, passivation layer, again wired circuit and the first insulating barrier and form on wired circuit again and outwards penetrate the first insulating barrier and inwardly penetrate passivation layer and be electrically connected multiple metal guide pillars of wired circuit covering silicon backboard face, and by functional chip face-down bonding on corresponding metal guide pillar, can realize the object of electrical connection functional chip and metal level, hence one can see that, the utility model has been avoided processing at MEMS chip back, can realize covering silicon plate by metal salient point and sealing ring is connected with the bonding of MEMS chip, encapsulation process is transplanted to and is covered on silicon plate, again by form passivation layer on covering silicon backboard face, on passivation layer, form again wired circuit and metal guide pillar, face-down bonding functional chip on metal guide pillar, the functional chip with difference in functionality can be carried out to vertical stacking encapsulation, after realizing wafer scale MEMS encapsulation, with subsequent logic computing chip, storage chip, drive the integration of the functional chips such as chip, a kind of three-dimensional MEMS encapsulating structure is provided, thereby reach the overall size that greatly reduces chip package, improve packaging efficiency, further shorten and postpone, reduce the object of noise and power consumption.
The utility model three-dimensional MEMS encapsulating structure is after wafer scale MEMS encapsulation, with subsequent logic computing chip, the technical process that the chips such as storage chip are integrated, main innovate point is covering silicon backboard face formation passivation layer, wired circuit and the first insulating barrier again, and form multiple metal guide pillars by plating mode, as the bridge being connected with difference in functionality chip and the external world, this encapsulating structure has not only reduced encapsulation volume effectively, the chip with difference in functionality can also be carried out to three-dimension packaging, and this encapsulating structure reduces the more integrated but process complexity of encapsulation.
Above embodiment is with reference to accompanying drawing, and preferred embodiment of the present utility model is elaborated.Those skilled in the art is by carrying out amendment or the change on various forms to above-described embodiment; or applied to the encapsulating structure of different MEMS chips; but do not deviate from the situation of essence of the present utility model, within all dropping on protection domain of the present utility model.
Claims (10)
1. a three-dimensional MEMS encapsulating structure, it is characterized in that: comprise MEMS chip (A), cover silicon plate (B) and multiple functional chip (C), the front of the front of described MEMS chip and described covering silicon plate is connected with a sealing ring and several metal salient point bondings for the PIN pin that is electrically connected described MEMS chip that are intervally arranged; The back side of described covering silicon plate is coated with one deck wired circuit, one deck passivation layer (5), one deck wired circuit and one deck the first insulating barrier (11) more from inside to outside successively, described wired circuit is again provided with and outwards penetrates described the first insulating barrier and inwardly penetrate described passivation layer and be electrically connected multiple metal guide pillars (9) of described wired circuit, and described functional chip face-down bonding is on corresponding metal guide pillar; The periphery of described covering silicon plate is provided with the conductive through hole corresponding with described metal salient point, and described conductive through hole is between described sealing ring and described metal salient point, and described conductive through hole is electrically connected described metal salient point and described wired circuit.
2. three-dimensional MEMS encapsulating structure according to claim 1, it is characterized in that: described functional chip is at least one driving in class chip, storage class chip and logical calculated class chip, between described functional chip and described metal guide pillar, is filled with underfill (14).
3. three-dimensional MEMS encapsulating structure according to claim 1, is characterized in that: on the described metal guide pillar of part (9), be implanted with the ball (13) for being electrically connected with the external world.
4. three-dimensional MEMS encapsulating structure according to claim 1, is characterized in that: described passivation layer (5) is negative photoresist.
5. three-dimensional MEMS encapsulating structure according to claim 1, it is characterized in that: described wired circuit again and described metal guide pillar are multiple layer metal, first layer metal is wherein the alloy of a kind of or at least two kinds of metals in titanium, aluminium, copper and gold, and the second metal level being covered on this first layer metal is the alloy of a kind of or at least two kinds of metals in nickel, silver, titanium, cobalt, copper and metal.
6. three-dimensional MEMS encapsulating structure according to claim 1, it is characterized in that: front one sealing ring of the front of described MEMS chip (A) and described covering silicon plate and be intervally arranged several for the structure that is electrically connected the metal salient point bonding of PIN pin of described MEMS chip and is connected be: in the middle part of described MEMS chip positive, there is cavity (16), the positive perimeter rows of described MEMS chip is furnished with several PIN pin (7), the front of described MEMS chip is coated with first insulating layer (15) on the region except cavity and PIN pin, described the second insulating barrier is provided with the first sealing ring (10) of setting width and setting height that has that is positioned at described cavity periphery, on each described PIN pin, be manufactured with the first metal salient point (6), the front correspondence position of described covering silicon plate is provided with has the second sealing ring (10 ') of setting width and setting height, on the front correspondence position of described covering silicon plate, be manufactured with the second metal salient point (6 '), between described the first sealing ring and described the second sealing ring, bonded seal is connected, and between described the first metal salient point and described the second metal salient point, bonding is electrically connected.
7. three-dimensional MEMS encapsulating structure according to claim 6, it is characterized in that: described conductive through hole is included in one deck the 3rd insulating barrier (3) and the layer of metal layer (4) on the perforate (2) forming on described covering silicon plate and the hole wall that covers successively described perforate, and described the 3rd insulating barrier and described metal level extend to the front and back of described covering silicon plate; The part that described metal level extends on the back side of described covering silicon plate forms described wired circuit; The part that described metal level extends on the front of described covering silicon plate conducts with described the second metal salient point; Cover and in the described perforate after described metal level, be filled with organic insulation (8).
8. three-dimensional MEMS encapsulating structure according to claim 6, it is characterized in that: the positive middle part of described covering silicon plate inside contracts and forms an indent (1), described indent is positioned at described the second sealing ring, and described indent is trapezoidal or rectangle or semicircle along the axial cross section of described conductive through hole.
9. three-dimensional MEMS encapsulating structure according to claim 8, is characterized in that: described indent (1) forms a cavity with described cavity (16), is vacuum or the gas (12) that is filled with setting pressure in described cavity; While being filled with gas in described cavity, described gas is the one in nitrogen, helium, sulfur hexafluoride and silane.
10. three-dimensional MEMS encapsulating structure according to claim 9, it is characterized in that: the straight hole that is shaped as upper and lower opening equal diameters of described conductive through hole or upper and lower opening inclined hole not etc., and the radial section of described conductive through hole is circular square or oval.
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| CN201420357894.5U CN204022464U (en) | 2014-06-30 | 2014-06-30 | Three-dimensional MEMS encapsulating structure |
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| CN201420357894.5U CN204022464U (en) | 2014-06-30 | 2014-06-30 | Three-dimensional MEMS encapsulating structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105174195A (en) * | 2015-10-12 | 2015-12-23 | 美新半导体（无锡）有限公司 | WLP (wafer-level packaging) structure and method for cavity MEMS (micro-electromechanical system) device |
| CN105236346A (en) * | 2015-11-13 | 2016-01-13 | 华天科技（昆山）电子有限公司 | MEMS chip packaging structure and manufacturing method thereof |
| CN105347291A (en) * | 2015-10-21 | 2016-02-24 | 华天科技（昆山）电子有限公司 | Packaging structure for transferring chip bonding stress and production method thereof |
| US9858954B1 (en) | 2016-10-25 | 2018-01-02 | Western Digital Technologies, Inc. | Magnetic recording head test fixture for heat assisted magnetic recording head |
| CN112530874A (en) * | 2020-12-02 | 2021-03-19 | 赛莱克斯微系统科技（北京）有限公司 | Three-dimensional wafer integrated structure, preparation method thereof and electronic equipment |
-
2014
- 2014-06-30 CN CN201420357894.5U patent/CN204022464U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105174195A (en) * | 2015-10-12 | 2015-12-23 | 美新半导体（无锡）有限公司 | WLP (wafer-level packaging) structure and method for cavity MEMS (micro-electromechanical system) device |
| CN105347291A (en) * | 2015-10-21 | 2016-02-24 | 华天科技（昆山）电子有限公司 | Packaging structure for transferring chip bonding stress and production method thereof |
| CN105236346A (en) * | 2015-11-13 | 2016-01-13 | 华天科技（昆山）电子有限公司 | MEMS chip packaging structure and manufacturing method thereof |
| CN105236346B (en) * | 2015-11-13 | 2017-09-26 | 华天科技（昆山）电子有限公司 | MEMS chip encapsulating structure and preparation method thereof |
| US9858954B1 (en) | 2016-10-25 | 2018-01-02 | Western Digital Technologies, Inc. | Magnetic recording head test fixture for heat assisted magnetic recording head |
| CN112530874A (en) * | 2020-12-02 | 2021-03-19 | 赛莱克斯微系统科技（北京）有限公司 | Three-dimensional wafer integrated structure, preparation method thereof and electronic equipment |
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