CN103400830B - Multilayer chiop stacked structure and its implementation - Google Patents
Multilayer chiop stacked structure and its implementation Download PDFInfo
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- CN103400830B CN103400830B CN201310333411.8A CN201310333411A CN103400830B CN 103400830 B CN103400830 B CN 103400830B CN 201310333411 A CN201310333411 A CN 201310333411A CN 103400830 B CN103400830 B CN 103400830B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Abstract
The invention discloses a kind of multilayer chiop stacked structure, at least comprise three layers of chip, comprise TSV in the chip of intermediate layer, outside at least one intermediate layer chip, region processing has the metal column penetrating dielectric layer, directly realizes the communication of non-adjacent layer.Also disclose the implementation method that two kinds of multilayer chiops are stacking, the present invention is while use TSV, region outside the chip of intermediate layer, make the vertical conduction passage penetrating dielectric layer, directly realize cross-layer communication, not only reduce the pressure of internal layer chip, also for system provides more freedom.
Description
Technical field
The present invention relates to micro-electronic manufacturing and sophisticated semiconductor encapsulation technology field, particularly a kind of multilayer chiop stacked structure and its implementation.
Background technology
Five ten years in the past, integrated circuit is according to famous " Moore law " high speed development, the integrated circuit feature size of current commercialization has reached 28nm magnitude, approach physics limit gradually, and integrated circuit all encounters the development bottleneck being difficult to go beyond in design, manufacture and cost etc.Three-dimensional integration technology is considered to one and surmounts mole effective technology of (MorethanMoore), it is by utilizing third dimension, use the perpendicular interconnection penetrating silicon substrate, realize the electric communication between multilayer chiop, improve the interconnect delay problem that planar integrated circuit faces.Three-dimensional integrated core is that multilayer chiop is stacking, and processes perpendicular interconnection passage, realizes the communication of multilayer chiop.
Realize the stacking mode that can use wafer-wafer of multilayer chiop, also the mode of chip-to-wafer can be used, when using the mode of wafer-wafer to realize chip-stacked, the size of each layer chip must be strict the same, if each layer rate of finished products is not good enough, can make stacking after rate of finished products very low, the rate of finished products of such as individual layer is 90%, then the rate of finished products of three level stack is exactly 0.9*0.9*0.9=0.729=72.9%.Adopt the stack manner of chip-to-wafer, not only each layer can select the chip of different size, and known non-defective unit chip (KnownGoodDie, KGD) can be selected to carry out stacking, can effectively ensure stacking rate of finished products.But existing implementation, realizes vertical communication by means of only the TSV in chip, when non-close on two-layer need communication time, then need design corresponding TSV in the chip of intermediate layer, this all brings great difficulty to system and intermediate layer chip manufacturing.Current mode is when system, take into full account cross-layer communication need, make special TSV passage in advance at intermediate core lamella, bring very large pressure to intermediate layer chip manufacture, also bring great difficulty to system, because need the design coordinating multilayer chiop simultaneously.
Summary of the invention
The invention provides a kind of degree of freedom improving cross-layer communication channel density, increase multilayer chiop communication channel, improve interconnection density, improve multilayer chiop stacked structure and its implementation of the stacking supply chain of TSV.
Technical scheme of the present invention is:
A kind of multilayer chiop stacked structure, at least comprise three layers of chip, comprise TSV in the chip of intermediate layer, outside at least one intermediate layer chip, region processing has the metal column penetrating dielectric layer, directly realizes the communication of non-adjacent layer.
An implementation method for multilayer chiop stacked structure, comprises the steps:
(1) processing metal welded disc and metal column in ground floor chip die;
(2) chip of the second layer with TSV is assembled;
(3) filled media layer is covered;
(4) thinning second layer TSV chip and dielectric layer, expose TSV and metal column;
(5) wiring layer (RDL) and metal solder dish is processed again;
(6) third layer chip is assembled.
The method of processing metal post is the mode of plating or routing.
Further, after (4) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(4) step, realize the stacking of more intermediate layers chip.
The implementation method of another kind of multilayer chiop stacked structure, comprises the steps:
(1) in ground floor chip die, second layer chip is assembled;
(2) filled media layer is covered;
(3) thinning second layer chip and dielectric layer;
(4) in chip, process TSV, and region processing penetrates the metal column of dielectric layer outside chip;
(5) wiring layer and micro convex point is processed again;
(6) third layer chip is assembled.
Further, after (5) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(5) step, realize the stacking of more intermediate layers chip.
Owing to have employed above technical scheme, the technological progress acquired by the present invention is as follows:
The present invention is while use TSV, and the region outside the chip of intermediate layer, makes the vertical conduction passage penetrating dielectric layer, can directly realize cross-layer communication, this not only lowers the pressure of internal layer chip, also for system provides more freedom.
Accompanying drawing explanation
Fig. 1-1 is the first step schematic diagram in the embodiment of the present invention 1;
Fig. 1-2 is the second step schematic diagram in the embodiment of the present invention 1;
Fig. 1-3 is the 3rd step schematic diagram in the embodiment of the present invention 1;
Fig. 1-4 is the 4th step schematic diagram in the embodiment of the present invention 1 and embodiment 2;
Fig. 1-5 is the 5th step schematic diagram in the embodiment of the present invention 1 and embodiment 2;
Fig. 1-6 is the 6th step schematic diagram in the embodiment of the present invention 1 and embodiment 2 is also multilayer chiop stacked structure schematic diagram of the present invention;
Fig. 2-1 is the first step schematic diagram of the embodiment of the present invention 2;
Fig. 2-2 is the second step schematic diagram of the embodiment of the present invention 2;
Fig. 2-3 is the 3rd step schematic diagram of the embodiment of the present invention 2.
Embodiment
Below in conjunction with accompanying drawing, the present invention is further elaborated.
A kind of multilayer chiop stacked structure, at least comprise three layers of chip, comprise TSV in the chip of intermediate layer, outside at least one intermediate layer chip, region processing has the metal column penetrating dielectric layer, directly realizes the communication of non-adjacent layer.
An implementation method for multilayer chiop stacked structure, comprising:
(1) processing metal welded disc and metal column in ground floor chip die;
(2) chip of the second layer with TSV is assembled;
(3) filled media layer is covered;
(4) thinning second layer TSV chip and dielectric layer, expose TSV and metal column;
(5) wiring layer (RDL) and metal solder dish is processed again;
(6) third layer chip is assembled.
The method of processing metal post is the mode of plating or routing.
Further, after (4) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(4) step, realize the stacking of more intermediate layers chip.The implementation method of another kind of multilayer chiop stacked structure, comprising:
(1) in ground floor chip die, second layer chip is assembled;
(2) filled media layer is covered;
(3) thinning second layer chip and dielectric layer;
(4) in chip, process TSV, and region processing penetrates the metal column of dielectric layer outside chip;
(5) wiring layer and micro convex point is processed again;
(6) third layer chip is assembled.
Further, after (5) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(5) step, realize the stacking of more intermediate layers chip.
Embodiment 1:
(1) see shown in Fig. 1-1, ground floor chip substrate 101 is processed chips welding dish 103 and metal column 104, the mode that processing mode is preferably electroplated, the mode that metal column 104 can use routing to form metal stud post simultaneously realizes, 102 is ground floor chip surface circuit layer, and 103 is the metal solder dish of ground floor chip surface, assembles for chip, the height of metal column 104 need mate with the final thickness of second layer chip, and height is preferably greater than the numerical value of 50um;
(2) see shown in Fig. 1-2, on the basis of ground floor chip, assembling second layer chip, described second layer chip internal is processed with TSV204 in advance; Second layer chip comprises substrate 201 simultaneously, surface circuit layer 202 and surperficial micro convex point 203; Second layer chip is assembled in ground floor chip substrate in the mode of face down, the mode of the preferred thermocompression bonding of assembling mode; Ground floor chip realizes being electrically connected by metal solder dish with second layer chip.
(3) see shown in Fig. 1-3, cover filled media material 205, this dielectric material preferred polymers material or molding material, as polyimides, moulding compound etc., cover second layer chip and the gap of filling outside second layer chip.
(4) see shown in Fig. 1-4, thinning second layer chip substrate 201 and dielectric layer material 205, expose the metal column 104 of TSV204 and the processing in ground floor chip substrate 101 being produced on second layer chip internal in advance;
(5) see shown in Fig. 1-5, process again wiring layer (RDL) and metal pad 206, for the assembling of third layer chip;
(6) see shown in Fig. 1-6, on the basis of second layer chip, assembling third layer chip, third layer chip comprises substrate 301, surface circuit layer 302 and surface metal welded disc 303, as micro convex point etc., third layer chip is assembled in second layer chip back in the mode of face down, the mode of preferred thermocompression bonding.If after (5) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(5) step, then can realize the stacking of more intermediate layers chip, what finally realize more than three layers is chip-stacked.
Embodiment 2:
(1) see shown in Fig. 2-1, second layer chipset is loaded in ground floor chip substrate 101; Ground floor chip substrate 101 is processed with surface circuit layer 102 and surface metal welded disc 103, as micro convex point etc., second layer chip substrate 201 is processed with surface circuit layer 202 and second layer chip surface metal solder dish 203, as micro convex point etc., second layer chip is assembled on ground floor chip in the mode of face down, the mode of preferred thermocompression bonding, final second layer chip realizes being electrically connected by surface metal Welding Structure with ground floor chip;
(2) see shown in Fig. 2-2, cover filled media material 205, this dielectric material preferred polymers material or molding material, as polyimides, moulding compound etc., this dielectric material covers second layer chip and the gap of filling outside second layer chip;
(3) see shown in Fig. 2-3, thinning second layer chip substrate 201 and cover second layer chip and fill the dielectric layer 205 of the external series gap of second layer chip;
(4) see shown in Fig. 1-4, processing TSV204 and metal column 104, TSV are processed to comprise and are carved hole, insulating layer deposition, the steps such as filled with conductive material, and metal column processing comprises dielectric layer hole etching, the steps such as filled with conductive material, final acquisition vertical conduction passage;
(5) see shown in Fig. 1-5, process again wiring layer (RDL) and pad 206, for the assembling of third layer chip;
(6) see shown in Fig. 1-6, on the basis of second layer chip, assembling third layer chip, third layer chip comprises substrate 301, surface circuit layer 302 and surface metal welded disc 303, as micro convex point etc., third layer chip is assembled in second layer chip back in the mode of face down, the mode of preferred thermocompression bonding.If after (5) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(5) step, then can realize the stacking of more intermediate layers chip, what finally realize more than three layers is chip-stacked.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention.Within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. an implementation method for multilayer chiop stacked structure, comprises the steps:
(1) processing metal welded disc and metal column in ground floor chip die;
(2) chip of the second layer with TSV is assembled;
(3) filled media layer is covered;
(4) thinning second layer TSV chip and dielectric layer, expose TSV and metal column;
(5) wiring layer (RDL) and metal solder dish is processed again;
(6) third layer chip is assembled.
2. the implementation method of multilayer chiop stacked structure according to claim 1, is characterized in that: the method for processing metal post is the mode of plating or routing.
3. the implementation method of multilayer chiop stacked structure according to claim 1, it is characterized in that, after (4) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(4) step, realize the stacking of more intermediate layers chip.
4. an implementation method for multilayer chiop stacked structure, comprises the steps:
(1) in ground floor chip die, second layer chip is assembled;
(2) filled media layer is covered;
(3) thinning second layer chip and dielectric layer;
(4) in chip, process TSV, and region processing penetrates the metal column of dielectric layer outside chip;
(5) wiring layer and micro convex point is processed again;
(6) third layer chip is assembled.
5. the implementation method of multilayer chiop stacked structure according to claim 4, it is characterized in that, after (5) step, using the stacked combination of ground floor chip and second layer chip as new ground floor chip die, repeat (1)-(5) step, realize the stacking of more intermediate layers chip.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103700639B (en) * | 2013-12-31 | 2017-09-01 | 矽力杰半导体技术(杭州)有限公司 | Package assembling and its manufacture method |
| WO2015136998A1 (en) | 2014-03-10 | 2015-09-17 | 三菱重工業株式会社 | Multi-chip module, on-board computer, sensor interface substrate, and multi-chip module manufacturing method |
| CN105609480B (en) * | 2015-12-24 | 2018-11-30 | 合肥矽迈微电子科技有限公司 | Stacked Die Packaging structure |
| CN105489578B (en) * | 2015-12-24 | 2019-03-05 | 合肥矽迈微电子科技有限公司 | Stacked Die Packaging structure |
| CN106783634B (en) * | 2016-12-26 | 2019-09-20 | 通富微电子股份有限公司 | One kind being fanned out to packaging and its packaging method |
| EP3869554A4 (en) * | 2018-11-09 | 2022-03-23 | Huawei Technologies Co., Ltd. | Chip integrated with at least two dies |
| CN110544673B (en) * | 2019-09-12 | 2021-03-19 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
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| CN101681903A (en) * | 2009-03-30 | 2010-03-24 | 香港应用科技研究院有限公司 | Electronic Packaging and preparation method thereof |
| CN102810527A (en) * | 2011-05-30 | 2012-12-05 | 三星电子株式会社 | Semiconductor package and fabrication method of the same |
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| US9219023B2 (en) * | 2010-01-19 | 2015-12-22 | Globalfoundries Inc. | 3D chip stack having encapsulated chip-in-chip |
| US8293578B2 (en) * | 2010-10-26 | 2012-10-23 | International Business Machines Corporation | Hybrid bonding techniques for multi-layer semiconductor stacks |
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| KR100723524B1 (en) * | 2006-01-27 | 2007-05-30 | 삼성전자주식회사 | Semiconductor device where erosion of dielectric is reduced during metal cmp process and fabrication method of the same |
| CN101681903A (en) * | 2009-03-30 | 2010-03-24 | 香港应用科技研究院有限公司 | Electronic Packaging and preparation method thereof |
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Application publication date: 20131120 Assignee: Jiangsu Xinde Semiconductor Technology Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2022980027357 Denomination of invention: Multilayer chip stack structure and its implementation Granted publication date: 20151209 License type: Common License Record date: 20221213 |
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