CN205177812U - Lateral wall and back have insulation protection's chip package structure - Google Patents
Lateral wall and back have insulation protection's chip package structure Download PDFInfo
- Publication number
- CN205177812U CN205177812U CN201520829489.3U CN201520829489U CN205177812U CN 205177812 U CN205177812 U CN 205177812U CN 201520829489 U CN201520829489 U CN 201520829489U CN 205177812 U CN205177812 U CN 205177812U
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- protective layer
- wafer
- insulating protective
- chip
- back side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model relates to a lateral wall and back have insulation protection's chip package structure, including the wafer, be equipped with the first insulation protective layer on the electrode surface of wafer, the first insulation protective layer is equipped with the breach in department of the electrode portion of switching on, the lateral wall and the back of wafer are equipped with the 2nd insulation protective layer, the 2nd insulation protective layer and an insulation protective layer be connected together. The utility model discloses can prevent that the chip from perhaps pasting the dress process because the exposed electric leakage that leads to in the lateral wall and the back is bad in the encapsulation.
Description
Technical field
The utility model relates to wafer encapsulation technology field, particularly relates to a kind of sidewall and the back side chip-packaging structure with insulation protection.
Background technology
Existing wafer level packaging technique, after chip cutting is separated, the silicon of its chip sides is directly in the environment exposed, because silicon is that semiconductor can cause chip to there is electric leakage inefficacy in follow-up encapsulation and packaging technology.The product of wire-bonding package technique often can cause the line of low bank and chip sidewall contact and cause leaking electricity losing efficacy under plastic packaging material punching press; Wafer stage chip encapsulation (CSP) product is in attachment reflux technique, and solder ball or electrode zone easily because solder(ing) paste number to be printed too much causes part scolding tin to climb above the exposed silicon of chip sidewall, cause chip to leak electricity; Or because inter-chip pitch is closer, after heating or backflow, cause the sidewall of chip or rear-face contact to cause to the conductor of other devices losing efficacy.
Especially for the product of very small dimensions wafer-level packaging, as the encapsulating products of 0402,0210,01005 equidimension, do not protect due to side and cause electric leakage inefficacy puzzlement never to solve.Because attachment process precision and stability limitation, and himself very light in weight of device, in surface mount process, the solder(ing) paste number to be printed of electrode is unstable, and backflow heating temperature is uneven, cause scolding tin easily to climb to chip sidewall and cause even short circuit of leaking electricity, cause chip attachment bad.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of sidewall and the back side chip-packaging structure with insulation protection, can prevent chip in encapsulation or attachment process because the exposed electric leakage caused of sidewall and the back side is bad.
The utility model solves the technical scheme that its technical problem adopts: provide a kind of sidewall and the back side with the chip-packaging structure of insulation protection; comprise wafer; the electrode surface of described wafer is provided with the first insulating protective layer; described first insulating protective layer is provided with breach at place of electrode conduction portion; the sidewall of described wafer and the back side are provided with the second insulating protective layer, and described second insulating protective layer and the first insulating protective layer connect together.
The thickness of described first insulating protective layer is 0.5-15 μm.
The thickness of described second insulating protective layer is 3-50 μm.
Described electrode conduction portion is provided with conductive circuit layer, and described conductive circuit layer is provided with the salient point for conducting electricity.
Beneficial effect
Owing to have employed above-mentioned technical scheme; the utility model compared with prior art; there is following advantage and good effect: the utility model can prevent chip in encapsulation or attachment process because the exposed electric leakage caused of sidewall and the back side is bad, can protect IC promote Die strength, improving product yield; wafer scale production can be carried out; efficiency is high, and packaging technology is simple, and technical difficulty is lower; packaging cost is low, and package thickness can be reduced to very thin.Because the back side of chip is protected completely by the second integrated insulating protective layer with side, wherein without any gap, therefore not easily sliver in manufacturing process.
Accompanying drawing explanation
Fig. 1 is the structural representation of the utility model first execution mode;
Fig. 2 is the structural representation of the utility model second execution mode;
Fig. 3-Fig. 6 is the manufacturing process figure of the utility model first execution mode;
Fig. 7-Figure 12 is the manufacturing process figure of the utility model second execution mode.
Embodiment
Below in conjunction with specific embodiment, set forth the utility model further.Should be understood that these embodiments are only not used in restriction scope of the present utility model for illustration of the utility model.In addition should be understood that those skilled in the art can make various changes or modifications the utility model, and these equivalent form of values fall within the application's appended claims limited range equally after the content of having read the utility model instruction.
First execution mode of the present utility model relates to a kind of sidewall and the back side chip-packaging structure with insulation protection; as shown in Figure 1; comprise wafer 100; the electrode surface of described wafer 100 is provided with the first insulating protective layer 200; described first insulating protective layer 200 is provided with breach at place of electrode conduction portion 101; the sidewall of described wafer 100 and the back side are provided with the second insulating protective layer 700, and described second insulating protective layer 700 and the first insulating protective layer 200 connect together.
Second execution mode of the present utility model relates to a kind of sidewall sidewall and the back side chip-packaging structure with insulation protection equally; it is roughly identical with the first execution mode; its difference is; as shown in Figure 2; described electrode conduction portion 101 is provided with conductive circuit layer 300, and described conductive circuit layer 300 is provided with the salient point 400 for conducting electricity.
The chip packaging method of the first execution mode of the present utility model, comprises the following steps:
Step one: make the first insulating protective layer 200 at the electrode surface of wafer 100; the thickness of the first insulating protective layer 200 is 0.5-15 μm; and be provided with breach at place of electrode conduction portion 101; by modes such as exposure imaging, laser ablation or wet etchings, electrode conduction portion is come out; wherein; scribe line is protected by the first insulating barrier 200, sees Fig. 3.
Step 2: precut in the scribe line area of wafer 100, cuts out the groove 500 with certain depth, and the degree of depth of groove is 15-500 μm, sees Fig. 4.
Step 3: carry out pad pasting 600 on the electrode surface of wafer 100, by abrasive disc technique by wafer 100 thinning back side to predetermined thickness, and allow single chips separate, see Fig. 5.
Step 4: make the second insulating protective layer 700, second insulating protective layer 700 at the back side of wafer 100 and sidewall and the first insulating protective layer 200 connects together, makes the side of wafer 100 and the back side completely by dielectric protection layer.Wherein, the second insulating protective layer 700 makes by modes such as printing, injection, spin coatings, sees Fig. 6.
Step 5: be separated with film 600 by wafer 100, obtains the chip-packaging structure of single the back side as shown in Figure 1 with insulation protection.
The chip packaging method of the second execution mode of the present utility model, comprises the following steps:
Step one: make the first insulating protective layer 200 at the electrode surface of wafer 100; the thickness of the first insulating protective layer 200 is 0.5-15 μm; and be provided with breach at place of electrode conduction portion 101; by modes such as exposure imaging, laser ablation or wet etchings, electrode conduction portion is come out; wherein; scribe line is protected by the first insulating barrier 200, sees Fig. 7.
Step 2: make conductive circuit layer 300 in electrode conduction portion 101, this conductive circuit layer 300 makes by the mode of sputtering etching, chemical deposition, printing or spraying, and this conductive circuit layer 300 can be also sandwich construction, sees Fig. 8.
Step 3: make the salient point 400 for conducting electricity in conductive circuit layer 300, salient point 400 can by chemical deposition, print or plant the modes such as ball and make, this salient point 400 can be single structure, also can be sandwich construction, its composition can be single metal, also can be metal alloy, see Fig. 9.
Step 4: precut in the scribe line area of wafer 100, cuts out the groove 500 with certain depth, and the degree of depth of groove is 15-500 μm, sees Figure 10.
Step 5: carry out pad pasting 600 on the electrode surface of wafer 100, by abrasive disc technique by wafer 100 thinning back side to predetermined thickness, and allow single chips separate, see Figure 11.
Step 6: make the second insulating protective layer 700, second insulating protective layer 700 at the back side of wafer 100 and sidewall and the first insulating protective layer 200 connects together, makes the side of wafer 100 and the back side completely by dielectric protection layer.Wherein, the second insulating protective layer 700 makes by modes such as printing, injection, spin coatings, sees Figure 12.
Step 7: be separated with film 600 by wafer 100, obtains the chip-packaging structure of single the back side as shown in Figure 2 with insulation protection.
Claims (4)
1. a sidewall and the back side are with the chip-packaging structure of insulation protection; comprise wafer (100); the electrode surface of described wafer (100) is provided with the first insulating protective layer (200); described first insulating protective layer (200) is provided with breach at electrode conduction portion (101) place; it is characterized in that; the sidewall of described wafer (100) and the back side are provided with the second insulating protective layer (700), and described second insulating protective layer (700) and the first insulating protective layer (200) connect together.
2. sidewall according to claim 1 and the back side are with the chip-packaging structure of insulation protection, it is characterized in that, the thickness of described first insulating protective layer (200) is 0.5-15 μm.
3. sidewall according to claim 1 and the back side are with the chip-packaging structure of insulation protection, it is characterized in that, the thickness of described second insulating protective layer (700) is 3-50 μm.
4. sidewall according to claim 1 and the back side are with the chip-packaging structure of insulation protection; it is characterized in that; described electrode conduction portion (101) is provided with conductive circuit layer (300), and described conductive circuit layer (300) is provided with the salient point (400) for conducting electricity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520829489.3U CN205177812U (en) | 2015-10-23 | 2015-10-23 | Lateral wall and back have insulation protection's chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520829489.3U CN205177812U (en) | 2015-10-23 | 2015-10-23 | Lateral wall and back have insulation protection's chip package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205177812U true CN205177812U (en) | 2016-04-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201520829489.3U Active CN205177812U (en) | 2015-10-23 | 2015-10-23 | Lateral wall and back have insulation protection's chip package structure |
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| CN (1) | CN205177812U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108597998A (en) * | 2017-09-30 | 2018-09-28 | 中芯集成电路（宁波）有限公司 | Wafer scale system encapsulating method and structure |
| CN112038301A (en) * | 2019-06-03 | 2020-12-04 | 华为技术有限公司 | Chip, electronic device and manufacturing method of chip |
| CN114361025A (en) * | 2022-03-21 | 2022-04-15 | 宁波芯健半导体有限公司 | GaN ultrathin chip fan-out type packaging structure and packaging method |
-
2015
- 2015-10-23 CN CN201520829489.3U patent/CN205177812U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108597998A (en) * | 2017-09-30 | 2018-09-28 | 中芯集成电路（宁波）有限公司 | Wafer scale system encapsulating method and structure |
| CN112038301A (en) * | 2019-06-03 | 2020-12-04 | 华为技术有限公司 | Chip, electronic device and manufacturing method of chip |
| CN114361025A (en) * | 2022-03-21 | 2022-04-15 | 宁波芯健半导体有限公司 | GaN ultrathin chip fan-out type packaging structure and packaging method |
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| GR01 | Patent grant |