CN202839738U - Micro-bump chip packaging structure - Google Patents
Micro-bump chip packaging structure Download PDFInfo
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- CN202839738U CN202839738U CN 201220506417 CN201220506417U CN202839738U CN 202839738 U CN202839738 U CN 202839738U CN 201220506417 CN201220506417 CN 201220506417 CN 201220506417 U CN201220506417 U CN 201220506417U CN 202839738 U CN202839738 U CN 202839738U
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- chip
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- surface passivation
- passivation layer
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Abstract
The utility model relates to a micro-bump chip packaging structure and belongs to the technical field of semiconductor packaging. The micro-bump chip packaging structure comprises a chip body, a chip pad, a chip surface passivation layer, a metal sputtering layer, a metal protection layer and a micro-bump, wherein the metal sputtering layer is arranged on the chip pad revealed through an opening of the chip surface passivation layer. The metal sputtering layer comprises a lower blocking layer and an upper seed layer. The metal protection layer is arranged on the seed layer of the metal sputtering layer and extends to all sides through the opening of the chip surface passivation layer. A shallow groove is formed in the front side of the metal protection layer, wherein the micro-bump is arranged in the shallow groove. The micro-bump comprises a metal pillar and a metal cap arranged at the top end of the metal pillar. The seed layer is an electroplate conducting layer of the metal protection layer and the micro-pump. Due to the fact that the metal protection layer protects the chip pad from being damaged by corrosion, the yield ratio and reliability of the packaging of semiconductor structures are improved.
Description
Technical field
The utility model relates to a kind of dimpling point chip-packaging structure, belongs to the semiconductor packaging field.
Background technology
Along with the development of electronic technology, the diversification of systemic-function, miniaturization are leading the development of trend.In order to satisfy the user to system's miniaturization, multi-functional requirement, the pin salient point of chip is also towards the future development of small size, narrow pitch, multi-convex point.Along with this development, a kind of miniature copper pillar bump more and more receives publicity, and adopt this dimpling dot structure not only can obtain very narrow pitch, and its signal transmission performance also is better than existing other bump structures.In order to produce more less salient points, and increase as far as possible the contact area of salient point and pad, with the stability of enhanced feature.That usually the size of salient point is made is also less than chip surface passivation layer opening, and therefore the dimpling point is positioned at the inside that passivation layer is windowed in this structure.This is just so that outside the aluminum pad on segment chip surface is exposed to, after carrying out chip in the road encapsulation, and the scaling powder corrosion failure that uses in the aggressive solvent that the aluminum pad of exposure is very easily used in the technique and the reflux course.In addition since aluminum pad contact with the direct of miniature copper post, pad can with copper post generation diffusion reaction, thereby cause yield loss and the reduction of the reliability in the follow-up use procedure problem of the encapsulation of rear road.
Summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, and a kind of dimpling point chip-packaging structure that is not damaged by corrosion, improves semiconductor packages yield and reliability with coat of metal, protection chip bonding pad is provided.
The utility model is achieved in that
A kind of novel dimpling point chip-packaging structure; it comprises chip body and chip bonding pad; described chip bonding pad is arranged on the front of chip body; it also comprises the chip surface passivation layer; the metal sputtering layer; coat of metal and dimpling point; described chip surface passivation layer covers the front of chip body and the periphery of chip bonding pad; the middle part of the chip surface passivation layer on the described chip bonding pad is provided with the chip surface passivation layer opening; described metal sputtering layer is arranged on the chip bonding pad that the chip surface passivation layer opening exposes; described metal sputtering layer comprises the Seed Layer on barrier layer and the upper strata of lower floor; described coat of metal be arranged on the Seed Layer of metal sputtering layer and from the chip surface passivation layer opening to around extend; form shallow rising as high as the banks in the front of coat of metal; described dimpling point is arranged in shallow the rising as high as the banks, and described dimpling point comprises metal column and is arranged on the metal cap on metal column top.
The size of described dimpling point is less than the size of chip surface passivation layer opening.
The diameter of described metal column is 10 ~ 30 μ m, height 15 ~ 50 μ m.
The size of described coat of metal is greater than the size of chip surface passivation layer opening.
Described Seed Layer is all the electroplated conductive layer of coat of metal and dimpling point.
Described metal sputtering layer is one or more layers.
The beneficial effects of the utility model are:
Even one or more layers barrier layer of sputter and Seed Layer on wafer; then on Seed Layer, adopt the mode of electroplating to deposit one or more layers metal coating at chip surface passivation layer opening exposed chip pad place, then produce required dimpling dot structure at coat of metal.By increasing coat of metal, promoted the scaling powder resistance of Copper column structure in reflux course of dimpling point, avoid simultaneously the destruction of being corroded property of pad solvent, thereby protected the aluminum pad that exposes.Because the existence on sputter barrier layer has also intercepted pad and contacted with the direct of coat of metal, avoid the diffusion of aluminium and copper in addition, promoted the reliability of dimpling dot structure.
Description of drawings
Fig. 1 is the schematic diagram of a kind of dimpling point chip-packaging structure of the utility model.
Wherein:
Chip surface passivation layer 103
Chip surface passivation layer opening 1031
Coat of metal 105
Shallowly rise as high as the banks 1051
Embodiment
Referring to Fig. 1, the utility model relates to a kind of dimpling point chip-packaging structure, and it comprises chip body 101, chip bonding pad 102, chip surface passivation layer 103, metal sputtering layer 104, coat of metal 105 and dimpling point 106.Described chip bonding pad 102 is arranged on the front of chip body 101.Described chip surface passivation layer 103 covers the front of chip body 101 and the periphery of chip bonding pad 102.The middle part of the chip surface passivation layer 103 on the described chip bonding pad 102 is provided with chip surface passivation layer opening 1031, described metal sputtering layer 104 is arranged on the chip bonding pad 102 that surperficial chip surface passivation layer opening 1031 exposes, and described metal sputtering layer 104 comprises the Seed Layer on barrier layer and the upper strata of lower floor.
Described coat of metal 105 be arranged on the Seed Layer of metal sputtering layer 104 and from chip surface passivation layer opening 1031 to around extend, form in the front of coat of metal 105 and shallowly rise as high as the banks 1051.The size of described coat of metal 105 is greater than the size of chip surface passivation layer opening 1031.
Described dimpling point 106 is arranged on shallow rising as high as the banks in 1051, and described dimpling point 106 comprises metal column 1061 and is arranged on the metal cap 1062 on metal column 1061 tops.The material of described metal column 1061 is copper.The material of described metal cap 1062 is that the size of tin or the described dimpling point 106 of ashbury metal is less than the size of chip surface passivation layer opening 1031.The diameter of described metal column 1061 is 10 ~ 30 μ m, height 15 ~ 50 μ m.Described Seed Layer is all the electroplated conductive layer of coat of metal 105 and dimpling point 106.
The implementation step of a kind of dimpling point chip-packaging structure of the utility model is:
1) on the chip bonding pad 102 that chip surface passivation layer 103 and the chip surface passivation layer opening 1031 of crystal column surface exposes, utilize one or more layers metal sputtering layer 104 of mode uniform fold of sputter, described metal sputtering layer 104 comprises barrier layer and Seed Layer.
2) adopt photoetching process, evenly be coated with the last layer photoresist at crystal column surface first, form the figure opening by exposure and visualization way at the crystal column surface photoresist again.
3) electroplate out coat of metal 105 at the figure opening part that forms.
4) utilize degumming process to remove photoresist.
5) recycling photoetching process, the first plating at crystal column surface goes out evenly to be coated with the last layer photoresist on the coat of metal 105, forms the figure opening by exposure and visualization way at the crystal column surface photoresist.
6) the recycling plating mode is electroplated out the metal column 1061 of required dimpling point 106 and the metal cap 1062 on metal column 1061 tops.
7) by remove photoresist, etching process, dimpling is put photoresist unnecessary on 106 outsides, the wafer and metal sputtering layer 104 is removed, finally produce needed dimpling point chip-packaging structure with coat of metal.
Claims (6)
1. dimpling point chip-packaging structure; comprise chip body (101) and chip bonding pad (102); described chip bonding pad (102) is arranged on the front of chip body (101); it is characterized in that: also comprise chip surface passivation layer (103); metal sputtering layer (104); coat of metal (105) and dimpling point (106); described chip surface passivation layer (103) covers the front of chip body (101) and the periphery of chip bonding pad (102); the middle part of the chip surface passivation layer (103) on the described chip bonding pad (102) is provided with chip surface passivation layer opening (1031); described metal sputtering layer (104) is arranged on the chip bonding pad (102) that chip surface passivation layer opening (1031) exposes; described metal sputtering layer (104) comprises the Seed Layer on barrier layer and the upper strata of lower floor; described coat of metal (105) be arranged on the Seed Layer of metal sputtering layer (104) and from chip surface passivation layer opening (1031) to around extend; form shallow rising as high as the banks (1051) in the front of coat of metal (105); described dimpling point (106) is arranged in shallow the rising as high as the banks (1051), and described dimpling point (106) comprises metal column (1061) and is arranged on the metal cap (1062) on metal column (1061) top.
2. a kind of dimpling point chip-packaging structure according to claim 1, it is characterized in that: the size of described dimpling point (106) is less than the size of chip surface passivation layer opening (1031).
3. a kind of dimpling point chip-packaging structure according to claim 1, it is characterized in that: the diameter of described metal column (1061) is 10 ~ 30 μ m, height 15 ~ 50 μ m.
4. a kind of dimpling point chip-packaging structure according to claim 1, it is characterized in that: the size of described coat of metal (105) is greater than the size of chip surface passivation layer opening (1031).
5. a kind of dimpling point chip-packaging structure according to claim 1 is characterized in that: described Seed Layer is all the electroplated conductive layer of coat of metal (105) and dimpling point (106).
6. a kind of dimpling point chip-packaging structure according to claim 1 is characterized in that: described metal sputtering layer (104) is one or more layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220506417 CN202839738U (en) | 2012-09-29 | 2012-09-29 | Micro-bump chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220506417 CN202839738U (en) | 2012-09-29 | 2012-09-29 | Micro-bump chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202839738U true CN202839738U (en) | 2013-03-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220506417 Expired - Lifetime CN202839738U (en) | 2012-09-29 | 2012-09-29 | Micro-bump chip packaging structure |
Country Status (1)
| Country | Link |
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| CN (1) | CN202839738U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113383A (en) * | 2021-04-09 | 2021-07-13 | 颀中科技（苏州）有限公司 | Metal bump structure and manufacturing method |
-
2012
- 2012-09-29 CN CN 201220506417 patent/CN202839738U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113113383A (en) * | 2021-04-09 | 2021-07-13 | 颀中科技（苏州）有限公司 | Metal bump structure and manufacturing method |
| WO2022214058A1 (en) * | 2021-04-09 | 2022-10-13 | 颀中科技（苏州）有限公司 | Metal bump structure and manufacturing method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130327 |
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| CX01 | Expiry of patent term |