CN103165413B - A kind of method removing cull - Google Patents
A kind of method removing cull Download PDFInfo
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- CN103165413B CN103165413B CN201110424678.9A CN201110424678A CN103165413B CN 103165413 B CN103165413 B CN 103165413B CN 201110424678 A CN201110424678 A CN 201110424678A CN 103165413 B CN103165413 B CN 103165413B
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Abstract
The invention discloses a kind of method removing cull, for removing at the cull carrying out staying in thickening process to the press welding block in chip, after adopting described the first metal layer and described second metal level carried out alloying, again described second metal level is processed, and in order to solve after described the first metal layer and described second metal level carry out alloying, described second metal level is carried out to the problem of the more difficult aligning of photoetching, adopt and described the first metal layer and described passivation layer are etched, form the superposition mark of consistent opening, carry out the technical scheme of photoetching and etching again, effectively avoid exist in prior art in the technical problem carrying out leaving in thickening process cull contaminated equipment to the press welding block in chip, and then reach when equipment of bringing into chip processes, can not contaminated equipment, the technique effect of equipment coefficient of losses can be reduced.
Description
Technical field
The present invention relates to semiconductor chip and manufacture field, particularly relating to a kind of method removing cull, for removing at the cull carrying out staying in thickening process to the press welding block in chip.
Background technology
In semiconductor chip manufacture field, due to the development of encapsulation technology, traditional gold thread encapsulation or and aluminum steel encapsulation can not meet present encapsulation requirement, and copper cash encapsulation has low-resistivity, low price, high thermal conductance due to copper cash itself, make the application of this encapsulation technology more and more extensive.
For meeting the requirement of copper cash encapsulation, in chip, the metal layer thickness of press welding block requires also corresponding increase, in order to make the metal level of press welding block in chip thicken, have employed multiple thickening technology.
In traditional chip, the metal level process for upsetting of press welding block mainly, after its passivation layer carries out etching processing, sputter layer of metal layer again on this passivation layer, then by gluing exposure imaging technology, Al beyond pressure welding point region is etched away, again press welding block in chip is removed photoresist process, finally the two metal layers of the passivation layer upper and lower surface on press welding block in chip is carried out Alloying Treatment, reach the effect that local thickeies the metal level of press welding block in chip.
But the present inventor is realizing in process of the present invention, finding that such scheme exists following technical problem:
In traditional chip, press welding block manufacture craft can make some lines close quarters such as anti-electrostatic protecting structure region in chip leave cull in manufacturing process; even if replacing photoresist or employing are removed photoresist, cull all can not remove by solution completely; unclean owing to removing photoresist; and then by when in chip, press welding block brings equipment into; can pollute equipment, occur the technical problem causing equipment to use.
Summary of the invention
The invention provides a kind of method removing cull; for removing at the cull carrying out staying in thickening process to the press welding block in chip; and then exist in solution prior art owing to leaving cull in some lines close quarters such as anti-electrostatic protecting structure region in chip, and then cause the problem of chip contaminated equipment.
The invention provides a kind of method removing cull, for removing at the cull carrying out staying in thickening process to the press welding block in chip, described method specifically comprises: be that the first metal layer of d1 and the second metal level carry out Alloying Treatment to thickness, and the first metal layer of at least one the first opening part corresponding and described second metal level are combined closely;
Photoresist layer is formed at described second metal level upper surface;
By photoetching at described photoresist layer quantity of formation second opening identical with the first opening, in described second opening, the position of each second opening is vertically corresponding with each first opening in described first opening;
Along described second layer on surface of metal corresponding to each second opening vertically downward, by etching, part second metal level in described second opening is removed, for each second opening forms the second bottom surface.
Optionally, described first opening is that described the first metal layer is formed through over etching, and wherein, the described first opening degree of depth is d1, width is w1, and each first opening has the first bottom surface.
Optionally, the lower surface of described the first metal layer upper surface and described second metal level has the passivation layer that thickness is d2.
Optionally, described is that the first metal layer of d1 and the second metal level carry out Alloying Treatment to thickness, make before the first metal layer of at least one the first opening part corresponding and described second metal level combine closely, specifically also comprise: by sputtering on described passivation layer, form the second metal level, wherein, described second metal level is formed at described passivation layer upper surface, and the 3rd opening that quantity of formation is identical with described first opening, in described 3rd opening, the position of each 3rd opening is vertically corresponding with each first opening in described first opening, each 3rd opening has the 3rd bottom surface, described 3rd bottom surface and described first bottom surface are positioned at different level.
Optionally, described passing through on described passivation layer sputters, before forming the second metal level, specifically also comprise: be the passivation layer of d2 by being etched in the thickness of described the first metal layer upper surface, at the 4th opening that the upper surface quantity of formation of described the first metal layer is identical with described first opening, in described 4th opening, the position of each 4th opening is vertically corresponding with each first opening at least one first opening described, wherein, described 4th opening has the 4th bottom surface, and described 4th bottom surface and described first bottom surface are positioned at same level.
Optionally, described 3rd bottom surface and described second bottom surface are positioned at same level.
Optionally, by process of removing photoresist, remove the cull in each 4th opening in described 4th opening, and described photoresist layer.
Optionally, the material of described the first metal layer is specially: Al, Cu, albronze or Al-Si-Cu alloy.
Optionally, the material of described second metal level is specially: Al, Cu, albronze or Al-Si-Cu alloy.
Optionally, the width of described 3rd opening is w2; Wherein, described w2 is less than or equal to described w1.
There is in technique scheme following technique effect or advantage:
In the present invention, technical scheme is by after adopting described the first metal layer and described second metal level being carried out alloying, again described second metal level is processed, and in order to solve after described the first metal layer and described second metal level carry out alloying, described second metal level is carried out to the problem of the more difficult aligning of photoetching, adopt and described the first metal layer and described passivation layer are etched, form the superposition mark of consistent opening, carry out the technical scheme of photoetching and etching again, effectively avoid exist in prior art in the technical problem carrying out leaving in thickening process cull contaminated equipment to the press welding block in chip, and then reach when equipment of bringing into chip processes, can not contaminated equipment, the technique effect of equipment coefficient of losses can be reduced.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that the embodiment of the present invention removes cull;
Fig. 2 is that the embodiment of the present invention is to the structure chart after the first metal layer process in chip;
Fig. 3 is that the embodiment of the present invention is to the structure chart after passivation layer process in chip;
Fig. 4 is the structure chart after the embodiment of the present invention sputters one deck second metal level over the passivation layer;
Fig. 5 is the structure chart that the embodiment of the present invention forms photoresist layer on the second metal level;
Fig. 6 is that the embodiment of the present invention carries out the structure chart after photoetching to photoresist layer;
Fig. 7 is the structure chart after the embodiment of the present invention etches photoresist layer.
Embodiment
Can effectively avoid some lines close quarters in chip to leave cull as anti-electrostatic protecting structure region leaving cull to provide; and then not contaminated equipment reduce the implementation of equipment coefficient of losses; embodiments provide a kind of method removing cull; below in conjunction with Figure of description, embodiments of the invention are described; be to be understood that; embodiment described herein, only for instruction and explanation of the present invention, is not intended to limit the present invention.And when not conflicting, the embodiment in the present invention and the feature in embodiment can combine mutually.
With reference to figure 1, remove the flow chart of the method for cull for the embodiment of the present invention is a kind of.
Step 101, is that the first metal layer of d1 and the second metal level carry out Alloying Treatment to thickness, the first metal layer of at least one the first opening part corresponding and described second metal level is combined closely.
Wherein, with reference to figure 2, the first opening is that described the first metal layer is formed through over etching, and wherein, the described first opening degree of depth is d1, width is w1, and each first opening has the first bottom surface.
The lower surface of described the first metal layer upper surface and described second metal level has the passivation layer that thickness is d2.
Wherein, the material of the first metal layer can adopt Al, Cu, albronze or Al-Si-Cu alloy, and in embodiments of the present invention, the material of the first metal layer adopts Al, be to be understood that, Al metal material listed is herein only the metal material that the present embodiment adopts, and also can select other metal material according to the embodiment of the present invention, can consider cost and the optimum efficiency that can reach in conjunction with various metal material and determine to adopt which kind of material in practical application.
Before step 101, can to the process of described passivation layer well in advance, with reference to figure 3, be the passivation layer of d2 by being etched in the thickness of described the first metal layer upper surface, at the 4th opening that the upper surface quantity of formation of described the first metal layer is identical with described first opening, in described 4th opening, the position of each 4th opening is vertically corresponding with each first opening at least one first opening described, wherein, described 4th opening has the 4th bottom surface, described 4th bottom surface and described first bottom surface are positioned at same level, described 4th bottom surface and described 3rd bottom surface are positioned at different level.
After handling passivation layer well, can process the second metal level, with reference to figure 4, by sputtering on described passivation layer, form the second metal level, wherein, described second metal level is formed at described passivation layer upper surface, and the 3rd opening that quantity of formation is identical with described first opening, in described 3rd opening, the position of each 3rd opening is vertically corresponding with each first opening in described first opening, each 3rd opening has the 3rd bottom surface, and described 3rd bottom surface and described first bottom surface are positioned at different level.
Step 102, forms photoresist layer at described second metal level upper surface.
With reference to figure 5 be second metal level upper surface formed photoresist layer.
Step 103, by photoetching at described photoresist layer quantity of formation second opening identical with the first opening, in described second opening, the position of each second opening is vertically corresponding with each first opening in described first opening.
With reference to figure 6 for after carrying out photoetching to described photoresist layer, in the quantity of the second opening that described photoresist layer is formed, identical with described first opening.
Wherein, in second opening, the position of each second opening is vertically corresponding with the first opening each in the first opening, the second opening described by Fig. 6 is greater than the 3rd opening, and the second A/F also can equal the 3rd opening, can be less than or equal to the 4th opening, the concrete value of the second openings of sizes is determined according to actual conditions.
Step 104, along described second layer on surface of metal corresponding to each second opening vertically downward, by etching, removes part second metal level in described second opening, for each second opening forms the second bottom surface.
Described 3rd bottom surface and described second bottom surface are positioned at same level, as shown in Figure 7.
In actual application, for semiconductor fabrication, described etching is divided into wet etching and dry etching usually, and the embodiment of the present application adopts wet etching.Certainly, two kinds of methods respectively have feature, can need to come according to actual conditions the method for selective etching.The mainly impact of environmentally temperature, humidity, and these methods because of usually selective etching of the operating pressure selected and power.
The embodiment of the present invention has following technique effect or advantage:
In the present invention, technical scheme is by after adopting described the first metal layer and described second metal level being carried out alloying, again described second metal level is processed, and in order to solve, after carrying out alloying, described second metal level is carried out to the problem of the more difficult aligning of photoetching, adopt and described the first metal layer and described passivation layer are etched, form the superposition mark of consistent opening, carry out the technical scheme of photoetching and etching again, effectively avoid exist in prior art in the technical problem carrying out leaving in thickening process cull contaminated equipment to the press welding block in chip, and then reach when equipment of bringing into chip processes, can not contaminated equipment, the technique effect of equipment coefficient of losses can be reduced.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (8)
1. remove a method for cull, it is characterized in that, described method specifically comprises:
Alloying Treatment is carried out to the first metal layer and the second metal level, the first metal layer of at least one the first opening part corresponding and described second metal level are combined closely, wherein, described the first metal layer thickness is d1, described first opening is that described the first metal layer is formed through over etching, and each first opening has the first bottom surface;
Photoresist layer is formed at described second metal level upper surface;
By photoetching at described photoresist layer quantity of formation second opening identical with the first opening, in described second opening, the position of each second opening is vertically corresponding with each first opening in described first opening;
Along described second layer on surface of metal corresponding to each second opening vertically downward, by etching, part second metal level in described second opening is removed, for each second opening forms the second bottom surface;
By process of removing photoresist, remove the cull in each second opening in described second opening, and described photoresist layer.
2. the method for claim 1, is characterized in that, described first opening is that described the first metal layer is formed through over etching, and wherein, described first A/F is w1.
3. method as claimed in claim 2, it is characterized in that, the lower surface of described the first metal layer upper surface and described second metal level has the passivation layer that thickness is d2;
Described Alloying Treatment is carried out to the first metal layer and the second metal level, makes before the first metal layer of at least one the first opening part corresponding and described second metal level combine closely, specifically also to comprise:
Be the passivation layer of d2 by being etched in the thickness of described the first metal layer upper surface, at the 4th opening that the upper surface quantity of formation of described the first metal layer is identical with described first opening, in described 4th opening, the position of each 4th opening is vertically corresponding with each first opening at least one first opening described, wherein, described 4th opening has the 4th bottom surface, and described 4th bottom surface and described first bottom surface are positioned at same level.
4. method as claimed in claim 3, it is characterized in that, the described thickness by being etched in described the first metal layer upper surface is the passivation layer of d2, after the 4th opening that the upper surface quantity of formation of described the first metal layer is identical with described first opening, described Alloying Treatment is carried out to the first metal layer and the second metal level, make before the first metal layer of at least one the first opening part corresponding and described second metal level combine closely, specifically also to comprise:
By sputtering on described passivation layer, form the second metal level, wherein, described second metal level is formed at described passivation layer upper surface, and the 3rd opening that quantity of formation is identical with described first opening, in described 3rd opening, the position of each 3rd opening is vertically corresponding with each first opening in described first opening, and each 3rd opening has the 3rd bottom surface, described 3rd bottom surface and described first bottom surface are positioned at different level, and described 4th bottom surface and described 3rd bottom surface are positioned at different level.
5. method as claimed in claim 4, it is characterized in that, described 3rd bottom surface and described second bottom surface are positioned at same level.
6. the method for claim 1, is characterized in that, the material of described the first metal layer is specially:
Al, Cu, albronze or Al-Si-Cu alloy.
7. the method for claim 1, is characterized in that, the material of described second metal level is specially:
Al, Cu, albronze or Al-Si-Cu alloy.
8. method as claimed in claim 4, it is characterized in that, the width of described 3rd opening is w2;
Wherein, described w2 is less than or equal to described w1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110424678.9A CN103165413B (en) | 2011-12-16 | 2011-12-16 | A kind of method removing cull |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110424678.9A CN103165413B (en) | 2011-12-16 | 2011-12-16 | A kind of method removing cull |
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| CN103165413A CN103165413A (en) | 2013-06-19 |
| CN103165413B true CN103165413B (en) | 2016-03-30 |
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| CN201110424678.9A Active CN103165413B (en) | 2011-12-16 | 2011-12-16 | A kind of method removing cull |
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| CN104425288A (en) * | 2013-08-23 | 2015-03-18 | 北大方正集团有限公司 | Manufacturing method of chip encapsulation structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101312130A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Aluminum cushion layer etching method and bump formation method |
| CN101964304A (en) * | 2009-07-23 | 2011-02-02 | 联华电子股份有限公司 | Manufacturing method of semiconductor element |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3609761B2 (en) * | 2001-07-19 | 2005-01-12 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101312130A (en) * | 2007-05-23 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | Aluminum cushion layer etching method and bump formation method |
| CN101964304A (en) * | 2009-07-23 | 2011-02-02 | 联华电子股份有限公司 | Manufacturing method of semiconductor element |
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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