CN104425288A - Manufacturing method of chip encapsulation structure - Google Patents
Manufacturing method of chip encapsulation structure Download PDFInfo
- Publication number
- CN104425288A CN104425288A CN201310373524.0A CN201310373524A CN104425288A CN 104425288 A CN104425288 A CN 104425288A CN 201310373524 A CN201310373524 A CN 201310373524A CN 104425288 A CN104425288 A CN 104425288A
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- Prior art keywords
- chip
- metal
- layer
- passivation layer
- welding block
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/116—Manufacturing methods by patterning a pre-deposited material
- H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
- H01L2224/11622—Photolithography
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to the semiconductor process technical field and discloses a manufacturing method of a chip encapsulation structure. According to the manufacturing method, after a passivation layer and a metal layer are formed on chip metal wires, the chip is arranged in a high-temperature alloy furnace tube so that alloying processing can be performed on the metal layer, and as a result, a metal alloy layer can be formed; patterning processing is performed on the metal alloy layer, so that a pressure welded block can be formed; and therefore, photoresist left by the patterning processing will not exist, and the problem of pollution to the high-temperature alloy furnace tube in high-temperature carbonization can be solved. With the manufacturing method provided by the technical scheme of the invention adopted, the chip can satisfy a requirement for the thickness of the metal layer formed through copper wire bonding, and the manufacturing process of the chip can be optimized, and the maintenance frequency of the alloy furnace tube will not be increased, and the manufacturing cost of the chip can be reduced.
Description
Technical field
The present invention relates to semiconductor process techniques field, particularly relate to a kind of manufacture method of chip-packaging structure.
Background technology
Along with the development in market, chip package process is constantly to the future development of high electrical performance, high-heat performance and low cost.In chip package process, routing bonding process is modal technology, and because copper cash has low resistivity, high thermal conductivity, the advantage such as cheap, bonding (bonding) wire rod adopts copper cash to replace existing gold thread and aluminum steel to become inevitable.But copper cash is relative to gold thread and aluminum steel, and its hardness ratio is higher, and is easily oxidized, in routing processing procedure, easily the metal level 2 in chip pressure welding district 10 is broken (as shown in Figure 1), cause the failure of routing bonding process.So with copper cash when packaging and routing, very high to the thickness requirement of chip pressure welding district metal level.
Shown in composition graphs 2 and Fig. 3, be the requirement making the thickness of chip pressure welding district metal level reach copper cash packaging and routing, some chip manufacturing factory adopts the method increasing separately pressure welding area metal layer thickness at present, is specially:
Chip substrate 1 sputters the first metal layer, and this substrate comprises pressure welding area;
First time photoetching, etching technics are carried out to the first metal layer, forms chip metal cabling 3;
Chip metal cabling 3 is formed passivation layer 4 and thicker the second metal level 5 of thickness successively;
Second time photoetching, etching technics are carried out to the second metal level 5, forms the press welding block pattern (not shown) being positioned at pressure welding area;
Finally metallic alloying process is carried out to press welding block.
Above-mentioned method can meet the requirement of copper cash encapsulation to metal layer thickness, but in actual production process, because metal routing in chip is intensive and spacing is less, when forming passivation layer and second time metal level, very little gap (as shown in Figure 2) can be formed between metal routing, second time photoetching and etching technics in, because this gap is less, the more difficult thorough removal of photoresist in gap, cause having cull to stay inside gap, when the most laggard high-temperature alloy furnace tube carries out metallic alloying process, cull at high temperature (425 DEG C) carbonizes, so that alloy furnace tubes by adopting is polluted and blackening, impact is produced.If increase alloy furnace tubes by adopting maintenance frequency, can reduce again the production capacity of alloy furnace tubes by adopting, chip manufacturing cost is increased, this just requires that chip manufacturing factory is while chip meets the requirement of copper cash packaging and routing, is optimized chip manufacturing process flow process.
Summary of the invention
In view of above-mentioned technical problem, the invention provides a kind of manufacture method of chip-packaging structure, be the chip manufacturing process that the metal layer thickness meeting copper cash routing requires in order to solve in prior art, the problem that high-temperature alloy furnace tube is polluted by cull can be caused.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of chip-packaging structure, be included in and substrate form the first metal layer and the first patterning processes is carried out to described the first metal layer, form the step of chip metal cabling pattern, described substrate comprises pressure welding area, further comprising the steps of:
Step S1, on described chip metal cabling, form passivation layer;
Step S2, on described passivation layer, form certain thickness second metal level;
Step S3, Alloying Treatment is carried out to described second metal level, form metal alloy layer;
Step S4, carry out the second patterning processes to described metal alloy layer, form the pattern of the first press welding block, wherein, described first press welding block is positioned at the top of described pressure welding area.
The beneficial effect of technique scheme of the present invention is as follows:
In technique scheme, after chip metal cabling is formed passivation layer and metal level, first enter high-temperature alloy furnace tube and Alloying Treatment formation metal alloy layer is carried out to metal level, and then patterning processes formation press welding block is carried out to metal alloy layer, thus photoresist residual in patterning processes can not be there is, at high temperature carbonize the problem that high-temperature alloy furnace tube is polluted.Meet the metal layer thickness requirement of copper cash packaging and routing at chip while, optimize the manufacturing process of chip, the maintenance frequency of alloy furnace tubes by adopting can not be increased, reduce the manufacturing cost of chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Schematic diagram when Fig. 1 represents that in existing chip manufacturing process, pressure welding area metal level is broken;
Fig. 2 represents in existing chip manufacturing process the partial schematic diagram form passivation layer and the second metal level on chip metal cabling after;
Fig. 3 represents the partial schematic diagram in existing chip manufacturing process, the second metal level being carried out to chip metal routing region after patterning processes;
Fig. 4 represents the manufacture method flow chart of embodiment of the present invention chips encapsulating structure;
Fig. 5-Fig. 8 represents the manufacturing process schematic diagram of embodiment of the present invention chips encapsulating structure.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
A kind of manufacture method of chip-packaging structure is provided, for the manufacture craft of the chip-packaging structure of copper cash packaging and routing in the embodiment of the present invention.First the method is generally silicon substrate at substrate 1(substrate 1) upper sputtering the first metal layer 2, then the first metal layer 2 is comprised to first patterning processes (patterning processes in following content includes spin coating photoresist, photoetching, etching and removal photoresist process) of spin coating photoresist, photoetching, etching and removal photoresist, form the pattern of chip metal cabling 3, as shown in Figure 5, wherein, substrate 1 comprises pressure welding area 10, one end of copper cash is welded with the metal level above pressure welding area 10, realizes the packaging and routing of copper cash.As shown in Figure 4, in the present embodiment, this manufacture method is further comprising the steps of:
Step S1, on described chip metal cabling, form passivation layer;
Step S2, on described passivation layer, form certain thickness second metal level;
Step S3, Alloying Treatment is carried out to described second metal level, form metal alloy layer;
Step S4, carry out the second patterning processes to described metal alloy layer, form the pattern of the first press welding block, wherein, described first press welding block is positioned at the top of described pressure welding area.
In above-mentioned steps, after chip metal cabling is formed passivation layer and metal level, first enter high-temperature alloy furnace tube and Alloying Treatment formation metal alloy layer is carried out to metal level, and then patterning processes formation press welding block is carried out to metal alloy layer, thus photoresist residual in patterning processes can not be there is, at high temperature carbonize the problem that high-temperature alloy furnace tube is polluted.Meet the metal layer thickness requirement of copper cash packaging and routing at chip while, optimize the manufacturing process of chip, the maintenance frequency of alloy furnace tubes by adopting can not be increased, reduce the manufacturing cost of chip.
Shown in composition graphs 8, the first press welding block 6 is the second metal level 5 above pressure welding area 10.Wherein, metal level above pressure welding area 10 only can comprise the second metal level 5, also can comprise the first metal layer 2 and the second metal level 5 simultaneously, preferred the latter in the present embodiment, because the metal layer thickness above pressure welding area 10 is the thickness sum of the first metal layer 2 and the second metal level 5, while the metal layer thickness meeting copper cash packaging and routing requires, the integral thickness of chip can be effectively reduced.To achieve these goals, in the first patterning processes, also comprise the pattern of formation second press welding block 7, and the second press welding block 7 is the first metal layer 2 above pressure welding area 10.Correspondingly, also comprise before step S2:
Carry out the 3rd patterning processes to described passivation layer, form the pattern of passivation layer via hole, described first press welding block is connected by described passivation layer via hole with the second press welding block.
As shown in Figure 6, owing to only defining passivation layer 4 between chip metal cabling 3 in this step, gap between chip metal cabling 3 is larger, then remove the photoresist between clean chip metal cabling 3 than being easier in the 3rd patterning processes, thus in follow-up metallic alloying processing procedure, can not produce high-temperature alloy furnace tube and pollute.
In the present embodiment, specifically can form passivation layer 4 by sputtering technology on chip metal cabling 3 in step S1, as shown in Figure 6.Specifically the second metal level 5 can be formed by sputtering technology on passivation layer 4, as shown in Figure 7 in step S2.Wherein, the thickness of the second metal level 5 is determined by the thickness of copper cash during packaging and routing, and metal level during guarantee packaging and routing above pressure welding area 10 can not be broken.In step S3, the Alloying Treatment of the second metal level 5 can reduce the resistance that packaging and routing is introduced, be specially, chip-packaging structure is put into the high-temperature alloy furnace tube being full of nitrogen and hydrogen, and under the temperature conditions of 425 DEG C technique 30 minutes, form alusil alloy.
The manufacturing process of chips encapsulating structure of the present invention will be specifically described below with an embodiment:
The first step: sputter the first metal layer 2 on substrate 1, and according to the design layout of chip, photoetching, etching technics are carried out to the first metal layer 2, form chip metal cabling 3 and the second press welding block 7, metal layer thickness (i.e. the thickness of the second press welding block 7) now above pressure welding area 10 is of uniform thickness with chip metal cabling 3, as shown in Figure 5.
Second step: form passivation layer 4 on chip metal cabling 3, carries out photoetching, etching technics to passivation layer 4, and form passivation layer via hole 8, wherein, passivation layer via hole 8 is positioned at the top of the second press welding block 7, as shown in Figure 6.Thus expose the second press welding block 7, now the thickness of pressure welding area 10 upper metal layer can meet the routing requirement of gold thread and aluminum steel, but still can not meet the routing requirement of copper cash.
3rd step: sputter the second metal level 5 in passivation layer via hole 8, and chip-packaging structure is put into the high-temperature alloy furnace tube being full of nitrogen and hydrogen, technique 30 minutes under the temperature conditions of 425 DEG C, forms alusil alloy layer, as shown in Figure 7.
4th step: carry out photoetching, etching technics to the second metal level 5, form the first press welding block 6, wherein, the first press welding block 6 is positioned at above pressure welding area 10, and is connected with the second press welding block 7 by passivation layer via hole.Thus the metal layer thickness thickeied above pressure welding area 10, meet the routing requirement of copper cash, and the thickness of chip metal cabling 3 is constant, as shown in Figure 8.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the technology of the present invention principle; can also make some improvement and replacement, these improve and replace and also should be considered as protection scope of the present invention.
Claims (3)
1. the manufacture method of a chip-packaging structure, be included in and substrate form the first metal layer and carries out the first patterning processes to described the first metal layer, form the step of chip metal cabling pattern, described substrate comprises pressure welding area, it is characterized in that, further comprising the steps of:
Step S1, on described chip metal cabling, form passivation layer;
Step S2, on described passivation layer, form certain thickness second metal level;
Step S3, Alloying Treatment is carried out to described second metal level, form metal alloy layer;
Step S4, carry out the second patterning processes to described metal alloy layer, form the pattern of the first press welding block, wherein, described first press welding block is positioned at the top of described pressure welding area.
2. manufacture method according to claim 1, is characterized in that, carries out the first patterning processes to described the first metal layer, and form the pattern of chip metal cabling and the second press welding block, wherein, described second press welding block is positioned at the top of described pressure welding area;
Also comprise before step S2:
Carry out the 3rd patterning processes to described passivation layer, form the pattern of passivation layer via hole, described first press welding block is connected by described passivation layer via hole with the second press welding block.
3. manufacture method according to claim 1, is characterized in that, step S3 is specially:
Chip-packaging structure is put into the high-temperature alloy furnace tube being full of nitrogen and hydrogen, technique 30min under the temperature conditions of 425 DEG C, form silicon-aluminum layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310373524.0A CN104425288A (en) | 2013-08-23 | 2013-08-23 | Manufacturing method of chip encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310373524.0A CN104425288A (en) | 2013-08-23 | 2013-08-23 | Manufacturing method of chip encapsulation structure |
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| Publication Number | Publication Date |
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| CN104425288A true CN104425288A (en) | 2015-03-18 |
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| CN201310373524.0A Pending CN104425288A (en) | 2013-08-23 | 2013-08-23 | Manufacturing method of chip encapsulation structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN102832268A (en) * | 2012-09-10 | 2012-12-19 | 中国科学院半导体研究所 | Boron-aluminum co-doped back surface field silicon solar battery and preparation method thereof |
| CN103165413A (en) * | 2011-12-16 | 2013-06-19 | 北大方正集团有限公司 | Adhesive residue removing method |
-
2013
- 2013-08-23 CN CN201310373524.0A patent/CN104425288A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102237327A (en) * | 2010-05-05 | 2011-11-09 | 北大方正集团有限公司 | Chip with thickened metal layer of press welding block and manufacturing method for chip |
| CN103165413A (en) * | 2011-12-16 | 2013-06-19 | 北大方正集团有限公司 | Adhesive residue removing method |
| CN102832268A (en) * | 2012-09-10 | 2012-12-19 | 中国科学院半导体研究所 | Boron-aluminum co-doped back surface field silicon solar battery and preparation method thereof |
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Application publication date: 20150318 |