CN102522325B - Production method for submicron multilayer metallic electrode - Google Patents

Production method for submicron multilayer metallic electrode Download PDF

Info

Publication number
CN102522325B
CN102522325B CN201110364080.5A CN201110364080A CN102522325B CN 102522325 B CN102522325 B CN 102522325B CN 201110364080 A CN201110364080 A CN 201110364080A CN 102522325 B CN102522325 B CN 102522325B
Authority
CN
China
Prior art keywords
electrode
metal level
layer
etching
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110364080.5A
Other languages
Chinese (zh)
Other versions
CN102522325A (en
Inventor
杨小兵
王传敏
刘军
孙金池
姚全斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute
Mxtronics Corp
Original Assignee
China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute
Mxtronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute, Mxtronics Corp filed Critical China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute
Priority to CN201110364080.5A priority Critical patent/CN102522325B/en
Publication of CN102522325A publication Critical patent/CN102522325A/en
Application granted granted Critical
Publication of CN102522325B publication Critical patent/CN102522325B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention relates to a production method for a submicron multilayer metallic electrode. The production method comprises the following steps of: 1) adopting an evaporation or sputtering technology to form a Ti-W-Ti-Au four-layer metal electroplating sub-layer; 2) photoetching an electrode pattern, electroplating an Au metal layer and removing photoresist after electroplating is completed; 3) adopting three steps to etch the Ti-W-Ti-Au four-layer metal electroplating sub-layer, wherein a first step is to adopt an ion beam technology which uses inert gas as main etching gas to etch away an Au layer which is at the topmost layer of the electroplating sub-layer, a second step is to adopt a plasma technology which uses F-base gas or CI-base gas as main etching gas to etch away most Ti-W-Ti metal layers, and a third step is to a plasma technology which uses CF4 gas as main etching gas to clearly etch away metal residues; and 4) annealing the etched electrode in an oxygen-free atmosphere to repair electrode etching damages. By adopting the method provided by the invention, the electrode can resist high temperature during welding and the damages to a device during etching can be reduced.

Description

A kind of manufacture method of submicron multilayer metallic electrode
Technical field
The present invention relates to a kind of multilayer metallic electrode manufacture method, particularly adopt the polysilicon emitter method for making its electrode based on gold.
Background technology
Multi-layered electrode reliability based on gold is high, and high frequency characteristics is good, is usually used in the electrode of high frequency power pipe.Multi-layered electrode manufacture craft mainly comprises the sputtering of layer gold and transition zone thereof, plating and etching technics.Conventional multi-layered electrode adopts Ti-Au or W-Au structure, and as adhesive linkage, the thickness of Ti or W is no more than ion beam and plasma process is adopted to realize the separated etching of electrode respectively.Adopt this conventional multilayer electrode, because gold and silicon are easy to form alloy, in the encapsulation process of chip rear end, because chips welding temperature is high, are easy to melt golden phenomenon, finally cause device performance to lose efficacy.In addition, in etching process to the polysilicon layer under electrode or silicon layer undercutting larger, the etching injury of generation is very large on device performance impact, particularly very large to the gain effects of power tube, I-V curve distribution is uneven, and current amplification factor reduces, and finally affects the qualification rate of product.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of manufacture method of submicron multilayer metallic electrode, can make the high temperature resistant welding of electrode, and can reduce the damage of etching process to device.
The present invention includes following technical scheme:
A manufacture method for submicron multilayer metallic electrode, comprises the following steps:
(1) evaporation or sputtering technology is adopted to form Ti-W-Ti-Au tetra-layers of metal plating sublayer;
(2) make electrode pattern by lithography, then electroplate Au metal level, remove photoresist after plating;
(3) three step etching Ti-W-Ti-Au tetra-layers of metal plating sublayer are adopted, the first step adopts the ion beam technology based on inert gas to be etched away by uppermost for plating sublayer Au layer, Ti-W-Ti layer major part metal level etches away based on the plasma process of F base gas or Cl base gas by second step, and the 3rd step is with CF 4gas is main etching gas, adopts plasma process to carry out over etching, by clean for residual metallic residue etching;
(4) electrode after etching carries out annealing in oxygen-free atmosphere again, to repair electrode etch damage.
In described step (1), W layer thickness is more than or equal to
In described step (2), the thickness of the Au metal level of plating is 0.5um-2um.
Inert gas in described step (3) in the first step is Ar.
In described step (3), described F base gas is SF 6or CF 4, described Cl base gas is Cl 2or BCl 3.
In described step (3), second step SF 6and CF 4mist etches.
In described step (4), oxygen-free atmosphere is N 2, annealing temperature is 0-500 DEG C, and annealing time is 0.5-2 hour.
Described multilayer metallic electrode is the electrode of polysilicon emitter.
The present invention's beneficial effect is compared with prior art:
(1) in the present invention, adopt unique Ti-W-Ti-Au tetra-layers of metal structure, make the high temperature resistant welding of electrode;
(2) in electrode fabrication process, adopt three unique step etching technics, and in the over etching stage, adopt without SF 6f base etching gas decrease over etching to device, after etching, low temperature annealing process makes etching injury repaired, and eliminates the impact of etching injury on device performance, substantially increases the reliability of this electrode and the stability of device performance.
(3) this technique is simple, reproducible, can be widely used in the multilayer metallic electrode manufacture of submicrometer processing high-frequency power device.
Accompanying drawing explanation
Fig. 1 submicron multilayer metallic electrode manufacture method of the present invention schematic diagram;
The multilayer metallic electrode schematic diagram that Fig. 2 the present invention is final;
The device I-V properties curve of Fig. 3-a electrode etch damage;
Device I-V properties curve after Fig. 3-b electrode etch injury repair.
In figure, 1-silicon substrate, 2-silicon epitaxy layer, 3-SiO 2dielectric layer, 4-polysilicon emitter, 5-base lead hole, 6,8-Ti metal level, 7-W metal level, 9-sputters Au metal level, and 10-electroplates Au metal level
Embodiment
(1) as shown in Fig. 1-a, the silicon chip of electrode to be done comprises silicon substrate 1, silicon epitaxy layer 2, polysilicon emitter 4, base lead hole 5; And for isolating the SiO in polysilicon emitter 4 and base lead hole 5 2dielectric layer 3.The silicon chip of electrode to be done is put into sputtering equipment, silicon chip sputters a Ti metal level 6, W metal level 7, the 2nd Ti metal level 8, Au metal level 9 successively, as shown in Fig. 1-b, form Ti-W-Ti-Au tetra-layers of metal plating sublayer.Wherein Ti metal layer thickness is one Ti metal level 6 thickness is preferably 2nd Ti metal level 8 thickness is preferably one Ti metal level 6 Thickness Ratio the 2nd Ti metal level 8 thickness is thick, because the former is the adhesive linkage between metal and silicon, and the latter is the adhesive linkage between metal.W metal level 7 thickness is more than or equal to be preferably or this thickness can stop Au to spread in silicon at 400 DEG C, but is more prone in order to the electrode of postorder is interrupted etching, and W metal level 7 thickness is too not thick, meets the demands.The thickness of sputtering Au metal level 9 is or this one deck just forms one deck plating Au sublayer, unnecessary too thick, otherwise in the technique of postorder, the ion beam technology time is oversize, and waste resource.
(2) make electrode pattern by lithography, then electroplate Au metal level 10, remove photoresist after plating, as shown in fig 1-c.The thickness wherein electroplating Au metal level 10 is 0.5um-2um, and this thickness is determined by the maximum operating currenbt of device; For conventional power device, the thickness of plating Au metal level 10 is preferably 1.2-1.5um.
(3) adopt the whole metal plating sublayer of Ar gas ion beam etching, the Au metal level 9 of plating sublayer is etched totally, as shown in Fig. 1-d.
(4) adopt the Ti-W-Ti layer that plasma etching industrial etching metal plating sublayer is remaining in two steps, first pass into SF 6and CF 4mist, this one-phase, because W metal level 7 thickness is thicker, and SF 6etching W is easy to, and passes into CF 4thin Ti metal level 8 can be etched, can SF be stoped simultaneously 6to the sidetracking of W metal level 7, the integrality of holding electrode.Etch period is 1mins-2mins, can etch to the greatest extent, as shown in Fig. 1-e by Ti-W-Ti layer major part metal level.Then in the over etching stage, N is replaced with by etching gas 2and CF 4mist, CF 4ti metal level 6 can be etched, and too much etching can not be produced to polycrystal emitter.Keep other conditions constant, then etch 3mins-4mins, the residue of Ti metal level 6 thoroughly can be etched totally, as shown in Fig. 1-f.
(5) carry out process annealing by the silicon chip feeding annealing furnace after etching, annealing atmosphere is oxygen-free atmosphere, as N2, thus electrode etch damage is repaired.Annealing temperature is 0-500 DEG C, and be preferably 300 DEG C, 400 DEG C, this temperature both can reach reparation etching injury, and impurity in device can not be made again to occur to distribute again.Annealing time is 0.5-2 hour, and be preferably 1 hour, the time is too short, and etching injury reparation is not thorough, and the time is oversize, and electrode can move, and finally can affect electrical property.
By above technical process, finally form submicron multilayer metallic electrode, as shown in Figure 2.
The above; be only the embodiment of the best of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.
The present invention adopts unique Ti-W-Ti-Au tetra-layers of metal structure, and wherein Ti is adhesive linkage, strengthens the ohmic contact between metal level and silicon layer; W is barrier layer, stops Au to spread to silicon substrate, its thicker thickness prevent Au to spread to silicon substrate, ensure that Au electrode can bear the back-end chip welding temperature of 400 DEG C and can not melt golden phenomenon.
The present invention adopts three step etching electroplating sublayer Ti-W-Ti-Au metal levels, in the over etching stage, due to SF 6etches polycrystalline silicon etch rate much larger than metal etch speed (about ), therefore adopt without SF 6f base gas as CF 4plasma process etching residual metallic residue, both ensure that the metal between Different electrodes disconnected, can not produce too much undercutting again to polysilicon emitter.
After electrode etch completes, owing to there is etching injury, transistor base resistance is larger, defect is many, and electric current compound is serious, and the multiplication factor therefore under small area analysis is little, and under different base current, the amplified current that emitter obtains is different, and whole I-V curve is tilted and skewness, as shown in Fig. 3-a.Electrode is annealed at low temperatures, has repaired electrode etch damage, and the defect in electrode is repaired, compound is little, and current amplification factor recovers to become large, and the I-V curve of device becomes steep, distribute comparatively uniformity, shown in Fig. 3-b, thus substantially increases the performance reliability of product.
The invention solves the high temperature resistant Welding Problems of metal electrode and dry etching electrode pair polysilicon damage problem, substantially increase the reliability of gold electrode and the stability of device performance, the electrode manufacture of submicrometer processing high-frequency power device can be widely used in.The content be not described in detail in specification of the present invention belongs to the known technology of professional and technical personnel in the field.

Claims (4)

1. a manufacture method for submicron multilayer metallic electrode, is characterized in that, described multilayer metallic electrode is the electrode of polysilicon emitter; The preparation method of the electrode of polysilicon emitter comprises the following steps:
(1) silicon chip of electrode to be done comprises silicon substrate (1), silicon epitaxy layer (2), polysilicon emitter (4), base lead hole (5) and the SiO for isolating polysilicon emitter (4) and base lead hole (5) 2dielectric layer (3); Adopt sputtering technology on the silicon chip of electrode to be done, sputter a Ti metal level (6), W metal level (7), the 2nd Ti metal level (8), an Au metal level (9) successively, thus form Ti-W-Ti-Au tetra-layers of metal plating sublayer; Wherein, Ti metal level (6) Thickness Ratio the 2nd Ti metal level (8) thickness is thick;
(2) make electrode pattern by lithography, then electroplate the 2nd Au metal level (10), remove photoresist after plating;
(3) three step etching Ti-W-Ti-Au tetra-layers of metal plating sublayer are adopted, the first step adopts the ion beam technology based on inert gas to be etched away by four layers of uppermost Au metal level (9) in metal plating sublayer, Ti-W-Ti layer major part metal level etches away based on the plasma process of F base gas by second step, and the 3rd step is with CF 4gas is main etching gas, adopts plasma process to carry out over etching, by clean for residual metallic residue etching; Second step SF 6and CF 4mist etches;
(4) electrode after etching carries out annealing in oxygen-free atmosphere again, to repair electrode etch damage; In described step (four), oxygen-free atmosphere is N 2, annealing temperature is 0-500 DEG C, and annealing time is 0.5-2 hour.
2. the manufacture method of submicron multilayer metallic electrode according to claim 1, is characterized in that: in described step (), W metal level (7) thickness is more than or equal to
3. the manufacture method of submicron multilayer metallic electrode according to claim 1, is characterized in that: in described step (two), the thickness of the 2nd Au metal level (10) of plating is 0.5 micron-2 microns.
4. the manufacture method of submicron multilayer metallic electrode according to claim 1, is characterized in that: the inert gas in described step (three) in the first step is Ar.
CN201110364080.5A 2011-11-15 2011-11-15 Production method for submicron multilayer metallic electrode Expired - Fee Related CN102522325B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110364080.5A CN102522325B (en) 2011-11-15 2011-11-15 Production method for submicron multilayer metallic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110364080.5A CN102522325B (en) 2011-11-15 2011-11-15 Production method for submicron multilayer metallic electrode

Publications (2)

Publication Number Publication Date
CN102522325A CN102522325A (en) 2012-06-27
CN102522325B true CN102522325B (en) 2015-02-11

Family

ID=46293204

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110364080.5A Expired - Fee Related CN102522325B (en) 2011-11-15 2011-11-15 Production method for submicron multilayer metallic electrode

Country Status (1)

Country Link
CN (1) CN102522325B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103730412A (en) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 Metal interconnecting wire formation method
CN103871858A (en) * 2014-03-03 2014-06-18 中国电子科技集团公司第五十五研究所 Manufacturing method for submicron electrode of indium phosphide-based heterojunction transistor
CN108493768A (en) * 2018-04-10 2018-09-04 中国科学院半导体研究所 The preparation method of ridge waveguide structure laser P-type electrode

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1650050A (en) * 2002-03-26 2005-08-03 莱蒂斯能量有限责任公司 Electrode constructs, and related cells and methods

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6467964A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Multilayer electrode structure
JP5318624B2 (en) * 2009-03-27 2013-10-16 日本電信電話株式会社 Method for manufacturing heterojunction bipolar transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1650050A (en) * 2002-03-26 2005-08-03 莱蒂斯能量有限责任公司 Electrode constructs, and related cells and methods

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JP昭64-67964A 1989.03.14 *
JP特开2010-232397A 2010.10.14 *
多层难熔金属的刻蚀工艺技术研究;段雪等;《真空科学与技术学报》;20051231;第25卷(第6期);463-470 *

Also Published As

Publication number Publication date
CN102522325A (en) 2012-06-27

Similar Documents

Publication Publication Date Title
CN101393842B (en) Slot forming method
JP5062558B2 (en) Method for manufacturing active matrix substrate
US8866299B2 (en) Backside processing of semiconductor devices
CN103606516A (en) Manufacturing method of low-temperature non-gold ohmic contact of GaN-based high-electronic-mobility transistor
CN102522325B (en) Production method for submicron multilayer metallic electrode
CN115274999B (en) Josephson junction and preparation method and application thereof
CN107369719B (en) Oxide thin film transistor pure copper composite structure source-drain electrode and preparation method thereof
US20180211921A1 (en) Interconnect structure and fabricating method thereof
CN104867828A (en) Manufacturing method of GaAs based semiconductor device
CN113725287B (en) Low-temperature gold-free ohmic contact GaN-based HEMT device and preparation method thereof
JP5672329B2 (en) Switching element
WO2018014792A1 (en) Passivation layer manufacturing method, high-voltage semiconductor power device and front electrode
JP2010004058A (en) Dry etching method for silicon film
US20050164512A1 (en) Method of manufacturing semiconductor device
JP3616724B2 (en) Manufacturing method of semiconductor device
CN112366254B (en) LED chip preparation method and LED chip thereof
JP5311792B2 (en) Manufacturing method of semiconductor device
KR102092338B1 (en) Manufacturing method of an array substrate for liquid crystal display
Wen et al. 32‐1: Invited Paper: A Mask‐Reduction Process With Innovative Undercut for Large Size AMOLED Display
CN106711237A (en) Manufacturing method of high-voltage power type Schottky diode
CN109037191B (en) Trimming resistor and manufacturing method thereof
JP2003258259A (en) Electrode structure, thin-film transistor and manufacturing method therefor
US9865748B2 (en) Semiconductor structure and method for manufacturing the same
KR100296708B1 (en) Method for making integrated circuit metal line structure
CN114879455A (en) Method for removing photoresist

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150211

Termination date: 20211115

CF01 Termination of patent right due to non-payment of annual fee