CN102522325A - Production method for submicron multilayer metallic electrode - Google Patents

Production method for submicron multilayer metallic electrode Download PDF

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CN102522325A
CN102522325A CN2011103640805A CN201110364080A CN102522325A CN 102522325 A CN102522325 A CN 102522325A CN 2011103640805 A CN2011103640805 A CN 2011103640805A CN 201110364080 A CN201110364080 A CN 201110364080A CN 102522325 A CN102522325 A CN 102522325A
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etching
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sub
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layer
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CN102522325B (en
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杨小兵
王传敏
刘军
孙金池
姚全斌
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China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute
Mxtronics Corp
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China Aviation Airspace Spaceflight Technology Group Co No9 Academy No772 Research Institute
Mxtronics Corp
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Abstract

The invention relates to a production method for a submicron multilayer metallic electrode. The production method comprises the following steps of: 1) adopting an evaporation or sputtering technology to form a Ti-W-Ti-Au four-layer metal electroplating sub-layer; 2) photoetching an electrode pattern, electroplating an Au metal layer and removing photoresist after electroplating is completed; 3) adopting three steps to etch the Ti-W-Ti-Au four-layer metal electroplating sub-layer, wherein a first step is to adopt an ion beam technology which uses inert gas as main etching gas to etch away an Au layer which is at the topmost layer of the electroplating sub-layer, a second step is to adopt a plasma technology which uses F-base gas or CI-base gas as main etching gas to etch away most Ti-W-Ti metal layers, and a third step is to a plasma technology which uses CF4 gas as main etching gas to clearly etch away metal residues; and 4) annealing the etched electrode in an oxygen-free atmosphere to repair electrode etching damages. By adopting the method provided by the invention, the electrode can resist high temperature during welding and the damages to a device during etching can be reduced.

Description

A kind of manufacture method of sub-micron multiple layer metal electrode
Technical field
The present invention relates to a kind of multiple layer metal method for making its electrode, particularly adopting with the gold is the polysilicon emitter method for making its electrode of main body.
Background technology
With the gold is the multi-layered electrode reliability height of main body, and high frequency characteristics is good, is usually used in the electrode of high frequency power pipe.The multi-layered electrode manufacture craft mainly comprises sputter, plating and the etching technics of gold layer and transition zone thereof.Conventional multi-layered electrode adopts Ti-Au or W-Au structure; As adhesive linkage, the thickness of Ti or W is no more than
Figure BSA00000614053800011
adopts ion beam and plasma process to realize the separated etching of electrode respectively.Adopt this conventional multi-layered electrode,, in the encapsulation process of chip rear end,, be easy to melt golden phenomenon, finally cause device performance to lose efficacy because of the chips welding temperature is high because gold is easy to form alloy with silicon.In addition, bigger to polysilicon layer under the electrode or silicon layer undercutting in etching process, the etching injury of generation is very big to the device performance influence; Particularly the gain effects to power tube is very big; The I-V curve distribution is inhomogeneous, and current amplification factor reduces, and finally influences the qualification rate of product.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacture method of sub-micron multiple layer metal electrode, can make the high temperature resistant welding of electrode, and can reduce the damage of etching process to device.
The present invention includes following technical scheme:
A kind of manufacture method of sub-micron multiple layer metal electrode comprises the following steps:
(1) adopt evaporation or sputtering technology to form four layers of metal plating sublayer of Ti-W-Ti-Au;
(2) make electrode pattern by lithography, electroplate the Au metal level then, remove photoresist after plating finishes;
(3) adopt four layers of metal plating sublayer of three step etching Ti-W-Ti-Au; It is that main ion beam technology will be electroplated the uppermost Au layer in sublayer and etch away that the first step adopts with the inert gas; The plasma process that second step was the master with F base gas or the basic gas of Cl etches away the most of metal level of Ti-W-Ti layer, and the 3rd step is with CF 4Gas is main etching gas, adopts plasma process to carry out over etching, and metal remained residue etching is clean;
(4) electrode after the etching carries out annealing in the oxygen-free atmosphere again, to repair the electrode etching injury.
The W layer thickness is more than or equal to in the said step (1)
The Au metal layer thickness of electroplating in the said step (2) is 0.5um-2um.
Inert gas in the said step (3) in the first step is Ar.
In the said step (3), said F base gas is SF 6Or CF 4, said Cl base gas is Cl 2Or BCl 3
In the said step (3), second step was used SF 6And CF 4Mist carries out etching.
Oxygen-free atmosphere is N in the said step (4) 2, annealing temperature is 0-500 ℃, annealing time is 0.5-2 hour.
Said multiple layer metal electrode is the electrode of polysilicon emitter.
The present invention's beneficial effect compared with prior art is:
(1) in the present invention, adopt unique four layers of metal structure of Ti-W-Ti-Au, make the high temperature resistant welding of electrode;
(2) in the electrode manufacturing process, adopt three unique step etching technics, and, adopt no SF in the over etching stage 6F base etching gas reduced over etching to device, low temperature annealing process makes that etching injury is able to repair after the etching, has eliminated the influence of etching injury to device performance, has improved the reliability of kind electrode and the stability of device performance greatly.
(3) this technology is simple, and good reproducibility can be widely used in the multiple layer metal electrode manufacturing of submicrometer processing high frequency power device.
Description of drawings
Fig. 1 sub-micron multiple layer metal of the present invention method for making its electrode sketch map;
The multiple layer metal electrode sketch map that Fig. 2 the present invention is final;
The device I-V properties curve of Fig. 3-a electrode etching injury;
Device I-V properties curve after Fig. 3-b electrode etching injury is repaired.
Among the figure, 1-silicon substrate, 2-silicon epitaxy layer, 3-SiO 2Dielectric layer, the 4-polysilicon emitter, 5-base lead hole, 6, the 8-Ti metal level, the 7-W metal level, 9-sputter Au metal level, 10-electroplates the Au metal level
Embodiment
(1) shown in Fig. 1-a, waits that the silicon chip of doing electrode comprises silicon substrate 1, silicon epitaxy layer 2, polysilicon emitter 4, base lead hole 5; And the SiO that is used to isolate polysilicon emitter 4 and base lead hole 5 2Dielectric layer 3.With waiting that the silicon chip of doing electrode puts into sputtering equipment, sputter the one Ti metal level 6, W metal level 7, the 2nd Ti metal level 8, Au metal level 9 successively on silicon chip form four layers of metal plating sublayer of Ti-W-Ti-Au shown in Fig. 1-b.Wherein to be preferably
Figure BSA00000614053800033
Ti metal level 6 thickness thicker than the 2nd Ti metal level 8 thickness for
Figure BSA00000614053800031
Ti metal level 6 thickness are preferably
Figure BSA00000614053800032
the 2nd Ti metal level 8 thickness for the Ti metal layer thickness; Because the former is the adhesive linkage between metal and the silicon, and the latter is the adhesive linkage between the metal.W metal level 7 thickness are preferably
Figure BSA00000614053800035
or
Figure BSA00000614053800036
this thickness and can stop Au under 400 ℃, in silicon, to spread more than or equal to
Figure BSA00000614053800034
; But, the electrode of postorder is more prone to for being interrupted etching; W metal level 7 thickness are too not thick, and meeting the demands gets final product.The thickness of sputter Au metal level 9 is electroplated the Au sublayer for
Figure BSA00000614053800037
or this one deck just forms one deck; Unnecessary too thick; Otherwise in the technology of postorder; The ion beam technology time is oversize, and the waste resource.
(2) make electrode pattern by lithography, electroplate Au metal level 10 then, remove photoresist after plating finishes, shown in Fig. 1-c.The thickness of wherein electroplating Au metal level 10 is 0.5um-2um, and this thickness is by the maximum operating currenbt decision of device; For power device commonly used, the thickness of electroplating Au metal level 10 is preferably 1.2-1.5um.
(3) adopt the whole metal plating of Ar gas ion beam etching sublayer, Au metal level 9 etchings of electroplating the sublayer are clean, shown in Fig. 1-d.
(4) adopt the remaining Ti-W-Ti layer in plasma etching industrial etching metal plating sublayer in two steps, at first feed SF 6And CF 4Mist, this stage, because W metal level 7 thickness are thicker, and SF 6Etching W is easy to, and feeds CF 4Can etching approach Ti metal level 8, can stop SF simultaneously 6To the sidetracking of W metal level 7, keep the integrality of electrode.Etch period is 1mins-2mins, can the most of metal level etching of Ti-W-Ti layer is most, and shown in Fig. 1-e.Then in the over etching stage, with being replaced with N in the etching gas 2And CF 4Mist, CF 4Can etching Ti metal level 6, and can not produce too much etching to polycrystal emitter.Keep other conditions constant, etching 3mins-4mins again can be clean with the thorough etching of the residue of Ti metal level 6, shown in Fig. 1-f.
(5) silicon chip after the etching is sent into carried out process annealing in the annealing furnace, annealing atmosphere is an oxygen-free atmosphere, like N2, thereby makes the electrode etching injury be able to repair.Annealing temperature is 0-500 ℃, is preferably 300 ℃, and 400 ℃, this temperature both can reach the reparation etching injury, can not make impurity generation distribution again in the device again.Annealing time is 0.5-2 hour, is preferably 1 hour, and the time is too short, and the etching injury reparation is not thorough, and the time is oversize, and electrode can move, and finally can influence electrical property.
Through above technical process, finally form sub-micron multiple layer metal electrode, as shown in Figure 2.
The above; Be merely the best embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; The variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
The present invention adopts unique four layers of metal structure of Ti-W-Ti-Au, and wherein Ti is an adhesive linkage, strengthens the ohmic contact between metal level and the silicon layer; W is the barrier layer; Stop Au to spread to silicon substrate; Its thicker thickness
Figure BSA00000614053800041
has prevented that Au from spreading to silicon substrate, has guaranteed that the Au electrode can bear 400 ℃ back-end chip welding temperature and can not melt golden phenomenon.
The present invention adopts three step etching electroplating sublayer Ti-W-Ti-Au metal levels, at over etching in the stage, because SF 6The etch polysilicon etch rate
Figure BSA00000614053800042
Much larger than metal etch speed (approximately
Figure BSA00000614053800043
), therefore adopt no SF 6F base gas such as CF 4Plasma process etching residual metallic residue had both guaranteed that different interelectrode metals break off, and can not produce too much undercutting to polysilicon emitter again.
After the electrode etching was accomplished, owing to there is etching injury, transistor base resistance was bigger; Defective is many, and electric current is compound serious, and therefore the multiplication factor under the little electric current is little; And under different base currents; The amplified current that emitter obtains is different, makes whole I-V curve tilt and skewness, shown in Fig. 3-a.Electrode is annealed at low temperatures, has repaired the electrode etching injury, and the defective in the electrode is able to repair; Compound little, it is big that current amplification factor recovers to become, and the I-V curve of device becomes steep; The comparatively uniformity that distributes shown in Fig. 3-b, thereby has improved the performance of products reliability greatly.
The invention solves high temperature resistant Welding Problems of metal electrode and dry etching electrode pair polysilicon damage problem, improved the reliability of gold electrode and the stability of device performance greatly, can be widely used in the electrode manufacturing of submicrometer processing high frequency power device.The content of not doing to describe in detail in the specification of the present invention belongs to this area professional and technical personnel's known technology.

Claims (8)

1. the manufacture method of a sub-micron multiple layer metal electrode is characterized in that, comprises the following steps:
(1) adopt evaporation or sputtering technology to form four layers of metal plating sublayer of Ti-W-Ti-Au;
(2) make electrode pattern by lithography, electroplate the Au metal level then, remove photoresist after plating finishes;
(3) adopt four layers of metal plating sublayer of three step etching Ti-W-Ti-Au; It is that main ion beam technology will be electroplated the uppermost Au layer in sublayer and etch away that the first step adopts with the inert gas; The plasma process that second step was the master with F base gas or the basic gas of Cl etches away the most of metal level of Ti-W-Ti layer, and the 3rd step is with CF 4Gas is main etching gas, adopts plasma process to carry out over etching, and metal remained residue etching is clean;
(4) electrode after the etching carries out annealing in the oxygen-free atmosphere again, to repair the electrode etching injury.
2. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: the W layer thickness is more than or equal to
Figure FSA00000614053700011
in the said step (1)
3. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: the Au metal layer thickness of electroplating in the said step (2) is 0.5um-2um.
4. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: the inert gas in the said step (3) in the first step is Ar.
5. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: in the said step (3), said F base gas is SF 6Or CF 4, said Cl base gas is Cl 2Or BCl 3
6. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: in the said step (3), second step was used SF 6And CF 4Mist carries out etching.
7. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: oxygen-free atmosphere is N in the said step (4) 2, annealing temperature is 0-500 ℃, annealing time is 0.5-2 hour.
8. the manufacture method of sub-micron multiple layer metal electrode according to claim 1 is characterized in that: said multiple layer metal electrode is the electrode of polysilicon emitter.
CN201110364080.5A 2011-11-15 2011-11-15 Production method for submicron multilayer metallic electrode Expired - Fee Related CN102522325B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103730412A (en) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 Metal interconnecting wire formation method
CN103871858A (en) * 2014-03-03 2014-06-18 中国电子科技集团公司第五十五研究所 Manufacturing method for submicron electrode of indium phosphide-based heterojunction transistor
CN108493768A (en) * 2018-04-10 2018-09-04 中国科学院半导体研究所 The preparation method of ridge waveguide structure laser P-type electrode

Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS6467964A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Multilayer electrode structure
CN1650050A (en) * 2002-03-26 2005-08-03 莱蒂斯能量有限责任公司 Electrode constructs, and related cells and methods
JP2010232397A (en) * 2009-03-27 2010-10-14 Nippon Telegr & Teleph Corp <Ntt> Method of manufacturing heterojunction bipolar transistor

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
JPS6467964A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Multilayer electrode structure
CN1650050A (en) * 2002-03-26 2005-08-03 莱蒂斯能量有限责任公司 Electrode constructs, and related cells and methods
JP2010232397A (en) * 2009-03-27 2010-10-14 Nippon Telegr & Teleph Corp <Ntt> Method of manufacturing heterojunction bipolar transistor

Non-Patent Citations (1)

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Title
段雪等: "多层难熔金属的刻蚀工艺技术研究", 《真空科学与技术学报》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103730412A (en) * 2014-01-07 2014-04-16 上海华虹宏力半导体制造有限公司 Metal interconnecting wire formation method
CN103871858A (en) * 2014-03-03 2014-06-18 中国电子科技集团公司第五十五研究所 Manufacturing method for submicron electrode of indium phosphide-based heterojunction transistor
CN108493768A (en) * 2018-04-10 2018-09-04 中国科学院半导体研究所 The preparation method of ridge waveguide structure laser P-type electrode

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