CN104867828A - Manufacturing method of GaAs based semiconductor device - Google Patents
Manufacturing method of GaAs based semiconductor device Download PDFInfo
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- CN104867828A CN104867828A CN201510207719.7A CN201510207719A CN104867828A CN 104867828 A CN104867828 A CN 104867828A CN 201510207719 A CN201510207719 A CN 201510207719A CN 104867828 A CN104867828 A CN 104867828A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 230000007704 transition Effects 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 30
- 230000008020 evaporation Effects 0.000 claims description 11
- 238000001704 evaporation Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052804 chromium Inorganic materials 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000013011 mating Effects 0.000 claims description 4
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract 5
- 238000001259 photo etching Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007480 spreading Effects 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method of a GaAs based semiconductor device. The manufacturing method comprises the following steps: providing a substrate, wherein the substrate comprises a GaAs based semiconductor wafer, at least one base region, at least one emitter region and at least one collector region are formed on the wafer, every two adjacent regions have a height difference, and convex sharp corners are formed at positions where the height drops; forming an insulating layer on the substrate, wherein the shape of the insulating layer is matched with or basically matched with that of the substrate; etching the insulating layer through a photoetching technology so as to allow the regions to be exposed; etching the remaining part of the insulating layer through the photoetching technology such that the insulating layer has smooth transition in the regions with the height differences relative to the surface of the substrate; and forming a metal layer above the structure. The problem that cracks are generated on the metal layer is avoided through smoothened treatment on the surface of the insulating layer.
Description
Technical field
The present invention relates to semiconductor technology, particularly relate to a kind of manufacture method of GaAs based semiconductor device.
Background technology
In the manufacturing process of semiconductor device, often need to form various functional areas by techniques such as doping, ion implantation, etchings on the semiconductor wafer, and the element manufacturing to heterojunction bipolar transistor (HBT), often have comparatively significantly difference in height between functional areas, this just causes the physical features of semiconductor wafer surface comparatively precipitous and has the wedge angle of height fall formation.Such as, when making wireless radio frequency power amplifier, GaAs based wafer is formed with multiple double pole triode, and each double pole triode includes base stage, emitter and collector electrode, between adjacent electrode and electrode interior all define height fall and the wedge angle of micron number magnitude.On wafer during follow-up formation metal level, due to the out-of-flatness of wafer surface, the situation that metal level very easily occurs slight crack at sharp corner and peels off, and slight crack has the effect of spreading and spreading, make subsequent technique be difficult to carry out on the one hand, percent defective is high; Greatly have impact on the electric conductivity of metal level on the other hand, make the semiconductor device poor stability of making, useful life is short.The existence of the problems referred to above, affects and limits yields and the production efficiency of semiconductor device greatly.
Summary of the invention
The object of the invention is to the deficiency overcoming prior art, a kind of manufacture method of GaAs based semiconductor device is provided.
The technical solution adopted for the present invention to solve the technical problems is: a kind of manufacture method of GaAs based semiconductor device comprises the following steps:
1) provide a ground, described ground comprises semiconductor wafer, and wafer is formed with at least one base region, emitter region and collector area, wherein has difference in height between adjacent electrode district and forms evagination wedge angle in height fall place;
2) on ground, form the insulating barrier of mating shapes or a basic coupling with it, the corresponding described ground height fall region of wherein said insulating barrier also coordinates and is formed with evagination wedge angle;
3) described insulating barrier is etched by light etching process, to expose described each electrode district;
4) by light etching process etching residue insulating barrier, with the evagination wedge angle of level and smooth described insulating barrier;
5) above said structure, a metal level is formed.
Preferred as one, step 3) and step 4) in, light etching process adopts identical light shield, wherein step 3) the positive photoresistance of middle employing, step 4) the negative photoresistance of middle employing, step (4) reduces 0.1-0.5um relative to step (3) its etching critical dimension (CD).
Preferred as one, the thickness of described insulating barrier is 1.2-3um, step 4) in, the etched thickness of described light etching process is 0.1-0.3um.
Preferred as one, step 4) in, after described evagination wedge angle is level and smooth, the height fall region of the corresponding described ground of described insulating barrier is arc-shaped transition.
Preferred as one, step 4) in, after described evagination wedge angle is level and smooth, the height fall region of the corresponding described ground of described insulating barrier forms chamfering structure, and evagination minimum angles is greater than 110 °.
Preferred as one, described base region, emitter region and collector area form an ambipolar audion, wherein said base region is between described emitter and described collector electrode, and by described collector area, to described emitter region, it increases progressively described wafer surface highly successively.
Preferred as one, described ground also comprises the conductive layer be formed at above each electrode district of described wafer; Step 3) in, described insulating barrier exposes described conductive layer after etching.
Preferred as one, described conductive layer is metal, including the combination layer of a kind of or above-mentioned metal in Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au, is formed by the mode of magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
Preferred as one, described metal level includes the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal, is to be formed by the mode of magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
Preferred as one, described insulating barrier is pi, is formed by the mode of coating.
The invention has the beneficial effects as follows:
1, insulating barrier is formed at surface of bottom material, the shape of insulating barrier is with surface of bottom material mating shapes or substantially mate to have uniform thickness, ensure the homogeneity of its performance, again by the evagination wedge angle in the corresponding ground height fall region of the mode smoothing insulator layer of photoetch, form arc or chamfering structure, make its gentle transition, form a comparatively mild surface, form metal level thereon again, avoid the problem that metal level ruptures at the sharp corner that physical features is precipitous.
2, insulating barrier is undertaken being etched with by positive photoresistance imaging and exposes each electrode district, uses same light shield to coordinate gold-tinted energy adjusting etching sharp corner by negative photoresistance, does not increase the cost of light shield.
Accompanying drawing explanation
Fig. 1-Fig. 6 is followed successively by the structural representation of each technological process of manufacture method of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.Each accompanying drawing of the present invention is only signal to be easier to understand the present invention, and its concrete ratio can adjust according to design requirement.The upper and lower relation of opposed member in figure described in literary composition, will be understood that the relative position referring to component those skilled in the art, therefore all can overturn and present identical component, and this all should belong to the scope disclosed by this specification together.
A kind of manufacture method of GaAs based semiconductor device, with reference to figure 1, first a GaAs based semiconductor wafer 1 is to provide, wafer 1 is formed with multiple double pole triode structure 11, each double pole triode structure 11 includes emitter region 111, base region 112 and collector area 113, wherein base region 112 is between emitter region 111 and collector area 113, it increases progressively highly successively, adjacent electrode has height fall between district, wherein collector area 113 is in a low ebb place, and drop maximum between base region 112 is about about 1-2um.Owing to highly sharply changing, define comparatively precipitous physical features and there is evagination wedge angle.
With reference to figure 2, on the emitter region 111 of wafer 1, base region 112 and collector area 113, form conductive layer 2.Conductive layer 2 can be specifically metal, includes the combination layer of a kind of or above-mentioned metal in Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au, is formed by the mode of magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).Semiconductor wafer 1 and conductive layer 2 define the ground of semiconductor device.
With reference to figure 3, formation one mating shapes or the basic insulating barrier 3 mated with it on the ground of structure shown in Fig. 2.Insulating barrier is pi, and formed by the mode of coating, thickness is 1.2-3um.The thickness of insulating barrier 3 is substantially comparatively even to keep homogeneous performance, therefore also has the evagination wedge angle at physical features precipitous as ground and height fall place.
With reference to figure 4, by light etching process etching isolation layer 3, to expose the conductive layer 2 at emitter region 111, base region 112 and place, collector area 113.Concrete, apply positive photoresistance on the insulating layer 3, the light shield mated with conductive layer 2 with optical transmission window carries out exposing, developing the etching window being formed and correspond to above conductive layer 2, and removes the partial insulative layer 3 being positioned at this window, to expose conductive layer 2.
With reference to figure 5, by light etching process etching residue insulating barrier 3, make the segment smoothing transition of the corresponding surface of bottom material height fall of insulating barrier 3.Concrete, the negative photoresistance of coating above structure shown in Fig. 4, carry out exposing, developing with the light shield of above-mentioned steps, coordinate the adjustment of gold-tinted energy during exposure, etching critical dimension (CD) reduces 0.1-0.5um will just etch the wedge angle A place of generation in non-exposed expanded range to previous step.Then, by dry ecthing, insulating barrier 3 is etched away the thickness of 0.1-0.3um, to remove wedge angle, make the region of height fall, especially seamlessly transit between base region 112 and collector area 113, form comparatively mild surface.In the present embodiment, after evagination wedge angle is level and smooth, the height fall region of the corresponding ground of insulating barrier 3 is arc-shaped transition.In addition, by the adjustment of energy, so that the height fall region of the corresponding ground of insulating barrier 3 can be made to form chamfering structure, wherein the evagination minimum angles of chamfering is greater than 110 °, to make stress preferably to both sides dispersion, the fracture avoiding stress to concentrate causing.
With reference to figure 6, a metal level 4 is formed in the top of said structure, metal level includes the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal, formed by the mode of evaporation, and in emitter region 111, base region 112 and collector area 113 and conductive layer 2 directly connect conducting.Metal level 4 is formed on milder surface, not easily produces crack, is beneficial to the carrying out of subsequent manufacturing processes.
In semiconductor device of the present invention, conductive layer 2 after etching and metal level 4 can be list structures that is orthogonal and that be electrically connected in each electrode district, and be connected respectively at structures such as periphery and control circuits, may be used for making wireless radio frequency power amplifier, obtained device performance is stablized.
Above-described embodiment is only used for further illustrating the manufacture method of a kind of GaAs based semiconductor device of the present invention; but the present invention is not limited to embodiment; every above embodiment is done according to technical spirit of the present invention any simple modification, equivalent variations and modification, all fall in the protection range of technical solution of the present invention.
Claims (10)
1. a manufacture method for GaAs based semiconductor device, is characterized in that comprising the following steps:
1) provide a ground, described ground comprises a GaAs based semiconductor wafer, and wafer is formed with at least one base region, emitter region and collector area, wherein has difference in height between adjacent electrode district and forms evagination wedge angle in height fall place;
2) on ground, form the insulating barrier of mating shapes or a basic coupling with it, the corresponding described ground height fall region of wherein said insulating barrier also coordinates and is formed with evagination wedge angle;
3) described insulating barrier is etched by light etching process, to expose described each electrode district;
4) by light etching process etching residue insulating barrier, with the evagination wedge angle of level and smooth described insulating barrier;
5) above said structure, a metal level is formed.
2. manufacture method according to claim 1, it is characterized in that: step 3) and step 4) in, light etching process adopts identical light shield, wherein step 3) the positive photoresistance of middle employing, step 4) in adopt negative photoresistance, step 4) relative to step 3) its etching critical dimension reduces 0.1-0.5um.
3. manufacture method according to claim 1 and 2, is characterized in that: the thickness of described insulating barrier is 1.2-3um, step 4) in, the etched thickness of described light etching process is 0.1-0.3um.
4. manufacture method according to claim 3, is characterized in that: step 4) in, after described evagination wedge angle is level and smooth, the curved transition in height fall region of the corresponding described ground of described insulating barrier.
5. manufacture method according to claim 3, is characterized in that: step 4) in, after described evagination wedge angle is level and smooth, the height fall region of the corresponding described ground of described insulating barrier forms chamfering structure, and evagination minimum angles is greater than 110 °.
6. manufacture method according to claim 1, it is characterized in that: described base region, emitter region and collector area form an ambipolar audion, wherein said base region is between described emitter and described collector electrode, and by described collector area, to described emitter region, it increases progressively described wafer surface highly successively.
7. manufacture method according to claim 1, is characterized in that: described ground also comprises the conductive layer be formed at above each electrode district of described wafer; Step 3) in, described insulating barrier exposes described conductive layer after etching.
8. manufacture method according to claim 5, it is characterized in that: described conductive layer is metal, including the combination layer of a kind of or above-mentioned metal in Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au, is formed by the mode of magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
9. the manufacture method according to claim 1 or 8, it is characterized in that: described metal level includes the combination layer of Ti, Ni, Cu, Al, Pt, W, Mo, Cr, Au or above-mentioned metal, is formed by the mode of magnetic control sputtering plating, ion evaporation, arc ions evaporation or chemical vapour deposition (CVD).
10. manufacture method according to claim 1, is characterized in that: described insulating barrier is pi, is formed by the mode of coating.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510207719.7A CN104867828B (en) | 2015-04-28 | 2015-04-28 | A kind of preparation method of GaAs based semiconductor device |
| PCT/CN2016/073992 WO2016173311A1 (en) | 2015-04-28 | 2016-02-18 | Preparation method for gaas-based semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510207719.7A CN104867828B (en) | 2015-04-28 | 2015-04-28 | A kind of preparation method of GaAs based semiconductor device |
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| CN104867828A true CN104867828A (en) | 2015-08-26 |
| CN104867828B CN104867828B (en) | 2018-03-09 |
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| WO (1) | WO2016173311A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106019813A (en) * | 2016-05-30 | 2016-10-12 | 上海华力微电子有限公司 | Photoetching mask, photoetching method of interconnection line graphics and preparation method of interconnection line |
| WO2016173311A1 (en) * | 2015-04-28 | 2016-11-03 | 厦门市三安光电科技有限公司 | Preparation method for gaas-based semiconductor device |
| CN109599345A (en) * | 2018-10-31 | 2019-04-09 | 厦门市三安集成电路有限公司 | A kind of method that Heterojunction Bipolar Transistors metal connecting line is not easy to break |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668388A (en) * | 1995-07-07 | 1997-09-16 | Thomson-Csf | Bipolar transistor with optimized structure |
| CN1855533A (en) * | 2005-04-21 | 2006-11-01 | 松下电器产业株式会社 | Heterojunction bipolar transistor and method for fabricating the same |
| CN103177957A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Method for avoiding generating metal sharp angles |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006332257A (en) * | 2005-05-25 | 2006-12-07 | Sony Corp | Hetero-junction semiconductor device and its manufacturing method |
| US7462892B2 (en) * | 2005-07-26 | 2008-12-09 | Sony Corporation | Semiconductor device |
| CN104867828B (en) * | 2015-04-28 | 2018-03-09 | 厦门市三安集成电路有限公司 | A kind of preparation method of GaAs based semiconductor device |
-
2015
- 2015-04-28 CN CN201510207719.7A patent/CN104867828B/en active Active
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2016
- 2016-02-18 WO PCT/CN2016/073992 patent/WO2016173311A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5668388A (en) * | 1995-07-07 | 1997-09-16 | Thomson-Csf | Bipolar transistor with optimized structure |
| CN1855533A (en) * | 2005-04-21 | 2006-11-01 | 松下电器产业株式会社 | Heterojunction bipolar transistor and method for fabricating the same |
| CN103177957A (en) * | 2011-12-21 | 2013-06-26 | 上海华虹Nec电子有限公司 | Method for avoiding generating metal sharp angles |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016173311A1 (en) * | 2015-04-28 | 2016-11-03 | 厦门市三安光电科技有限公司 | Preparation method for gaas-based semiconductor device |
| CN106019813A (en) * | 2016-05-30 | 2016-10-12 | 上海华力微电子有限公司 | Photoetching mask, photoetching method of interconnection line graphics and preparation method of interconnection line |
| CN109599345A (en) * | 2018-10-31 | 2019-04-09 | 厦门市三安集成电路有限公司 | A kind of method that Heterojunction Bipolar Transistors metal connecting line is not easy to break |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2016173311A1 (en) | 2016-11-03 |
| CN104867828B (en) | 2018-03-09 |
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