CN108389791B - Preparation method of GaN-based HEMT device source field plate and HEMT device - Google Patents
Preparation method of GaN-based HEMT device source field plate and HEMT device Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 5
- 239000002184 metal Substances 0.000 claims abstract description 45
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 43
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 43
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 43
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 43
- 229920002120 photoresistant polymer Polymers 0.000 claims description 43
- 238000005530 etching Methods 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 230000005684 electric field Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 3
- 238000012876 topography Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The invention is suitable for the technical field of semiconductors, and provides a preparation method of a source field plate of a GaN-based HEMT device and the HEMT device, wherein the method comprises the following steps: sequentially growing a SiN layer with a first thickness and a SiO layer with a second thickness on the upper surface of the device2A layer; removing the SiO2A portion of the layer corresponding to the first region; the SiO2The surface of the part of the remaining region of the layer corresponding to the second gate drain region facing the gate electrode region is a slope having a first inclination angle; sequentially removing the SiO2The layer and the SiN layer correspond to the source electrode region and the drain electrode region; growing a metal layer with a third thickness on the upper surface of the device corresponding to the source field plate region; the metal layer covers the SiO2And the layer is an inclined plane of the corresponding part of the second gate drain region. The field plate structure prepared by the invention is a wedge-shaped structure, so that the tube core breakdown voltage can be obviously improved, the circuit collapse can be inhibited, and the performance of the device can be obviously improved.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a source field plate of a GaN-based HEMT device and the HEMT device.
Background
The GaN device has the advantages of high breakdown voltage, high power density, high electron mobility, high electron saturation drift velocity and the like, and has wide application prospects in the military and civil fields of radar, aerospace, communication, power electronics and the like.
A GaN-based High Electron Mobility Transistor (HEMT) is a commonly used semiconductor device. In the working process of the GaN-based HEMT device, the drain end voltage can reach more than 50V, and the grid end voltage is generally-5V, so that the drain end grid edge electric field can reach MV/cm magnitude when the device works. Because the GaN material has a very obvious inverse piezoelectric effect, the GaN material generates lattice distortion due to a strong electric field between the gate and the drain, particularly, the electric field at the edge of the gate at the drain end is strongest, and an electron trap, a microcrack and the like can be generated at the position of the device in the long-term working process, so that the device is unstable and even fails. In order to inhibit the peak electric field at the edge of the drain terminal gate, a gate field plate or a source field plate can be added, so that the peak electric field distribution and the electric field intensity between the gate and the drain electrode are changed, the electric field between the gate and the drain electrode is relatively uniform, the voltage resistance, the stability and the reliability of the device are improved, in addition, the GaN tube core current collapse phenomenon can be inhibited by adding the field plate, and the performance of the device is improved. At present, a common field plate structure is a flat plate structure, but the flat plate field plate structure has limited effects of improving the breakdown voltage and the uniform current collapse of a device, and the performance of the device cannot be well improved.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method for manufacturing a source field plate of a GaN-based HEMT device and a HEMT device, so as to solve the problem that the source field plate structure in the prior art cannot improve the performance of the GaN-based HEMT device well.
The first aspect of the embodiments of the present invention provides a method for manufacturing a source field plate of a GaN-based HEMT device, including:
sequentially growing a SiN layer with a first thickness and a SiO layer with a second thickness on the upper surface of the device2A layer;
removing the SiO2A portion of the layer corresponding to a first region, wherein the first region includes a source gate region, a gate electrode region, and a first gate drain region, the first gate drain region being connected to the gate electrode region; the SiO2The surface of the part of the rest region of the layer, which corresponds to the second gate drain region and faces the gate electrode region, is a slope with a first inclination angle, and the second gate drain region is a region of the gate drain region except the first gate drain region;
sequentially removing the SiO2The part of the SiN layer corresponding to the source electrode region and the part of the SiN layer corresponding to the drain electrode region;
growing a metal layer with a third thickness on the upper surface of the device corresponding to the source field plate region; the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region; the gate structure comprises a source electrode region, a gate electrode region and a gate drain region, wherein the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer covers the SiO2And the layer is an inclined plane of the corresponding part of the second gate drain region.
Optionally, the SiO is removed2A portion of the layer corresponding to the first region, comprising:
by a photolithographic process on the SiO2Coating a first photoresist layer on the upper surface of the part of the layer corresponding to the second region, wherein the surface of the part of the first photoresist layer corresponding to the second gate drain region, which faces the gate electrode region, is an inclined plane with a second inclination angle; the second region is a region of the device other than the first region;
etching the SiO by an etching process2Etching the part of the layer corresponding to the first region to the upper surface of the SiN layer; wherein the SiO2The etch rate ratio of the layer to the first photoresist layer is 0.9:1 to 1.1: 1;
and removing the first photoresist layer.
Optionally, the first inclination angle is 30 ° to 45 °.
Further, the second inclination angle is 30 ° to 45 °.
Optionally, the SiO is removed sequentially2The portions of the SiN layer corresponding to the source electrode region and the drain electrode region comprise:
coating a second photoresist layer on the part of the device corresponding to the third area through a photoetching process; wherein the third region is a region of the device other than the source electrode region and the drain electrode region;
removing the SiO by an etching process2The part of the layer corresponding to the source electrode region and the part corresponding to the drain electrode regionRemoving the portions of the SiN layer corresponding to the source electrode region and the drain electrode region;
and removing the second photoresist layer.
Optionally, the growing a metal layer with a third thickness on the upper surface of the device corresponding to the source field plate region includes:
coating a third photoresist layer on the upper surface of the device corresponding to a non-source field plate area through a photoetching process, wherein the non-source field plate area is an area of the device except the source field plate area;
evaporating a metal layer on the upper surface of the device after covering the third photoresist layer by an electron beam evaporation process;
and removing the third photoresist layer.
Optionally, the metal layer includes a Ti metal layer and an Au metal layer on an upper surface of the Ti metal layer.
Further, the thickness of the Ti metal layer is 50 to 100 nanometers, and the thickness of the Au metal layer is 300 to 600 nanometers.
Optionally, the SiN layer has a thickness of 50 nm to 200 nm, and the SiO layer is formed on the substrate2The thickness of the layer is 500 nm to 800 nm.
A second aspect of an embodiment of the present invention provides an HEMT device, including a HEMT device body, in which a source gate region, a gate electrode region, and a gate drain region of the HEMT device body cover an SiN layer having a first thickness, and an upper surface of a portion of the SiN layer corresponding to the first gate drain region covers an SiO layer having a second thickness2Layer of said SiO2The surface of the layer facing the gate electrode region is beveled; wherein the first gate drain region is connected with the drain electrode region; a source field plate region on the upper surface of the HEMT device covers a metal layer with a third thickness, the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region, and the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer covers the SiO2And the layer is an inclined plane of the part corresponding to the first gate drain region.
Examples of the inventionCompared with the prior art, the beneficial effects are that: in the embodiment of the invention, the SiN layer with the first thickness and the SiO layer with the second thickness are sequentially grown on the upper surface of the device2Layer, then SiO is removed2A portion of the layer corresponding to the first region, and leaving SiO remaining2The surface of the layer corresponding to the second gate drain region facing the gate electrode region is an inclined plane with a first inclination angle, and SiO is removed2A part of the layer corresponding to the source electrode region and a part of the layer corresponding to the drain electrode region and a part of the SiN layer corresponding to the source electrode region and a part corresponding to the drain electrode region, and finally, a metal layer with a third thickness is grown on the upper surface of the device and the part corresponding to the source field plate region, and the metal layer covers the SiO2And the inclined surfaces of the layer and the corresponding part of the second gate drain region, thereby preparing the wedge-shaped source field plate. Compared with a flat-plate source field plate, the wedge-shaped source field plate can remarkably improve the tube core breakdown voltage and inhibit the circuit from collapsing, so that the performance of the device is remarkably improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a method for manufacturing a source field plate of a GaN-based HEMT device according to a first embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating an implementation of a method for manufacturing a source field plate of a GaN-based HEMT device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an implementation method of step S202 in fig. 2 according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an implementation method of step S203 in fig. 2 according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a HEMT device according to the second embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1(1), the GaN-based HEMT device includes a GaN wafer 101, a source electrode 102 and a drain electrode 103 are disposed on the GaN wafer 101, a dielectric layer 104 is disposed on a source-drain region on an upper surface of the GaN wafer 101, a gate electrode 105 is disposed on an upper surface of the dielectric layer 104, and the gate electrode 105 is located between the source electrode 102 and the drain electrode 103.
In the embodiment of the present invention, the source electrode region is a region where the source electrode 102 is located, the gate electrode region is a region where the gate electrode 105 is located, the drain electrode region is a region where the drain electrode 103 is located, the source gate region is a region between the source electrode 102 and the gate electrode 105, the gate drain region is a region between the gate electrode 105 and the drain electrode 103, and the source drain region is a region between the source electrode 102 and the drain electrode 103. For convenience of illustration, the gate drain region is divided into a first gate drain region and a second gate drain region, and the first gate drain region and the second gate drain region cover the entire gate drain region, wherein the first gate drain region is connected to the gate electrode region, and the second gate drain region is connected to the drain electrode region. The GaN-based HEMT device is divided into a first area and a second area, the first area and the second area cover the whole GaN-based HEMT device, the first area comprises a source gate area, a gate electrode area and a first gate drain area, and the second area comprises a source electrode area, a second gate drain area and a drain electrode area. The GaN-based HEMT device is further divided into a source field plate area and a non-source field plate area, wherein the source field plate area is an area where the source field plate is located, and the non-source field plate area is an area except the source field plate area. The source field plate region comprises a preset part of a source electrode region, a source grid region, a grid electrode region and a preset part of a grid drain region, the preset part of the grid drain region comprises preset parts of a first grid drain region and a second grid drain region, and the preset part of the source electrode region, the preset part of the source grid region, the preset part of the grid electrode region and the preset parts of the grid drain region are sequentially connected.
Example one
Referring to fig. 2, a method for manufacturing a source field plate of a GaN-based HEMT device includes:
step S201, growing a SiN layer with a first thickness and a SiO layer with a second thickness on the upper surface of the device in sequence2And (3) a layer.
In an embodiment of the invention, please refer to fig. 1(2), the GaN-based HEMT device is first cleaned, and then a SiN layer 106 with a first thickness and a SiO layer with a second thickness are sequentially deposited on the upper surface of the device by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process2Layer 107, SiN layer 106 and SiO2Layer 107 serves as a dielectric layer for two high etch selectivity ratios. SiN layer 106 and SiO2The thickness of the layer 107 can be set according to actual needs, and preferably, the thickness of the SiN layer 106 is 50 nm to 200 nm, SiO2The thickness of layer 107 is 50 nanometers to 800 nanometers.
Step S202, removing the SiO2A portion of the layer corresponding to a first region, wherein the first region includes a source gate region, a gate electrode region, and a first gate drain region, the first gate drain region being connected to the gate electrode region; the SiO2The surface of the part of the rest region of the layer, which corresponds to the second gate drain region, facing the gate electrode region is a slope with a first inclination angle, and the second gate drain region is the region of the gate drain region except the first gate drain region.
In the embodiment of the present invention, please refer to fig. 1(3), SiO removal is performed2The SiO in the portion of layer 107 corresponding to the first region remains in the portion corresponding to the second region2Layer 107, and the remaining SiO2The surface of the portion of the layer 107 corresponding to the second gate drain region facing the gate electrode region is sloped at an angle of 30 ° to 45 °.
Optionally, the specific implementation manner of step S202 is: by a photolithographic process on the SiO2Coating a first photoresist layer on the upper surface of the part corresponding to the second region; etching the SiO by an etching process2Layer and the firstEtching the part corresponding to the area to the upper surface of the SiN layer; wherein the SiO2The etch rate ratio of the layer to the first photoresist layer is 0.9:1 to 1.1: 1; and removing the first photoresist layer.
In the embodiment of the present invention, please refer to FIG. 3, first, in SiO2The upper surface of layer 107 is coated with a photoresist layer having a thickness of 3 to 4 microns and then the SiO layer is removed by a pre-bake, exposure, development, and curing process2A first photoresist layer 109 is formed on the photoresist on the upper surface of the layer 107 corresponding to the first region, such that the first photoresist layer 109 only covers the SiO2The upper surface of the layer 107 corresponding to the second region exposes the pattern to be etched. The surface of the first photoresist layer 109 corresponding to the second gate drain region facing the gate electrode region is inclined at an angle of 30 ° to 45 ° by controlling the hard coating process. Etching the exposed SiO by using coupled plasma etching equipment2Layer 107, etch to stop on SiN layer 106, wherein SiO2The etch rate ratio of layer 107 to first photoresist layer 109 is 0.9:1 to 1.1:1, leaving SiO remaining2The topography of layer 107 replicates that of the photoresist layer, i.e. ensures SiO2The topography of layer 107 is substantially the same as the topography of first photoresist layer 109 while, at the same time, the SiO2The etch rate ratio of layer 107 to SiN layer 106 is greater than 5:1, ensuring that the etch stops on SiN layer 106. Finally, the first photoresist layer 109 is removed. The surface of the first photoresist layer 109, which faces the gate electrode, corresponding to the source electrode region may be an inclined surface or a right-angle surface, which is not limited herein. When the surface is an inclined surface, the etched SiO2The surface of the portion of layer 107 corresponding to the source electrode region facing the gate electrode region is also beveled, when the surface is at right angles, the etched SiO2The surface of the portion of layer 107 corresponding to the source electrode region facing the gate electrode region is a right angle surface.
Step S203, removing the SiO in sequence2The SiN layer comprises a part corresponding to the source electrode region and a part corresponding to the drain electrode region.
In the embodiment of the invention, please refer to fig. 1 and 4, the SiN layer 10 on the upper surface of the source electrode is removed6 and SiO2Layer 107, removing SiN layer 106 and SiO on the upper surface of the drain electrode2Layer 107 to expose the source electrode 102 and the drain electrode 103.
Optionally, the specific implementation manner of step S203 is: coating a second photoresist layer on the part of the device corresponding to the third area through a photoetching process; wherein the third region is a region other than the source electrode region and the drain electrode region; removing the SiN layer and the SiO layer on the upper surface of the source electrode by etching2A layer for removing the SiN layer and the SiO layer on the upper surface of the drain electrode2A layer; and removing the second photoresist layer.
In the embodiment of the present invention, referring to fig. 4, first, a photoresist is coated on a third region of the device through a photolithography process, portions of the photoresist layer corresponding to the source electrode and the drain electrode are removed through a pre-baking, developing, exposing, and hardening processes to form a second photoresist layer 110, and then, SiO on the upper surface of the source electrode is respectively etched through an inductively coupled plasma etching apparatus2Layer 107 and SiN layer 106, etching SiO on the upper surface of the drain electrode2The layer 107 and the SiN layer 106 exposing the source electrode 102 and the drain electrode 103, and finally, the second photoresist layer 110 is removed.
Step S204, growing a metal layer with a third thickness on the upper surface of the device corresponding to the source field plate region; the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region; the gate structure comprises a source electrode region, a gate electrode region and a gate drain region, wherein the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer covers the SiO2And the layer is an inclined plane of the corresponding part of the second gate drain region.
In the embodiment of the present invention, referring to fig. 1(5), a metal layer 108 is grown on a portion of the upper surface of the device corresponding to the source field plate region by an electron beam evaporation process, where the metal layer 108 includes a Ti metal layer and an Au metal layer on the upper surface of the Ti metal layer, where the thickness of the Ti metal layer is 50 nm to 100 nm, and the thickness of the Au metal layer is 300 nm to 600 nm.
Optionally, the specific implementation manner of step S204 is: covering a third photoresist layer on the upper surface of the device corresponding to the non-source field plate region through a photoetching process; evaporating a metal layer on the upper surface of the device after covering the third photoresist layer by an electron beam evaporation process; and removing the third photoresist layer.
In the embodiment of the invention, firstly, a photoresist layer covers a non-source field plate region, then the electron beam evaporation table is used for evaporating the metal layer, and finally, the third photoresist layer is stripped through a photoresist stripping process to form the source field plate. Due to SiO2The surface of the portion of the layer corresponding to the second gate drain region facing the gate electrode region is a slope having a first inclination angle, and the surface of the portion of the metal layer corresponding to the second gate drain region facing the gate electrode region is also a slope having a first inclination angle.
In the embodiment of the invention, the SiN layer 106 with the first thickness and the SiO layer with the second thickness are sequentially grown on the upper surface of the device2Layer 107, then SiO is removed2The portion of layer 107 corresponding to the first region, and leaving the SiO remaining2The surface of the layer 107 corresponding to the second gate drain region facing the gate electrode region is a bevel with a first tilt angle, and the SiO is removed2A part of the layer 107 corresponding to the source electrode region and a part of the layer 106 corresponding to the drain electrode region and a part of the SiN layer 106 corresponding to the source electrode region and the drain electrode region, and finally, a metal layer 108 with a third thickness is grown on the upper surface of the device corresponding to the source field plate region, and the metal layer 108 covers the SiO layer2The slope of the portion of layer 107 corresponding to the second gate drain region produces a tapered source field plate. Compared with a flat-plate source field plate, the wedge-shaped source field plate can remarkably improve the tube core breakdown voltage and inhibit the circuit from collapsing, so that the performance of the device is remarkably improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Example two
Referring to fig. 5, a HEMT device includes a HEMT device body, a source gate region and a gate electrode of the HEMT device bodyThe electrode region and the gate drain region are covered with a SiN layer 106 with a first thickness, and the upper surface of the SiN layer 106 corresponding to the first gate drain region is covered with SiO with a second thickness2Layer 107 of SiO2The surface of layer 107 facing the gate electrode region is beveled; wherein the first gate drain region is connected with the drain electrode region; a source field plate region on the upper surface of the HEMT device covers a metal layer 108 with a third thickness, the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region, and the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer 108 covers the SiO2The layer 107 is a slope of a portion corresponding to the first gate drain region.
In the HEMT device provided in the embodiment of the present invention, the SiN layer 106 has a first thickness and the SiO layer has a second thickness2Layer 107 and metal layer 108 of a third thickness form a tapered source field plate that is fabricated using the method of the first embodiment of the present invention and has the beneficial effects of the first embodiment of the present invention.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. A preparation method of a GaN-based HEMT device source field plate is characterized by comprising the following steps:
sequentially growing a SiN layer with a first thickness and a SiO layer with a second thickness on the upper surface of the device2A layer;
removing the SiO2A portion of the layer corresponding to a first region, wherein the first region includes a source gate region, a gate electrode region, and a first gate drain region, the first gate drain region and the gateConnecting electrode areas; the SiO2The surface of the part of the rest region of the layer, which corresponds to the second gate drain region and faces the gate electrode region, is a slope with a first inclination angle, and the second gate drain region is a region of the gate drain region except the first gate drain region; removing the SiO2A portion of the layer corresponding to the first region, comprising: by a photolithographic process on the SiO2Coating a first photoresist layer on the upper surface of the part of the layer corresponding to the second region, wherein the surface of the part of the first photoresist layer corresponding to the second gate drain region, which faces the gate electrode region, is an inclined plane with a second inclination angle; the second region is a region of the device other than the first region; etching the SiO by an etching process2Etching the part of the layer corresponding to the first region to the upper surface of the SiN layer; wherein the SiO2The etch rate ratio of the layer to the first photoresist layer is 0.9:1 to 1.1: 1; removing the first photoresist layer; at the same time, SiO2The etch rate ratio of the layer to the SiN layer is greater than 5: 1; the first inclination angle is 30 to 45 °;
sequentially removing the SiO2The part of the SiN layer corresponding to the source electrode region and the part of the SiN layer corresponding to the drain electrode region;
growing a metal layer with a third thickness on the upper surface of the device corresponding to the source field plate region; the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region; the gate structure comprises a source electrode region, a gate electrode region and a gate drain region, wherein the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer covers the SiO2And the layer is an inclined plane of the corresponding part of the second gate drain region.
2. The method of fabricating a source field plate of a GaN-based HEMT device according to claim 1, wherein said second slope angle is from 30 ° to 45 °.
3. The method according to claim 1, for fabricating a source field plate of a GaN-based HEMT device,characterized in that the SiO is removed in sequence2The portions of the SiN layer corresponding to the source electrode region and the drain electrode region comprise:
coating a second photoresist layer on the part of the device corresponding to the third area through a photoetching process; wherein the third region is a region of the device other than the source electrode region and the drain electrode region;
removing the SiO by an etching process2Removing the portions of the SiN layer corresponding to the source electrode region and the drain electrode region;
and removing the second photoresist layer.
4. The method for manufacturing a source field plate of a GaN-based HEMT device of claim 1, wherein said growing a metal layer of a third thickness on the upper surface of said device corresponding to the source field plate region comprises:
coating a third photoresist layer on the upper surface of the device corresponding to a non-source field plate area through a photoetching process, wherein the non-source field plate area is an area of the device except the source field plate area;
evaporating a metal layer on the upper surface of the device after covering the third photoresist layer by an electron beam evaporation process;
and removing the third photoresist layer.
5. The method of claim 1, wherein the metal layer comprises a Ti metal layer and an Au metal layer on an upper surface of the Ti metal layer.
6. The method for manufacturing a source field plate of a GaN-based HEMT device of claim 5, wherein the thickness of the Ti metal layer is 50 nm to 100 nm, and the thickness of the Au metal layer is 300 nm to 600 nm.
7. Such as rightThe method for manufacturing a source field plate of a GaN-based HEMT device according to any of claims 1 to 6, wherein the thickness of the SiN layer is 50 nm to 200 nm, and the SiO layer is formed of a silicon oxide (SiO)2The thickness of the layer is 500 nm to 800 nm.
8. The HEMT device comprises a HEMT device body, and is characterized in that a source gate region, a gate electrode region and a gate drain region of the HEMT device body are covered with an SiN layer with a first thickness, and the upper surface of the SiN layer corresponding to a second gate drain region is covered with an SiO layer with a second thickness2Layer of said SiO2The surface of the layer facing the gate electrode region is an inclined plane, the inclination angle of the inclined plane is 30-45 degrees, the thickness of the SiN layer is 50-200 nanometers, and the SiO layer is2The thickness of the layer is 500 to 800 nanometers; the grid drain region comprises a first grid drain region and a second grid drain region, wherein the first grid drain region is connected with the grid electrode region, and the second grid drain region is connected with the drain electrode region; a source field plate region on the upper surface of the HEMT device covers a metal layer with a third thickness, the source field plate region comprises a preset part of a source electrode region, a source gate region, a gate electrode region and a preset part of a gate drain region, and the preset part of the source electrode region, the source gate region, the gate electrode region and the preset part of the gate drain region are sequentially connected; the metal layer covers the SiO2And the layer is an inclined plane of the corresponding part of the second gate drain region.
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