CN112652656A - Power device and manufacturing method thereof - Google Patents
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- CN112652656A CN112652656A CN201910954252.0A CN201910954252A CN112652656A CN 112652656 A CN112652656 A CN 112652656A CN 201910954252 A CN201910954252 A CN 201910954252A CN 112652656 A CN112652656 A CN 112652656A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 80
- 238000002955 isolation Methods 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 20
- 230000001681 protective effect Effects 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 11
- 229910002704 AlGaN Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 230000005684 electric field Effects 0.000 abstract description 14
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 13
- 229910002601 GaN Inorganic materials 0.000 description 12
- 230000008569 process Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000010329 laser etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000000750 progressive effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The technical scheme includes that an isolation insulating medium layer is formed on a grid electrode protecting medium layer, the isolation insulating medium layer is provided with an opening, the opening at least exposes the grid electrode protecting medium layer covering the grid electrode, a metal field plate layer is formed on the surface of the isolation insulating medium layer, and the metal field plate layer at least covers the side wall of the opening between the grid electrode and the drain electrode. Therefore, according to the technical scheme, the metal field plate layer with the slope is arranged on the side wall of the opening, the metal field plate layer with the slope can be formed between the grid and the drain electrode, the traditional multilayer field plate structure is replaced by the continuous metal field plate layer with the slope on the side wall of the opening, the electric field balance of the power device is improved, multiple field plate manufacturing processes are not needed, the manufacturing process is simple, and the manufacturing cost is low.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a power device and a manufacturing method thereof.
Background
Gallium nitride (GaN) as a wide bandgap semiconductor material can withstand higher operating voltage, and has higher power density and operable temperature range, so that a semiconductor device prepared from GaN has the advantages of high power density, low energy consumption, high frequency and high bandwidth.
GaN power devices are a common type of GaN semiconductor device. The GaN power device has a high operating voltage, which is particularly prone to high voltage breakdown, and in order to solve the problem of high voltage breakdown, the conventional GaN semiconductor device needs to have a plurality of insulating stacked metal field plate layers above the GaN power device.
Disclosure of Invention
In view of this, the technical solution of the present invention provides a power device and a manufacturing method thereof, and specifically discloses the following solutions:
a power device, comprising:
a substrate;
a semiconductor layer disposed on the surface of the substrate;
the grid electrode is arranged between the drain electrode and the source electrode;
a gate protective dielectric layer covering the gate and the semiconductor layer, the source and the drain exposing the gate protective dielectric layer;
the isolation insulating medium layer covers the grid electrode protection medium layer and is provided with an opening, and the opening at least exposes the grid electrode protection medium layer covering the grid electrode; in a first direction, the distance between the side wall of the opening between the grid electrode and the drain electrode and the grid electrode is gradually increased from the bottom of the opening to the top of the opening; the first direction is parallel to the substrate;
a metal field plate layer covering at least a sidewall of the opening between the gate and the drain.
Preferably, in the above power device, the semiconductor layer includes:
a GaN channel layer disposed on the surface of the substrate;
the AlGaN barrier layer is arranged on the surface of the GaN channel layer;
the grid electrode is positioned on the surface of the AlGaN barrier layer, the grid electrode protective dielectric layer covers the grid electrode, the grid electrode protective dielectric layer is provided with two openings positioned on two sides of the grid electrode, and the two openings expose the AlGaN barrier layer and are respectively used for arranging the source electrode and the drain electrode.
Preferably, in the power device, the source electrode and the drain electrode are made of the same conductive layer, and the thickness of the isolation insulating dielectric layer is greater than that of the conductive layer.
Preferably, in the above power device, the thickness of the isolation insulating dielectric layer is in the range
Preferably, in the power device, the material of the isolation insulating dielectric layer is oxide, silicon nitride, aluminum nitride, or carbon-doped silicon oxide.
Preferably, in the power device, the source electrode and the metal field plate layer are connected to set a low potential, and the drain electrode is connected to set a high potential.
Preferably, in the above power device, the metal field plate layer extends from a sidewall of the opening between the gate and the drain to outside the opening, and/or at least covers a part of the drain.
The invention also provides a manufacturing method of the power device, which comprises the following steps:
providing a substrate;
forming a semiconductor layer on the surface of the substrate;
forming a grid electrode, a source electrode and a drain electrode on the surface of the semiconductor layer, wherein the grid electrode is positioned between the drain electrode and the source electrode; a grid electrode protective dielectric layer covers the surfaces of the grid electrode and the semiconductor layer, and the source electrode and the drain electrode are exposed out of the grid electrode protective dielectric layer;
forming an isolation insulating medium layer which covers the source electrode and the drain electrode and is provided with an opening, wherein the opening at least exposes the grid electrode protective medium layer covering the grid electrode; the distance between the side wall of the opening between the grid electrode and the drain electrode and the grid electrode in the first direction is gradually increased from the bottom of the opening to the top of the opening; the first direction is parallel to the substrate;
and forming a metal field plate layer, wherein the metal field plate layer at least covers the side wall of the opening between the grid electrode and the drain electrode.
Preferably, in the above manufacturing method, the source electrode and the drain electrode are made of the same conductive layer, and the thickness of the isolation insulating dielectric layer is greater than that of the conductive layer.
Preferably, in the above manufacturing method, the thickness of the isolation insulating dielectric layer is in the range
Preferably, in the above manufacturing method, the method for forming the isolation insulating dielectric layer includes:
forming the isolation insulating medium layer covering the grid electrode protection medium layer, the source electrode and the drain electrode;
forming a first mask layer on the isolation insulating medium layer;
and etching the isolation insulating medium layer based on the first mask layer to form the opening.
Preferably, in the above manufacturing method, the method of forming the metal field plate layer includes:
forming the metal field plate layer covering the isolation insulating medium layer, the side wall of the opening and the bottom of the opening;
forming a second mask layer on the surface of the metal field plate layer;
and etching the metal field plate layer based on the second mask layer to form the patterned metal field plate layer.
Preferably, in the above manufacturing method, the patterned metal field plate layer extends from the sidewall of the opening between the gate and the drain to the outside of the opening, and/or at least covers part of the drain.
As can be seen from the above description, in the power device and the manufacturing method thereof provided by the technical scheme of the present invention, an isolation insulating dielectric layer is formed on a gate protecting dielectric layer, the isolation insulating dielectric layer has an opening, the opening at least exposes the gate protecting dielectric layer covering the gate, a metal field plate layer is formed on the surface of the isolation insulating dielectric layer, and the metal field plate layer at least covers the side wall of the opening between the gate and the drain. Therefore, according to the technical scheme, the metal field plate layer with the slope is arranged on the side wall of the opening, the metal field plate layer with the slope can be formed between the grid and the drain electrode, the traditional multilayer field plate structure is replaced by the continuous metal field plate layer with the slope on the side wall of the opening, the electric field balance of the power device is improved, multiple field plate manufacturing processes are not needed, the manufacturing process is simple, and the manufacturing cost is low.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a power device having multiple dielectric stacked metal field plate layers;
fig. 2 is a schematic structural diagram of a power device according to an embodiment of the present invention;
fig. 3-13 are process flow diagrams of a method for manufacturing a power device according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power device having a plurality of metal field plate layers stacked in an insulating manner, the power device shown in fig. 1 including: the structure comprises a substrate 11, a channel layer 12 arranged on the surface of the substrate 11, a barrier layer 13 arranged on the surface of the channel layer 12 and an electrode structure arranged on the surface of the barrier layer 13. The electrode structure includes: a gate 14, a source 16, and a drain 17, the gate 14 being located between the source 16 and the drain 17. The surface of the gate 14 is covered with a gate protection dielectric layer 15, and the gate protection dielectric layer 15 has openings on both sides of the gate 14, respectively, and the two openings leak out of the barrier layer 13 and are used for arranging a source electrode 16 and a drain electrode 17, respectively. A plurality of metal field plate layers 19 are arranged above the gate protection dielectric layer 15, and insulating dielectric layers 18 are arranged between two adjacent metal field plate layers 19 and between the gate protection dielectric layer 15 and the adjacent metal field plate layers 19.
Although the power device shown in fig. 1 has the advantages that the withstand voltage is improved through the multilayer metal field plate layer 19 which is stacked, and the problem of high-voltage breakdown is avoided, the metal field plate layer of the structure has poor electric field balance effect on the GaN power device, the manufacturing process of the multilayer metal field plate layer is complex, each metal field plate layer 19 needs to be manufactured with one insulating medium layer 18 and one metal layer separately, and the metal layer is etched through the etching process to form the metal field plate layer 19 which needs a pattern structure, so that the process is complex, and the manufacturing cost is high.
In order to solve the above problems, embodiments of the present invention provide a power device and a manufacturing method thereof, in which a specific opening is formed in an isolation insulating dielectric layer, a metal field plate layer is disposed on a sidewall of the opening, a metal field plate layer with a slope may be formed between a gate and a drain, and a conventional multi-layer field plate structure is replaced by a continuous metal field plate layer with a slope on the sidewall of the opening, so that the purpose of improving voltage resistance and avoiding breakdown is achieved, the electric field balance of the power device is improved, and a multiple field plate manufacturing process is not required, so that the manufacturing process is simple and the manufacturing cost is low.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a power device according to an embodiment of the present invention, where the power device includes: a substrate 21; a semiconductor layer 20 provided on a surface of the substrate 21; a gate electrode 24, a source electrode 26 and a drain electrode 27 disposed on the surface of the semiconductor layer 20, wherein the gate electrode 24 is located between the drain electrode 27 and the source electrode 26; a gate protective dielectric layer 25 covering the gate 24 and the semiconductor layer 20, the source 26 and the drain 27 exposing the gate protective dielectric layer 25; an isolation insulating dielectric layer 28 covering the gate protecting dielectric layer 25, wherein the isolation insulating dielectric layer 28 has an opening K, and the opening K at least exposes the gate protecting dielectric layer 25 covering the gate 24; in the first direction X, a distance L between a sidewall of the opening K between the gate 24 and the drain 27 and the gate 24 is gradually increased from a bottom of the opening K to a top of the opening K; the first direction X is parallel to the substrate 21; a metal field plate layer 29, the metal field plate layer 29 covering at least a sidewall of the opening K between the gate 24 and the drain 27.
The distance L between the sidewall of the opening K between the gate 24 and the drain 27 and the gate 24 in the first direction X gradually increases from the bottom of the opening K to the top of the opening K, specifically, the distance L gradually increases in a second direction Y, and the second direction Y is perpendicular to the first direction X and is directed to the semiconductor layer 20 from the substrate 21.
In the power device according to the embodiment of the invention, the specific opening K is formed in the isolation insulating dielectric layer 28, the metal field plate layer 29 is arranged on the side wall of the opening K, the metal field plate layer 29 with the slope can be formed between the gate 24 and the drain 27, and the continuous metal field plate layer 29 with the slope on the side wall of the opening K replaces the traditional multilayer field plate structure, so that the purpose of improving the withstand voltage and avoiding the breakdown is achieved, the electric field balance of the power device is improved, multiple field plate manufacturing processes are not needed, the manufacturing process is simple, and the manufacturing cost is low.
Optionally, the semiconductor layer 20 includes: a GaN channel layer 22 disposed on a surface of the substrate 21; an AlGaN barrier layer 23 provided on a surface of the GaN channel layer 22; the gate 24 is located on the surface of the AlGaN blocking layer 23, the gate protective dielectric layer 25 covers the gate 24, the gate protective dielectric layer 25 has two openings located at two sides of the gate 24, and the two openings expose the AlGaN blocking layer 23 and are respectively used for arranging the source 26 and the drain 27.
The source electrode 26 and the drain electrode 27 are made of the same conductive layer. The thickness of the insulating dielectric layer 28 is greater than that of the conductive layer, that is, the height of the metal field plate layer 29 is greater than that of the drain 27, so that when the power device operates and a high potential is input to the drain 27, the electric field balance can be effectively improved by the metal field plate layer 29 on the sidewall. Optionally, the thickness of the isolation dielectric layer 28 is in the range
For example, can be
Or is
Such a thickness is effective for improving the electric field balance.
Optionally, the material of the isolation insulating dielectric layer 28 is oxide, or silicon nitride, or aluminum nitride, or carbon-doped silicon oxide. The gate protective dielectric layer 25 is made of oxide, silicon nitride, aluminum nitride, or carbon-doped silicon oxide. The materials of the isolation insulating dielectric layer 28 and the gate protection dielectric layer 25 may be set according to requirements, and may be the same or different, which is not specifically limited in the embodiment of the present invention.
The source 26 and the metal field plate layer 29 are used for connecting a set low potential, and the drain 27 is used for connecting a set high potential. The source electrode 26 and the metal field plate layer 29 can be provided with the pattern structure, so that the source electrode 26 and the metal field plate layer 29 are provided with the overlapped parts outside the opening K, and the overlapped parts are electrically connected through the through hole, so that the low potential required by the operation of the source electrode 24 can be reused as the input potential of the metal field plate layer 29, the potential floating is avoided, and the electric field balance of the power device is better ensured.
The metal field plate layer 29 extends from the sidewall of the opening K between the gate 24 and the drain 27 to the outside of the opening K and/or at least covers part of the drain 27. Preferably, the metal field plate layer 29 is arranged to extend from the sidewall of the opening K between the gate 24 and the drain 27 to the outside of the opening K, and completely cover the drain 27, so that the electric field of the drain 27 can be better uniform, and the electric field balance of the power device can be greatly improved.
The metal field plate layer 29 extends to the bottom of the opening K and may cover a portion or the entire gate 24. Preferably, the metal field plate layer 29 is disposed to extend to the bottom of the opening K, and is located between the gate 24 and the drain 27 without overlapping with the gate 24, and the height of the metal field plate layer 29 located at the bottom of the opening K is smaller than that of the gate 24, so as to effectively avoid the influence of a strong electric field on the gate 24 when a high potential is applied to the drain 27.
Therefore, in the power device provided by the embodiment of the invention, the traditional multilayer field plate structure can be replaced by the metal field plate layer 29 with the slope, the manufacturing process is simple, the manufacturing cost is low, and the problem of stress imbalance is avoided without the multilayer metal field plate structure.
Based on the foregoing power device embodiment, another embodiment of the present invention further provides a manufacturing method of a power device, which is used for manufacturing the power device in the foregoing embodiment, the manufacturing method is shown in fig. 3 to 13, and fig. 3 to 13 are process flow diagrams of a manufacturing method of a power device provided in an embodiment of the present invention, where the manufacturing method includes:
step S11: as shown in fig. 3, a substrate 21 is provided.
The substrate 21 is a semiconductor substrate, and may be a silicon substrate or other semiconductor material substrate, for example.
Step S12: as shown in fig. 4 and 5, a semiconductor layer 20 is formed on the surface of the substrate 21.
In this step, the method of forming the semiconductor layer 20 includes: first, as shown in fig. 4, a channel layer 22 is formed on the surface of a substrate 21, and a barrier layer 23 is formed on the surface of the channel layer 22. The channel layer 22 is a GaN channel layer, and the barrier layer 23 is an AlGaN barrier layer.
Step S13: as shown in fig. 6 to 9, a gate 24, a source 26, and a drain 27 are formed on the semiconductor layer.
The gate 24 is located between the drain 27 and the source 26; the gate 24 and the surface of the semiconductor layer 20 are covered with a gate protection dielectric layer 25, and the source 26 and the drain 27 expose the gate protection dielectric layer 25.
In this step, as shown in fig. 6, a gate 24 with a predetermined pattern structure is formed on the surface of the semiconductor layer 20, the gate 24 with a desired pattern structure may be formed through deposition and etching processes, or the gate 24 with a desired pattern structure may be directly formed through evaporation on a mask. Then, as shown in fig. 7, a gate protection dielectric layer 25 is formed to cover the gate 24 and the semiconductor layer 20, two openings are formed on the surface of the gate protection dielectric layer 25, the two openings are respectively used at two sides of the gate 24 to expose the barrier layer 23 at the bottom, and finally, the source electrode 26 and the drain electrode 27 are formed based on the two openings, and the source electrode 26 and the drain electrode 27 with the required pattern structure can be formed through deposition and etching processes, or the source electrode 26 and the drain electrode 27 with the required pattern structure can be directly formed through evaporation of a mask.
Step S14: as shown in fig. 10 to 11, forming an isolation insulating dielectric layer 28, where the isolation insulating dielectric layer 28 covers the source 26 and the drain 27 and has an opening K exposing at least the gate protecting dielectric layer 25 covering the gate 24; the distance L between the sidewall of the opening K between the gate 24 and the drain 27 and the gate 24 in the first direction X gradually increases from the bottom of the opening K to the top of the opening K; the first direction X is parallel to the substrate.
In this step, the method for forming the isolation insulating dielectric layer 28 includes:
first, as shown in fig. 10, the insulating dielectric layer 28 is formed to cover the gate protective dielectric layer 25, the source electrode 26, and the drain electrode 27. Then, a first mask layer is formed on the isolation insulating dielectric layer 28; the first mask layer may be a photoresist layer. And etching the isolation insulating medium layer 28 based on the first mask layer to form the opening K, as shown in fig. 11.
Step S15: as shown in fig. 12 and 13, a metal field plate layer 29 is formed, and the metal field plate layer 29 covers at least a sidewall of the opening K between the gate 24 and the drain 27.
In this step, the method of forming the metal field plate layer 29 includes: first, as shown in fig. 12, the metal field plate layer 29 covering the isolation insulating dielectric layer 28, the sidewall of the opening K, and the bottom of the opening K is formed; then, as shown in fig. 13, a second mask layer, which may be a photoresist layer, is formed on the surface of the metal field plate layer 29; finally, based on the second mask layer, the metal field plate layer 29 is etched to form the patterned metal field plate layer 29, and the second mask layer is removed, so that the final power device structure is as shown in fig. 2.
Optionally, the patterned metal field plate layer 29 extends from the sidewall of the opening K between the gate 24 and the drain 27 to the outside of the opening K, and/or at least covers part of the drain layer 27. The source electrode 26 and the drain electrode 27 are made of the same conductive layer, and the thickness of the isolation insulating dielectric layer 28 is larger than that of the conductive layer. The thickness of the isolating dielectric layer 28 is in the range of
The metal field plate layer 29 further comprises a portion at the bottom of said opening K, which portion 29 may be located between the gate 24 and the drain 27, or which portion 29 covers the gate 24 or completely covers the gate 24. The portion of metal field plate layer 29 is free from overlap with the sidewalls of the opening between gate 24 and source 26. Preferably, the metal field plate layer 29 is disposed between the gate 24 and the drain 27 without overlapping the gate 24, so that the metal field plate layer 29 is smaller than the gate 24, and the influence of the strong electric field on the gate 24 when the drain 27 applies a high potential can be avoided.
In the embodiment of the present invention, each etching process is described by taking a photoresist as a mask for etching, and the etching process may be dry etching or wet etching. In other ways, plasma etching or laser etching can be used.
If can form opening K through the plasma etching or the laser etching that can control the sculpture directionality, can make like this that opening K's lateral wall and keep apart curved surface between the insulating medium layer 28 top surface and be connected, make curved surface between opening K's lateral wall and the bottom connect, thereby can make the metal field plate 29 that forms be smooth curved surface structure at opening K's lateral wall and the juncture position of keeping apart insulating medium layer 28 top surface, be smooth curved surface structure at opening K's lateral wall and the juncture position of bottom, avoid having most advanced structure, thereby better assurance electric field homogeneity, better improvement electric field equilibrium.
According to the manufacturing method provided by the embodiment of the invention, the traditional multilayer laminated field plate structure is replaced by the metal field plate layer 29 with the slope, the manufacturing process is simple, the manufacturing cost is low, and the problem of uneven stress of the multilayer field plate structure is avoided.
The embodiments in the present description are described in a progressive manner, or in parallel, or in a combination of progressive manner and parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. For the manufacturing method disclosed by the embodiment, since the manufacturing method corresponds to the power device disclosed by the embodiment, the description is relatively simple, and relevant parts can be described by referring to the corresponding part of the power device.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (13)
1. A power device, comprising:
a substrate;
a semiconductor layer disposed on the surface of the substrate;
the grid electrode is arranged between the drain electrode and the source electrode;
a gate protective dielectric layer covering the gate and the semiconductor layer, the source and the drain exposing the gate protective dielectric layer;
the isolation insulating medium layer covers the grid electrode protection medium layer and is provided with an opening, and the opening at least exposes the grid electrode protection medium layer covering the grid electrode; in a first direction, the distance between the side wall of the opening between the grid electrode and the drain electrode and the grid electrode is gradually increased from the bottom of the opening to the top of the opening; the first direction is parallel to the substrate;
a metal field plate layer covering at least a sidewall of the opening between the gate and the drain.
2. The power device of claim 1, wherein the semiconductor layer comprises:
a GaN channel layer disposed on the surface of the substrate;
the AlGaN barrier layer is arranged on the surface of the GaN channel layer;
the grid electrode is positioned on the surface of the AlGaN barrier layer, the grid electrode protective dielectric layer covers the grid electrode, the grid electrode protective dielectric layer is provided with two openings positioned on two sides of the grid electrode, and the two openings expose the AlGaN barrier layer and are respectively used for arranging the source electrode and the drain electrode.
3. The power device of claim 1, wherein the source and drain electrodes are fabricated from the same conductive layer, and the thickness of the isolating dielectric layer is greater than the thickness of the conductive layer.
4. The power device of claim 3, wherein the thickness of the isolating dielectric layer is in the range of
5. The power device of claim 1, wherein the material of the isolation insulating dielectric layer is an oxide, or silicon nitride, or aluminum nitride, or carbon-doped silicon oxide.
6. The power device of claim 1, wherein the source electrode is connected to the metal field plate layer at a low set potential and the drain electrode is connected to a high set potential.
7. The power device of claim 1, wherein the metal field plate layer extends from a sidewall of the opening between the gate and the drain to outside the opening and/or at least partially covers the drain.
8. A manufacturing method of a power device is characterized by comprising the following steps:
providing a substrate;
forming a semiconductor layer on the surface of the substrate;
forming a grid electrode, a source electrode and a drain electrode on the surface of the semiconductor layer, wherein the grid electrode is positioned between the drain electrode and the source electrode; a grid electrode protective dielectric layer covers the surfaces of the grid electrode and the semiconductor layer, and the source electrode and the drain electrode are exposed out of the grid electrode protective dielectric layer;
forming an isolation insulating medium layer which covers the source electrode and the drain electrode and is provided with an opening, wherein the opening at least exposes the grid electrode protective medium layer covering the grid electrode; the distance between the side wall of the opening between the grid electrode and the drain electrode and the grid electrode in the first direction is gradually increased from the bottom of the opening to the top of the opening; the first direction is parallel to the substrate;
and forming a metal field plate layer, wherein the metal field plate layer at least covers the side wall of the opening between the grid electrode and the drain electrode.
9. The method according to claim 8, wherein the source electrode and the drain electrode are made of the same conductive layer, and the thickness of the isolation insulating dielectric layer is greater than that of the conductive layer.
10. The method of claim 8, wherein the thickness of the isolation dielectric layer is in the range of
11. The method for manufacturing the semiconductor device according to claim 8, wherein the method for forming the isolation insulating dielectric layer comprises the following steps:
forming the isolation insulating medium layer covering the grid electrode protection medium layer, the source electrode and the drain electrode;
forming a first mask layer on the isolation insulating medium layer;
and etching the isolation insulating medium layer based on the first mask layer to form the opening.
12. The method of manufacturing according to claim 8, wherein the method of forming the metal field plate layer comprises:
forming the metal field plate layer covering the isolation insulating medium layer, the side wall of the opening and the bottom of the opening;
forming a second mask layer on the surface of the metal field plate layer;
and etching the metal field plate layer based on the second mask layer to form the patterned metal field plate layer.
13. The method of claim 12, wherein the patterned metal field plate layer extends from a sidewall of the opening between the gate and the drain to outside the opening and/or at least partially covers the drain.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| JP2015192060A (en) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | Field-effect transistor and method of manufacturing the same |
| CN105448975A (en) * | 2015-12-03 | 2016-03-30 | 西安电子科技大学 | Composite step field plate grooved-gate high electron mobility transistor (HEMT) high-voltage device and fabrication method thereof |
| US20170077282A1 (en) * | 2015-09-15 | 2017-03-16 | Electronics And Telecommunications Research Institute | Electronical device |
| CN106653825A (en) * | 2015-10-28 | 2017-05-10 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| US20170263724A1 (en) * | 2016-03-11 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2017220508A (en) * | 2016-06-06 | 2017-12-14 | サンケン電気株式会社 | Semiconductor device |
| CN108389791A (en) * | 2018-02-28 | 2018-08-10 | 中国电子科技集团公司第十三研究所 | The preparation method and HEMT device of GaN base HEMT device source field plate |
-
2019
- 2019-10-09 CN CN201910954252.0A patent/CN112652656A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015192060A (en) * | 2014-03-28 | 2015-11-02 | 株式会社東芝 | Field-effect transistor and method of manufacturing the same |
| CN104332498A (en) * | 2014-09-01 | 2015-02-04 | 苏州捷芯威半导体有限公司 | Oblique field plate power device and preparation method for oblique field plate power device |
| US20170077282A1 (en) * | 2015-09-15 | 2017-03-16 | Electronics And Telecommunications Research Institute | Electronical device |
| CN106653825A (en) * | 2015-10-28 | 2017-05-10 | 英飞凌科技奥地利有限公司 | Semiconductor device |
| CN105448975A (en) * | 2015-12-03 | 2016-03-30 | 西安电子科技大学 | Composite step field plate grooved-gate high electron mobility transistor (HEMT) high-voltage device and fabrication method thereof |
| US20170263724A1 (en) * | 2016-03-11 | 2017-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2017220508A (en) * | 2016-06-06 | 2017-12-14 | サンケン電気株式会社 | Semiconductor device |
| CN108389791A (en) * | 2018-02-28 | 2018-08-10 | 中国电子科技集团公司第十三研究所 | The preparation method and HEMT device of GaN base HEMT device source field plate |
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