JP6065393B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

For example, in a high-frequency device such as a GaN-based HEMT (High Electron Mobility Transistor), research and development of a device structure capable of reducing a capacity such as a gate capacity has been advanced in order to improve a high-frequency characteristic.
Conventionally, for example, as shown in FIG. 6, a passivation film 103 and an interlayer insulating film 104 are provided around the gate electrode 100, that is, between the gate electrode 100 and the source electrode 101 and between the gate electrode 100 and the drain electrode 102. Such a structure is generally provided with an insulating film.

JP 2007-59613 A

By the way, from the viewpoint of capacity reduction, it is desirable that a space (air) is provided between the gate electrode and the source electrode and between the gate electrode and the drain electrode.
However, at present, a passivation film and an interlayer insulating film for forming a wiring are indispensable.
Therefore, it is desired to reduce the capacitance generated by the insulating film existing between at least one of the gate electrode and the source electrode and between the gate electrode and the drain electrode, that is, to reduce the capacitance, and to further improve the high frequency characteristics.

The semiconductor device includes a semiconductor region, a gate electrode formed above the semiconductor region, a source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode, and the semiconductor region Provided above the first insulating film covering the surface, at least one of the first insulating film between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and having a lower dielectric than the first insulating film The second insulating film is provided at a position away from the gate electrode, is provided on the gate electrode side of the second insulating film, and has a higher dielectric than the second insulating film. A third insulating film having a dielectric constant, a fourth insulating film provided above the second insulating film, having a dielectric constant lower than that of the first insulating film, and provided on the gate electrode side of the fourth insulating film, No. 4 having a higher dielectric constant than 4 insulating films And an insulating film, an end portion of the gate electrode side of the fifth insulating film, a third have been in a position shifted from the end of the gate electrode side of the insulating film requirements Rukoto.
In addition, the semiconductor device includes a semiconductor region, a gate electrode formed above the semiconductor region, a source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode, and a semiconductor A first insulating film covering the surface of the region, and provided above at least one of the first insulating film between the source electrode and the gate electrode and between the drain electrode and the gate electrode; A second insulating film having a low dielectric constant, the second insulating film being provided at a position distant from the gate electrode, provided on the gate electrode side of the second insulating film, and more than the second insulating film. A sixth insulating film having a high dielectric constant, a third insulating film having a high dielectric constant, covering the second insulating film and the third insulating film, having a curved end on the gate electrode side, and having a higher dielectric constant than the second insulating film It is a requirement to provide a film.
In addition, the semiconductor device includes a semiconductor region, a gate electrode formed above the semiconductor region, a source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode, and a semiconductor A first insulating film covering the surface of the region, and provided above at least one of the first insulating film between the source electrode and the gate electrode and between the drain electrode and the gate electrode; A second insulating film having a low dielectric constant; and a seventh insulating film that covers the first insulating film, has a curved end on the gate electrode side, and has a higher dielectric constant than the second insulating film. Is a requirement.

The method for manufacturing the semiconductor device includes a step of forming a source electrode and a drain electrode on both sides of a gate electrode formation region above the semiconductor region, a step of forming a first insulating film covering the surface of the semiconductor region, A second insulating film having a lower dielectric constant than the first insulating film between at least one first insulating film between the source electrode and the gate electrode forming region and between the drain electrode and the gate electrode forming region. Forming a third insulating film having a dielectric constant higher than that of the second insulating film on the gate electrode formation region side of the second insulating film, and forming the second insulating film and the third insulating film A portion including at least one of a step of embedding with the fourth insulating film and a curved surface portion formed on both sides of the gate electrode formation region of the fourth insulating film, and covering the second insulating film and the third insulating film 4th to leave It is a requirement in that it comprises a step of removing the film.

  Therefore, according to the semiconductor device and the manufacturing method thereof, the capacitance generated by the insulating film existing between at least one of the gate electrode and the source electrode and between the gate electrode and the drain electrode can be reduced, that is, the capacitance can be reduced. There is an advantage that it can be realized and the high frequency characteristics can be improved.

1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. (A)-(F) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device concerning 1st Embodiment. (A)-(E) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device concerning 1st Embodiment. (A)-(F) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device concerning 2nd Embodiment. (A)-(F) are typical sectional drawings for demonstrating the manufacturing method of the semiconductor device concerning 3rd Embodiment. It is typical sectional drawing which shows the structure of the conventional semiconductor device.

Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
[First Embodiment]
First, the semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

The semiconductor device according to the present embodiment is a high-frequency device such as a GaN-based HEMT (field effect transistor). The high frequency device is also referred to as a high output device or a high frequency / high output device.
As shown in FIG. 1, the semiconductor device includes a semiconductor region 1, a gate electrode 2, a source electrode 3 and a drain electrode 4, a passivation insulating film 5 that covers the surface of the semiconductor region 1, and a low dielectric constant film 6. And an interlayer insulating film 7 constituting a wiring layer.

  Here, the semiconductor region 1 is a semiconductor laminated structure laminated on a semiconductor substrate, for example, a semiconductor laminated structure having a GaN-HEMT structure. For example, a semiconductor laminated structure in which a GaN layer or an AlGaN layer is laminated on a SiC substrate. Note that the present invention is not limited to this, and a semiconductor stacked structure having an InP-HEMT structure, for example, may be used. For example, a semiconductor laminated structure in which an InGaAs layer or an InAlAs layer is laminated on an InP substrate.

The gate electrode 2 is formed above the semiconductor region 1. Here, the gate electrode 2 is formed on the semiconductor region 1, and the insulating films 9 and 10 are in contact with the side surfaces thereof.
The source electrode 3 and the drain electrode 4 are formed above the semiconductor region 1 and are provided on both sides of the gate electrode 2.
Further, the passivation insulating film 5 is exposed between the source electrode 3 and the drain electrode 4, that is, between the source electrode 3 and the gate electrode 2 and between the drain electrode 4 and the gate electrode 2. It is provided so as to cover the surface. Further, the passivation insulating film 5 is provided so as to cover the side surfaces and the upper surface of the source electrode 3 and the drain electrode 4. Here, the passivation insulating film 5 is a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5. Note that the passivation insulating film 5 is also referred to as a first insulating film.

The passivation insulating film 5 is not limited to this, and is, for example, a SiO film (for example, SiO ₂ film) having a dielectric constant of about 3.8 to about 4.1, and a dielectric constant of about 7.0 to 8.0. An SiON film having a dielectric constant of about 8.5 or an AlO film having a dielectric constant of about 8.5 (for example, an Al ₂ O ₃ film) may be used.
The low dielectric constant film 6 is provided above the passivation insulating film 5 between the drain electrode 4 and the gate electrode 2. The low dielectric constant film 6 is an insulating film having a dielectric constant lower than that of the passivation insulating film 5 and has a dielectric constant of about 2.0 to about 3.0. For example, a film made of polysiloxane such as a SiOC film having a dielectric constant of about 2.9 or a film made of methylsiloxane such as an MSQ film having a dielectric constant of about 2.2 to about 2.7. The low dielectric constant film 6 is also referred to as a second insulating film, a low-k film, or a low dielectric constant insulating film.

In the present embodiment, the low dielectric constant film 6 is provided on the drain electrode 4 side. That is, it is provided at a position away from the gate electrode 2 between the gate electrode 2 and the drain electrode 4. An insulating film 8 having a dielectric constant higher than that of the low dielectric constant film 6 is provided adjacent to the gate electrode 2 side of the low dielectric constant film 6. Thus, the reliability is improved by not providing the low dielectric constant film 6 in the vicinity of the gate electrode 2. Here, the insulating film 8 is made of the same material as that of the passivation insulating film 5. That is, the insulating film 8 is a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5. The insulating film 8 is also referred to as a third insulating film.

The insulating film 8 is not limited to this, and similarly to the passivation insulating film 5, for example, a SiO film (for example, SiO ₂ film) having a dielectric constant of about 3.8 to about 4.1, a dielectric constant of about An SiON film of about 7.0 to 8.0, an AlO film (for example, Al ₂ O ₃ film) having a dielectric constant of about 8.5 may be used. The insulating film 8 may not be made of the same material as that of the passivation insulating film 5, and may be an insulating film made of a different material as long as the insulating film has a dielectric constant higher than that of the low dielectric constant film 6. There may be. In this case, the dielectric constant of the insulating film 8 may be higher or lower than the dielectric constant of the passivation insulating film 5.

The interlayer insulating film 7 is provided so as to fill the entire surface. Here, the interlayer insulating film 7 is made of the same material as that of the passivation insulating film 5. That is, the interlayer insulating film 7 is a SiN film (for example, Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5.
Note that the interlayer insulating film 7 is not limited to this, and similarly to the passivation insulating film 5, for example, an SiO film (for example, SiO ₂ film) having a dielectric constant of about 3.8 to about 4.1, a dielectric constant, etc. It may be a SiON film of about 7.0 to 8.0, an AlO film (for example, Al ₂ O ₃ film) having a dielectric constant of about 8.5, or the like. Further, the interlayer insulating film 7 does not have to be made of the same material as the passivation insulating film 5, and is an insulating film made of a different material as long as it is an insulating film having a dielectric constant higher than that of at least the low dielectric constant film 6. It may be. In this case, the dielectric constant of the interlayer insulating film 7 may be higher or lower than the dielectric constant of the passivation insulating film 5.

In particular, in this embodiment, a plurality of layers (here, three layers) each including the low dielectric constant film 6 and the insulating film 8 adjacent thereto are stacked above the passivation insulating film 5.
In the present embodiment, an insulating film 9 that covers the passivation insulating film 5 is provided. The insulating film 9 has an end portion (upper end portion) on the gate electrode 2 side having a curved surface, that is, a gently rounded shape, and has a dielectric constant higher than that of the low dielectric constant film 6. As described above, since the insulating film 9 has a curved end on the gate electrode 2 side, electric field concentration at the end on the gate electrode 2 side can be reduced, and the breakdown voltage can be improved. . That is, in the conventional structure (see FIG. 6), the electric field concentration was likely to occur at the end portion (indicated by symbol Y in FIG. 6) of the passivation insulating film 103 on the gate electrode 100 side. The passivation insulating film 5 is covered with an insulating film 9, and the end surface on the gate electrode 2 side is curved, thereby reducing electric field concentration and improving the withstand voltage. Here, the insulating film 9 is made of the same material as that of the passivation insulating film 5. That is, the insulating film 9 is a SiN film (for example, Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5. The insulating film 9 is also referred to as a seventh insulating film.

Similarly, in this embodiment, an insulating film 10 is provided to cover a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. Here, since a plurality of layers including the low dielectric constant film 6 and the insulating film 8 adjacent thereto are provided, an insulating film 10 covering each of these layers is provided. These insulating films 10 have an end portion (upper end portion) on the gate electrode 2 side having a curved surface shape, that is, a gently rounded shape, and a dielectric constant higher than that of the low dielectric constant film 6. . Thus, since the insulating film 10 has a curved end on the gate electrode 2 side, electric field concentration at the end on the gate electrode 2 side can be reduced, and the breakdown voltage can be improved. . Here, the insulating film 10 is made of the same material as that of the passivation insulating film 5. That is, the insulating film 10 is a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5. The insulating film 10 is also referred to as a sixth insulating film.

The insulating film 10 is not limited to this, and similarly to the passivation insulating film 5, for example, a SiO film (for example, SiO ₂ film) having a dielectric constant of about 3.8 to about 4.1, a dielectric constant of about An SiON film of about 7.0 to 8.0, an AlO film (for example, Al ₂ O ₃ film) having a dielectric constant of about 8.5 may be used. The insulating film 10 may not be made of the same material as that of the passivation insulating film 5, and may be an insulating film made of a different material as long as the insulating film has a dielectric constant higher than that of the low dielectric constant film 6. There may be. In this case, the dielectric constant of the insulating film 10 may be higher or lower than the dielectric constant of the passivation insulating film 5.

  In this embodiment, the end of the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto on the side of the gate electrode 2, that is, immediately between the drain electrode 4 and between the gate electrode 2 and the drain electrode 4. The end on the gate electrode 2 side of the insulating film 8 provided adjacent to the low dielectric constant film 6 provided up to about a half of the distance is the end on the gate electrode 2 side of the passivation insulating film 5 It is located closer to the drain electrode 4 side. That is, the end of the insulating film 8 on the gate electrode 2 side is shifted from the end of the passivation insulating film 5 on the gate electrode 2 side.

For this reason, the end on the gate electrode 2 side of the insulating film 10 covering the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is the end of the insulating film 9 covering the passivation insulating film 5 on the gate electrode 2 side. It is located closer to the drain electrode 4 than the portion. That is, the end of the insulating film 10 on the gate electrode 2 side is shifted from the end of the insulating film 9 on the gate electrode 2 side.
Further, in the layer composed of the plurality of low dielectric constant films 6 and the insulating film 8 adjacent thereto, the end portion on the gate electrode 2 side of the layer composed of the upper low dielectric constant film 6 and the insulating film 8 adjacent thereto, ie, The end of the insulating film 8 on the gate electrode 2 side is located closer to the drain electrode 4 than the end of the lower dielectric constant film 6 and the insulating film 8 adjacent thereto on the gate electrode 2 side. . That is, the end portion on the gate electrode 2 side of the layer composed of the upper low dielectric constant film 6 and the insulating film 8 adjacent thereto is the end of the layer composed of the lower low dielectric constant film 6 and the insulating film 8 adjacent thereto. The position is shifted from the end on the gate electrode 2 side. Here, the low dielectric constant film 6 of the upper layer is provided above the low dielectric constant film 6 of the lower layer. Note that the low dielectric constant film 6 in the upper layer is referred to as a fourth insulating film. The upper insulating film 8 is referred to as a fifth insulating film. The lower dielectric constant film 6 in the lower layer is referred to as a second insulating film. The lower insulating film 8 is referred to as a third insulating film.

  Therefore, the gate electrode 2 side end of the insulating film 10 covering the layer made of the upper low dielectric constant film 6 and the insulating film 8 adjacent thereto is formed on the lower low dielectric constant film 6 and the insulating film adjacent thereto. The insulating film 10 covering the layer made of the film 8 is located closer to the drain electrode 4 than the end on the gate electrode 2 side. That is, the gate electrode 2 side end of the insulating film 10 covering the layer made of the upper low dielectric constant film 6 and the insulating film 8 adjacent thereto is the lower low dielectric constant film 6 and the insulating film adjacent thereto. The position of the insulating film 10 covering the layer 8 is shifted from the end on the gate electrode 2 side. The insulating film 10 covering the upper layer is referred to as an eighth insulating film. The insulating film 10 covering the lower layer is referred to as a sixth insulating film.

Thus, in the present embodiment, the passivation insulating film 5, the insulating film 9 covering the passivation insulating film 5, the low dielectric constant film 6, and the insulating film 8 adjacent thereto are provided between the gate electrode 2 and the drain electrode 4. And an insulating film laminated structure 11 in which an insulating film 10 covering a layer made of a low dielectric constant film 6 and an insulating film 8 adjacent thereto is laminated.
Here, the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto, and the insulating film 10 covering the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto are repeatedly laminated three times. It has a structure. That is, a structure in which a layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto and an insulating film 10 covering the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto are alternately laminated. It has become. Here, the passivation insulating film 5, the insulating film 9, the insulating film 8, and the insulating film 10 are made of the same material. In this case, the insulating film laminated structure 11 includes a low dielectric constant film 6 and insulating films 5, 9, 8, 10 having a higher dielectric constant than the low dielectric constant film 6 between the gate electrode 2 and the drain electrode 4. And a laminated structure. Therefore, the insulating film laminated structure 11 is a structure in which insulating films made of two kinds of materials are laminated. That is, the insulating film laminated structure 11 is a structure in which two types of insulating films made of materials having different dielectric constants are laminated. When each insulating film 5, 9, 8, 10 is made of a different material, that is, made of a material having a different dielectric constant, the insulating film laminated structure 11 has two or more types of insulation made of materials having different dielectric constants. A structure in which films are stacked is obtained. In this case, at least one insulating film is the low dielectric constant film 6.

In this case, instead of the passivation insulating film 103 and the interlayer insulating film 104 (indicated by symbol X in FIG. 6) provided between the gate electrode 100 and the drain electrode 102 in the conventional device structure (see FIG. 6). As shown in FIG. 1, it has a device structure provided with the above-described insulating film laminated structure 11.
The insulating film laminated structure 11 includes the low dielectric constant film 6 having a dielectric constant lower than that of the passivation insulating film 5 and the interlayer insulating film 7. That is, the low dielectric constant film 6 and the insulating films 5, 9, 8, 10 having a higher dielectric constant are used in combination around the gate electrode 2, particularly between the gate electrode 2 and the drain electrode 4. By embedding, the capacity can be kept lower than that of the conventional structure. As a result, the capacitance generated by the insulating film can be reduced, that is, the capacitance can be reduced, which contributes to the improvement of the high frequency characteristics.

For example, a low dielectric constant film having a dielectric constant of about 2.5 and an insulating film having a dielectric constant of about 7.0 are stacked by about 40 nm, and the total thickness is about 300 nm. In the structure in which the gap between the gate electrode 2 and the drain electrode 4 is embedded, the capacity can be reduced by about 10 to about 12% compared to the structure in which only the insulating film having a dielectric constant of about 7.0 is embedded. It is.
In particular, in the present embodiment, as described above, the low dielectric constant film 6 is provided on the drain electrode 4 side, and is adjacent to the gate electrode 2 side of the low dielectric constant film 6 and is higher than the low dielectric constant film 6. By providing the insulating film 8 having a dielectric constant, the low dielectric constant film 6 is not provided in the vicinity of the gate electrode 2 to improve the reliability.

As described above, in the present embodiment, the capacitance is reduced and the high frequency characteristics are improved while preventing a decrease in reliability such as an increase in leakage current or a decrease in threshold. Yes.
Further, by providing the insulating film laminated structure 11 as described above to realize a reduction in capacitance, the distance between the gate electrode 2 and the drain electrode 4 can be shortened, thereby realizing a reduction in resistance. Thus, the efficiency can be improved.

Thus, by reducing the capacitance and shortening the distance between the gate electrode 2 and the drain electrode 4, the resistance between the source electrode and the drain electrode can be reduced, and the high frequency characteristics are improved. It is possible to achieve high efficiency.
In the insulating film laminated structure 11 described above, the end portion on the gate electrode 2 side is positioned on the drain electrode 4 side as the layer is composed of the upper low dielectric constant film 6 and the insulating film 8 adjacent thereto. ing. That is, a plurality of layers composed of a plurality of low dielectric constant films 6 and an insulating film 8 adjacent thereto are stacked stepwise. For this reason, the end on the gate electrode 2 side is positioned closer to the drain electrode 4 side as the insulating film 10 covers the upper dielectric layer 6 and the insulating film 8 adjacent thereto. That is, the insulating film 10 covering the layer made of the plurality of low dielectric constant films 6 and the insulating film 8 adjacent thereto is laminated stepwise. Thereby, the electric field concentration at the end of the insulating film laminated structure 11 on the gate electrode 2 side can be dispersed. Thereby, it is possible to suppress the deterioration of the insulating film from a defective portion of the insulating film due to the electric field concentration, and the breakdown voltage can be improved.

  Further, as described above, the insulating film 9 covering the passivation insulating film 5 and the insulating film 10 covering the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto have the end on the gate electrode 2 side. It is curved. That is, the end portions of the insulating films 9 and 10 exposed on the gate electrode 2 side of the insulating film stacked structure 11 are all curved. For this reason, the electric field concentration at the end on the gate electrode 2 side can be reduced. Thereby, it is possible to suppress the deterioration of the insulating film from a defective portion of the insulating film due to the electric field concentration, and the breakdown voltage can be improved.

As described above, the end portions of the insulating films 9 and 10 exposed on the gate electrode 2 side of the insulating film stacked structure 11 are all curved surfaces, and are further laminated in a staircase pattern. Electric field concentration between the gate electrode and the drain electrode can be relaxed and dispersed, and a high breakdown voltage can be realized. For this reason, high reliability can be ensured.
Further, in the present embodiment, an insulating film laminated structure 12 is provided between the gate electrode 2 and the source electrode 3, in which a passivation insulating film 5 and an insulating film 9 that covers the passivation insulating film 5 are laminated. Here, the passivation insulating film 5 and the insulating film 9 covering the same are made of the same material. For this reason, the insulating film laminated structure 12 is a structure in which insulating films made of the same material are laminated. That is, the insulating film laminated structure 12 is a structure in which two types of insulating films made of materials having the same dielectric constant are laminated.

Here, as described above, the insulating film 9 covering the passivation insulating film 5 has a curved end at the gate electrode 2 side. For this reason, the electric field concentration at the end on the gate electrode 2 side can be relaxed, and the breakdown voltage can be improved.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

That is, first, as shown in FIG. 2A, on both sides of the gate electrode formation region above the semiconductor region 1, that is, above the semiconductor stacked structure (GaN-HEMT structure) formed on the semiconductor substrate. The source electrode 3 and the drain electrode 4 are formed respectively.
Next, a passivation insulating film 5 (first insulating film) is formed so as to cover the entire surface including the surface of the semiconductor region 1. For example, a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5 is formed as the passivation insulating film 5.

  Next, as shown in FIG. 2B, the passivation insulating film 5 in the gate electrode formation region (here, the gate electrode lower formation region) is removed. Here, the passivation insulating film 5 in the gate electrode formation region is removed by photolithography technology, that is, by performing exposure, development, and etching after resist application, so that the lower dimension of the gate electrode 2 to be formed later is smaller. An opening 5 A having a slightly larger dimension is formed in the passivation insulating film 5. Further, here, the etching is performed so that the end surface of the passivation insulating film 5 formed on both sides of the gate electrode formation region on the gate electrode formation region side, that is, the end surface exposed to the opening 5A is vertical. That is, the end surface of the passivation insulating film 5 on the gate electrode formation region side is vertical.

Next, as shown in FIG. 2C, an insulating film 9 (fifth insulating film) is formed so as to cover the passivation insulating film 5. That is, the passivation insulating film 5 is embedded with the insulating film 9. Here, the passivation insulating film 5 is buried with an insulating film 9 made of the same material. For example, as the insulating film 9, a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5 is formed. In this case, when the passivation insulating film 5 is embedded with the insulating film 9 so as to cover the end surface of the passivation insulating film 5 formed as described above, which is perpendicular to the gate electrode formation region side, the insulating film 9 is covered. The curved surface portions 9A are formed on both sides of the gate electrode formation region. The insulating film 9 only needs to be able to form the curved surface portion 9A on the gate electrode formation region side, and does not need to be as thick as the insulating film 9. For example, the insulating film 9 is 1/2 to 2/3 of the passivation insulating film 5. A thin insulating film having a certain thickness is formed.

  Next, as shown in FIG. 2D, the insulating film 9 in the gate electrode forming region is removed so as to leave curved portions 9A formed on both sides of the insulating film 9 with the gate electrode forming region interposed therebetween. Here, the insulating film 9 in the gate electrode formation region is removed by photolithography, that is, exposure, development, and etching after resist application, and an opening 9B is formed in the insulating film 9. As a result, the end portion 9C on the gate electrode formation region side of the insulating film 9 covering the passivation insulating film 5, that is, the portion in contact with the gate electrode 2 to be formed later is curved, that is, gently rounded. It becomes. In this manner, an insulating film stacked structure 12 in which the passivation insulating film 5 and the insulating film 9 are stacked is formed between the gate electrode formation region and the source electrode 3. And in the insulating film laminated structure 12, the edge part of the insulating film 9 exposed to the gate electrode formation area side becomes a curved surface shape.

Next, as shown in FIG. 2E, a low dielectric constant film 6 (second insulating film) is formed on the entire surface. That is, the low dielectric constant film 6 is formed on the insulating film 9 covering the passivation insulating film 5. For example, as the low dielectric constant film 6, an insulating film having a dielectric constant lower than that of the passivation insulating film 5 and having a dielectric constant of about 2.0 to about 3.0 is formed.
Next, as shown in FIG. 2F, other than that, the low dielectric constant film 6 provided between the drain electrode 4 and the gate electrode formation region, here, on the drain electrode 4 side is left. The portion of the low dielectric constant film 6 is removed. Here, a position of about a half of the distance between the drain electrode 4 and the gate electrode formation region from the vicinity of the drain electrode 4 by photolithography, that is, by performing exposure, development, and etching after resist application. The remaining portions of the low dielectric constant film 6 are removed so that the low dielectric constant film 6 is left.

Next, as shown in FIG. 3A, an insulating film 8 (third insulating film) having a dielectric constant higher than that of the low dielectric constant film 6 is formed on the entire surface. That is, the insulating film 8 having a higher dielectric constant than that of the low dielectric constant film 6 is formed on the insulating film 9 covering the passivation insulating film 5. Here, an insulating film 8 made of the same material as the passivation insulating film 5 and the insulating film 9 covering the passivation insulating film 5 is formed on the entire surface. For example, as the insulating film 8, a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5 is formed.

  Next, as shown in FIG. 3B, the insulating film 8 provided between the drain electrode 4 and the gate electrode formation region, here, on the gate electrode formation region side of the low dielectric constant film 6 is left. Then, the other portion of the insulating film 8 is removed. Here, by a photolithography technique, that is, by performing exposure / development / etching after resist application, a portion in the vicinity of the gate electrode formation region of the low dielectric constant film 6 from a portion in contact with the gate electrode formation region side. The remaining part of the insulating film 8 is removed so that the insulating film 8 up to this is left with the same thickness as the low dielectric constant film 6. Here, the vicinity of the gate electrode formation region is a portion located closer to the drain electrode 4 than the end of the passivation insulating film 5 on the gate electrode formation region side. That is, the end of the insulating film 8 provided adjacent to the low dielectric constant film 6 on the gate electrode forming region side is positioned closer to the drain electrode 4 than the end of the passivation insulating film 5 on the gate electrode forming region side. To. Further, here, the etching is performed so that the end surface of the insulating film 8 on the gate electrode formation region side becomes vertical. That is, the end surface of the insulating film 8 on the gate electrode formation region side is vertical.

  In this manner, a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is formed on the insulating film 9 covering the passivation insulating film 5. The end of the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto on the side of the gate electrode forming region is positioned closer to the drain electrode 4 than the end of the passivation insulating film 5 on the side of forming the gate electrode. Will do. That is, the end of the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto on the gate electrode forming region side, that is, the end of the insulating film 8 on the gate electrode forming region side is the gate of the passivation insulating film 5. The position is shifted from the end on the electrode forming region side.

Next, as shown in FIG. 3C, an insulating film 10 (fourth insulating film) is formed so as to cover the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. That is, the insulating film 10 embeds a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. Here, the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is embedded with the insulating film 10 having a higher dielectric constant than that of the low dielectric constant film 6. Here, a passivation insulating film 5, an insulating film 9 covering the passivation insulating film 5, and an insulating film 10 made of the same material as the insulating film 8 adjacent to the low dielectric constant film 6 are formed on the entire surface. For example, a SiN film (for example, Si ₃ N ₄ film) having a dielectric constant of about 7.0 to 7.5 is formed as the insulating film 10. In this case, the insulating film 8 adjacent to the low dielectric constant film 6 is embedded with the insulating film 10 so as to cover the vertical end face of the insulating film 8 formed as described above on the gate electrode formation region side. In the insulating film 10, the curved surface portions 10A are formed on both sides of the gate electrode formation region. The insulating film 10 only needs to be able to form the curved surface portions 10A on both sides of the gate electrode formation region and does not need to be so thick. Therefore, the insulating film 10 is, for example, 1/2 to that of the passivation insulating film 5. A thin insulating film having a thickness of about 2/3 is formed.

  Next, as shown in FIG. 3D, one of the curved portions 10A (here, the drain electrode 4 side) formed on both sides of the gate electrode formation region of the insulating film 10 is included, and the low dielectric constant The insulating film 10 is removed so as to leave a portion covering the layer made of the film 6 and the insulating film 8 adjacent thereto. Here, the insulating film 10 other than the above-described part is removed by photolithography, that is, after resist application, by performing exposure, development, and etching. Thereby, the end 10B on the gate electrode formation region side of the insulating film 10 covering the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto, that is, the portion in contact with the gate electrode 2 to be formed later is curved. Shape, that is, a gently rounded shape. Further, here, as described above, the end portion on the gate electrode forming region side of the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is the end portion on the gate electrode forming region side of the passivation insulating film 5. It is located closer to the drain electrode 4 side. Therefore, the position of the curved end portion 10B on the gate electrode formation region side of the insulating film 10 covering the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is positioned at the insulating film 9 covering the passivation insulating film 5. The position is shifted to the drain electrode 4 side from the curved end portion 9C on the gate electrode formation region side.

Then, the step of forming and processing the above-described low dielectric constant film 6, the step of forming and processing the insulating film 8 adjacent to the above-described low dielectric constant film 6, the above-described low dielectric constant film 6 and the adjacent thereof. The process of forming and processing the insulating film 10 covering the layer made of the insulating film 8 is repeated several times (here, twice; a total of three times).
That is, the upper low dielectric constant film 6 (second insulating film) and the insulating film 10 (fourth insulating film) covering the layer made of the insulating film 8 (third insulating film) adjacent thereto are disposed on the upper low dielectric constant film 6 (second insulating film). A layer composed of the dielectric constant film 6 (sixth insulating film) and the insulating film 8 (seventh insulating film) adjacent thereto and an insulating film 10 (eighth insulating film) covering the layer are formed. Here, first, after the step of removing the insulating film 10, the upper low dielectric constant film 6 is formed on the insulating film 10 above the lower low dielectric constant film 6. Next, an insulating film 8 is formed on the gate electrode formation region side of the upper low dielectric constant film 6. Specifically, in other words, the upper insulating film 8 is arranged so that the end surface of the upper insulating film 8 on the gate electrode formation region side is closer to the drain electrode 4 side than the end surface of the lower insulating film 8 on the gate electrode formation region side. Form. The upper insulating film 8 is formed so that the end surface of the upper insulating film 8 on the gate electrode formation region side is shifted from the end surface of the lower insulating film 8 on the gate electrode formation region side. Next, the low dielectric constant film 6 and the insulating film 8 adjacent thereto are embedded with the insulating film 10. The insulating film 10 includes one of the curved portions formed on both sides of the gate electrode formation region of the insulating film 10 (here, the drain electrode 4 side), and covers the low dielectric constant film 6 and the insulating film 8 adjacent thereto. The insulating film 10 is removed so as to leave the exposed portion. In this case, the position of the curved end portion 10B on the gate electrode formation region side of the upper insulating film 10 is closer to the drain electrode 4 side than the curved end portion 10B on the gate electrode formation region side of the lower insulating film 10. The position is shifted. That is, the position of the curved end portion 10B on the gate electrode formation region side of the upper insulating film 10 is shifted from the position of the curved end portion 10B on the gate electrode formation region side of the lower insulating film 10. Become.

As a result, as shown in FIG. 3E, between the gate electrode formation region and the drain electrode 4, a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto, and the insulating film 10 covering the layer, A structure in which the layers are alternately stacked is formed.
Thus, between the gate electrode formation region and the drain electrode 4, a layer comprising the passivation insulating film 5, the insulating film 9, the low dielectric constant film 6 and the insulating film 8 adjacent thereto, the insulating film 10, the low dielectric constant The insulating film stack structure 11 is formed by laminating the dielectric film 10 and the insulating film 8 adjacent thereto, the insulating film 10, the low dielectric constant film 6 and the insulating film 8 layer adjacent thereto, and the insulating film 10. The In the insulating film laminated structure 11, the end portions of the insulating films 9 and 10 exposed to the gate electrode formation region side are all curved surfaces, and the end portion on the gate electrode formation region side becomes closer to the upper layer. Each layer is positioned on the drain electrode 4 side and is staggered and stacked.

Thereafter, the gate electrode 2 is formed in the gate electrode formation region, for example, by vapor deposition.
Therefore, according to the semiconductor device and the manufacturing method thereof according to the present embodiment, it is possible to reduce the capacitance generated by the insulating film existing between the gate electrode 2 and the drain electrode 4, that is, to reduce the capacitance. There is an advantage that the high frequency characteristics can be improved.
[Second Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to the second embodiment will be described with reference to FIG.

In the present embodiment, an insulating film laminated structure 11 including a low dielectric constant film 6 is provided between the gate electrode 2 and the source electrode 3 as shown in FIG. The difference is that it is provided.
That is, in the first embodiment described above (see FIG. 1), the insulating film laminated structure 11 including the low dielectric constant film 6 is provided only between the gate electrode 2 and the drain electrode 4, whereas this embodiment The difference is that the insulating film laminated structure 11 including the low dielectric constant film 6 is provided only between the gate electrode 2 and the source electrode 3.

  In particular, in this embodiment, instead of the passivation insulating film 103 and the interlayer insulating film 104 provided between the gate electrode 100 and the source electrode 101 in the conventional device structure (see FIG. 6), FIG. As shown in FIG. 4, the device has a device structure provided with the insulating film laminated structure 11. The insulating film laminated structure 11 includes a low dielectric constant film 6 having a dielectric constant lower than that of the passivation insulating film 5 and the interlayer insulating film 7. As a result, the capacitance generated by the insulating film can be reduced, that is, the capacitance can be reduced, which contributes to the improvement of the high frequency characteristics.

  In particular, in the present embodiment, the low dielectric constant film 6 is provided on the source electrode 3 side, and the insulating film having a dielectric constant higher than that of the low dielectric constant film 6 is adjacent to the gate electrode 2 side of the low dielectric constant film 6. By providing the film 8, the low dielectric constant film 6 is not provided in the vicinity of the gate electrode 2, and the reliability is improved. As described above, in this embodiment, the capacity is reduced and the high-frequency characteristics are improved while the reliability is not lowered.

In the present embodiment, the end portions of the insulating films 9 and 10 exposed on the gate electrode 2 side of the insulating film stacked structure 11 are all curved surfaces, and are further stacked in a staircase pattern. Therefore, the electric field concentration between the gate electrode and the source electrode can be relaxed and dispersed, and a high breakdown voltage can be realized.
Further, in the present embodiment, an insulating film laminated structure 12 is provided between the gate electrode 2 and the drain electrode 4, in which a passivation insulating film 5 and an insulating film 9 that covers the passivation insulating film 5 are laminated. Since the insulating film 9 covering the passivation insulating film 5 has a curved end at the gate electrode 2 side, electric field concentration at the end at the gate electrode 2 side can be reduced, and the withstand voltage is improved. Can be made.

Other details of the configuration are the same as those of the first embodiment described above, and thus the description thereof is omitted here.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 (A) to 4 (F).
First, as in the case of the first embodiment described above [see FIGS. 2A to 2E], each process up to the process of forming the low dielectric constant film 6 on the entire surface is performed.

  Next, as shown in FIG. 4A, the low dielectric constant film 6 provided between the source electrode 3 and the gate electrode formation region, here, on the source electrode 3 side is left. The portion of the low dielectric constant film 6 other than is removed. Here, a position that is about ½ of the distance between the source electrode 3 and the gate electrode formation region from the immediate vicinity of the source electrode 3 by photolithography, that is, by performing exposure, development, and etching after resist application. The remaining portions of the low dielectric constant film 6 are removed so that the low dielectric constant film 6 is left.

Next, as shown in FIG. 4B, an insulating film 8 (third insulating film) having a dielectric constant higher than that of the low dielectric constant film 6 is formed on the entire surface. That is, the insulating film 8 having a higher dielectric constant than that of the low dielectric constant film 6 is formed on the insulating film 9 covering the passivation insulating film 5. Here, an insulating film 8 made of the same material as the passivation insulating film 5 and the insulating film 9 covering the passivation insulating film 5 is formed on the entire surface. For example, as the insulating film 8, a SiN film (for example, a Si ₃ N ₄ film) having a dielectric constant of about 7.0 to about 7.5 is formed.

  Next, as shown in FIG. 4C, the insulating film 8 provided between the source electrode 3 and the gate electrode formation region, here, on the gate electrode formation region side of the low dielectric constant film 6 is left. Then, the other portion of the insulating film 8 is removed. Here, by a photolithography technique, that is, by performing exposure / development / etching after resist application, a portion in the vicinity of the gate electrode formation region of the low dielectric constant film 6 from a portion in contact with the gate electrode formation region side. The remaining part of the insulating film 8 is removed so that the insulating film 8 up to this is left with the same thickness as the low dielectric constant film 6. Here, the vicinity of the gate electrode formation region is a portion located closer to the source electrode 3 than the end of the passivation insulating film 5 on the gate electrode formation region side. That is, the end of the insulating film 8 provided adjacent to the low dielectric constant film 6 on the gate electrode formation region side is positioned closer to the source electrode 3 than the end of the passivation insulating film 5 on the gate electrode formation region side. To. Further, here, the etching is performed so that the end surface of the insulating film 8 on the gate electrode formation region side becomes vertical. That is, the end surface of the insulating film 8 on the gate electrode formation region side is vertical.

  In this manner, a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is formed on the insulating film 9 covering the passivation insulating film 5. The end portion on the gate electrode formation region side of the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is positioned closer to the source electrode 3 than the end portion on the gate electrode formation region side of the passivation insulating film 5. Will do. That is, the end of the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto on the gate electrode forming region side, that is, the end of the insulating film 8 on the gate electrode forming region side is the gate of the passivation insulating film 5. The position is shifted from the end on the electrode forming region side.

Next, as shown in FIG. 4D, an insulating film 10 (fourth insulating film) is formed so as to cover the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. That is, the insulating film 10 embeds a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. Here, the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is embedded with the insulating film 10 having a higher dielectric constant than that of the low dielectric constant film 6. Here, a passivation insulating film 5, an insulating film 9 covering the passivation insulating film 5, and an insulating film 10 made of the same material as the insulating film 8 adjacent to the low dielectric constant film 6 are formed on the entire surface. For example, a SiN film (for example, Si ₃ N ₄ film) having a dielectric constant of about 7.0 to 7.5 is formed as the insulating film 10. In this case, the insulating film 8 adjacent to the low dielectric constant film 6 is embedded with the insulating film 10 so as to cover the vertical end face of the insulating film 8 formed as described above on the gate electrode formation region side. In the insulating film 10, the curved surface portions 10A are formed on both sides of the gate electrode formation region. The insulating film 10 only needs to be able to form the curved surface portions 10A on both sides of the gate electrode formation region and does not need to be so thick. Therefore, the insulating film 10 is, for example, 1/2 to that of the passivation insulating film 5. A thin insulating film having a thickness of about 2/3 is formed.

  Next, as shown in FIG. 4E, one of the curved portions 10A (here, the source electrode 3 side) formed on both sides of the gate electrode formation region of the insulating film 10 is included and has a low dielectric constant. The insulating film 10 is removed so as to leave a portion covering the layer made of the film 6 and the insulating film 8 adjacent thereto. Here, the insulating film 10 other than the above-described part is removed by photolithography, that is, after resist application, by performing exposure, development, and etching. Thereby, the end 10B on the gate electrode formation region side of the insulating film 10 covering the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto, that is, the portion in contact with the gate electrode 2 to be formed later is curved. Shape, that is, a gently rounded shape. Further, here, as described above, the end portion on the gate electrode forming region side of the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is the end portion on the gate electrode forming region side of the passivation insulating film 5. It is located on the source electrode 3 side. Therefore, the position of the curved end portion 10B on the gate electrode formation region side of the insulating film 10 covering the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto is positioned at the insulating film 9 covering the passivation insulating film 5. The position is shifted to the source electrode 3 side from the curved end portion 9C on the gate electrode formation region side.

Then, the step of forming and processing the above-described low dielectric constant film 6, the step of forming and processing the insulating film 8 adjacent to the above-described low dielectric constant film 6, the above-described low dielectric constant film 6 and the adjacent thereof. The process of forming and processing the insulating film 10 covering the layer made of the insulating film 8 is repeated several times (here, twice; a total of three times).
That is, the upper low dielectric constant film 6 (second insulating film) and the insulating film 10 (fourth insulating film) covering the layer made of the insulating film 8 (third insulating film) adjacent thereto are disposed on the upper low dielectric constant film 6 (second insulating film). A layer composed of the dielectric constant film 6 (sixth insulating film) and the insulating film 8 (seventh insulating film) adjacent thereto and an insulating film 10 (eighth insulating film) covering the layer are formed. Here, first, after the step of removing the insulating film 10, the upper low dielectric constant film 6 is formed on the insulating film 10 above the lower low dielectric constant film 6. Next, an insulating film 8 is formed on the gate electrode formation region side of the upper low dielectric constant film 6. Specifically, in other words, the upper insulating film 8 is arranged such that the end surface of the upper insulating film 8 on the gate electrode formation region side is closer to the source electrode 3 side than the end surface of the lower insulating film 8 on the gate electrode formation region side. Form. The upper insulating film 8 is formed so that the end surface of the upper insulating film 8 on the gate electrode formation region side is shifted from the end surface of the lower insulating film 8 on the gate electrode formation region side. Next, the low dielectric constant film 6 and the insulating film 8 adjacent thereto are embedded with the insulating film 10. The insulating film 10 includes one of the curved portions formed on both sides of the gate electrode formation region of the insulating film 10 (here, the source electrode 3 side), and covers the low dielectric constant film 6 and the insulating film 8 adjacent thereto. The insulating film 10 is removed so as to leave the exposed portion. In this case, the position of the curved end portion 10B on the gate electrode formation region side of the upper insulating film 10 is closer to the source electrode 3 side than the curved end portion 10B on the gate electrode formation region side of the lower insulating film 10. The position is shifted. That is, the position of the curved end portion 10B on the gate electrode formation region side of the upper insulating film 10 is shifted from the position of the curved end portion 10B on the gate electrode formation region side of the lower insulating film 10. Become.

As a result, as shown in FIG. 4F, between the gate electrode formation region and the source electrode 3, a layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto, and the insulating film 10 covering the layer, A structure in which the layers are alternately stacked is formed.
Thus, between the gate electrode formation region and the source electrode 3, a layer composed of the passivation insulating film 5, the insulating film 9, the low dielectric constant film 6 and the insulating film 8 adjacent thereto, the insulating film 10, and the low dielectric constant. The insulating film stack structure 11 is formed by laminating the dielectric film 10 and the insulating film 8 adjacent thereto, the insulating film 10, the low dielectric constant film 6 and the insulating film 8 layer adjacent thereto, and the insulating film 10. The In the insulating film laminated structure 11, the end portions of the insulating films 9 and 10 exposed to the gate electrode formation region side are all curved surfaces, and the end portion on the gate electrode formation region side becomes closer to the upper layer. Each layer is positioned on the source electrode 3 side, and is shifted in a staircase pattern.

Thereafter, the gate electrode 2 is formed in the gate electrode formation region, for example, by vapor deposition.
The details of the other manufacturing methods are the same as those in the case of the first embodiment described above, and the description thereof is omitted here.
Therefore, according to the manufacturing method of the semiconductor device according to the present embodiment, it is possible to reduce the capacitance generated by the insulating film existing between the gate electrode 2 and the source electrode 3, that is, to reduce the capacitance. There is an advantage that high frequency characteristics can be improved.
[Third Embodiment]
Next, a semiconductor device and a manufacturing method thereof according to the third embodiment will be described with reference to FIG.

In the present embodiment, the insulating film laminated structure 11 including the low dielectric constant film 6 is provided between the gate electrode 2 and the source electrode 3 and between the gate electrode 2 and the drain as compared with the first and second embodiments described above. The difference is that it is provided between the electrodes 4.
That is, the semiconductor device according to the present embodiment is the same as that of the first embodiment described above in which the insulating film laminated structure 11 including the low dielectric constant film 6 is provided between the gate electrode 2 and the drain electrode 4 (see FIG. 1). ) And the above-described second embodiment in which the insulating film laminated structure 11 including the low dielectric constant film 6 is provided between the gate electrode 2 and the source electrode 3 (see FIG. 4F). Is.

Note that the details of the configuration are the same as those of the first and second embodiments described above, and thus the description thereof is omitted here.
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 5 (A) to 5 (F).
First, as in the case of the first embodiment described above [see FIGS. 2A to 2E], each process up to the process of forming the low dielectric constant film 6 on the entire surface is performed.

  Next, as shown in FIG. 5A, as in the first and second embodiments described above, between the drain electrode 4 and the gate electrode formation region, and between the source electrode 3 and the gate electrode formation region, The other portions of the low dielectric constant film 6 are removed so as to leave the low dielectric constant film 6 provided between them. Here, the low dielectric constant provided on the drain electrode 4 side between the drain electrode 4 and the gate electrode formation region and on the source electrode 3 side between the source electrode 3 and the gate electrode formation region, respectively. The remaining low dielectric constant film 6 is removed so as to leave the film 6.

Next, as shown in FIG. 5B, an insulating film 8 having a dielectric constant higher than that of the low dielectric constant film 6 is formed on the entire surface, as in the case of the first and second embodiments described above.
Next, as shown in FIG. 5C, as in the first and second embodiments described above, between the drain electrode 4 and the gate electrode formation region, and between the source electrode 3 and the gate electrode formation region. The remaining portions of the insulating film 8 are removed so as to leave the insulating film 8 provided between them. Here, the gate electrode formation region side of the low dielectric constant film 6 between the drain electrode 4 and the gate electrode formation region, and the gate electrode of the low dielectric constant film 6 between the source electrode 3 and the gate electrode formation region. The remaining portions of the insulating film 8 are removed so as to leave the insulating film 8 provided on each side of the formation region.

Next, as shown in FIG. 5D, as in the case of the first and second embodiments described above, the insulating film 10 covers the layer made of the low dielectric constant film 6 and the insulating film 8 adjacent thereto. Is deposited.
Next, as shown in FIG. 5E, both of the curved portions 10A (drains) formed on both sides of the gate electrode formation region of the insulating film 10 as in the case of the first and second embodiments described above. The insulating film 10 is removed so as to leave a portion that includes the low dielectric constant film 6 and the insulating film 8 adjacent to the low dielectric constant film 6 and the electrode 4 side and the source electrode 3 side).

  Then, as in the case of the first and second embodiments, the step of forming and processing the low dielectric constant film 6 and the step of forming and processing the insulating film 8 adjacent to the low dielectric constant film 6 are performed. The process and the process of forming and processing the insulating film 10 covering the layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto are repeated several times (here, twice; a total of three times). Thereby, as shown in FIG. 5F, the low dielectric constant film 6 and the gate electrode forming region and the source electrode 3 are respectively formed between the gate electrode forming region and the drain electrode 4 and between the gate electrode forming region and the source electrode 3. A structure is formed in which layers made of adjacent insulating films 8 and insulating films 10 covering the layers are alternately stacked.

  Thus, the passivation insulating film 5, the insulating film 9, the low dielectric constant film 6, and this are provided between the gate electrode forming region and the drain electrode 4 and between the gate electrode forming region and the source electrode 3, respectively. A layer made of an insulating film 8 adjacent to the insulating film 10, an insulating film 10, a low dielectric constant film 6 and a layer made of the insulating film 8 adjacent thereto, an insulating film 10, the low dielectric constant film 6 and an insulating film 8 adjacent thereto. An insulating film laminated structure 11 in which layers and insulating films 10 are laminated is formed. In the insulating film laminated structure 11, the end portions of the insulating films 9 and 10 exposed to the gate electrode formation region side are all curved surfaces, and the end portion on the gate electrode formation region side becomes closer to the upper layer. The layers are positioned on the drain electrode 4 side or the source electrode 3 side, and the layers are stacked in a staircase pattern.

Thereafter, the gate electrode 2 is formed in the gate electrode formation region, for example, by vapor deposition.
The details of the other manufacturing methods are the same as those in the first and second embodiments described above, and therefore the description thereof is omitted here.
Therefore, according to the manufacturing method of the semiconductor device according to the present embodiment, the insulating film existing between the gate electrode 2 and the drain electrode 4 and the gate electrode, as in the first and second embodiments described above. There is an advantage that a reduction in capacitance caused by an insulating film existing between the source electrode 3 and the source electrode 3, that is, a reduction in capacitance can be realized, and higher frequency characteristics can be improved.
[Others]
In addition, this invention is not limited to the structure described in each embodiment mentioned above, A various deformation | transformation is possible in the range which does not deviate from the meaning of this invention.

For example, as described in each of the above-described embodiments, the insulating film laminated structure 11 including the low dielectric constant film 6 includes the source electrode 3 and the gate electrode 2, and the drain electrode 4 and the gate electrode 2. May be provided at least at one of the positions.
Further, for example, in each of the above-described embodiments, the insulating film laminated structure 11 including the low dielectric constant film 6 is described as an example. However, the present invention is not limited to this, and the gap between the source electrode and the gate electrode is described. A low dielectric constant film (second insulating film) having a dielectric constant lower than that of the passivation insulating film is provided above at least one of the passivation insulating film (first insulating film) between the drain electrode and the gate electrode. Anything is fine.

For example, in the conventional configuration (see FIG. 6), the low dielectric constant film 6 is provided on at least one passivation insulating film between the gate electrode and the drain electrode and between the gate electrode and the source electrode. But it ’s okay.
Further, for example, in the conventional configuration (see FIG. 6), the low dielectric constant film 6 may be provided at a position away from the gate electrode on the passivation insulating film. That is, the low dielectric constant film 6 may be provided on the drain electrode side on the passivation insulating film, that is, on the drain electrode side between the gate electrode and the drain electrode. Alternatively, a low dielectric constant film may be provided on the source electrode side on the passivation insulating film, that is, on the source electrode side between the gate electrode and the source electrode.

Further, for example, the low dielectric constant film 6 may be provided only in one layer, or a plurality of layers may be laminated.
As described above, the insulating film 8 adjacent to the low dielectric constant film 6, the insulating film 9 covering the passivation insulating film 5, the low dielectric constant film 6, and the insulating film 8 adjacent thereto are provided in each of the above-described embodiments. The insulating film 10 may not be provided.

Further, for example, in the insulating film laminated structure 11 including the low dielectric constant film 6 in each of the above-described embodiments, the insulating film 9 covering the passivation insulating film 5, the insulating film covering the low dielectric constant film 6 and the insulating film 8 adjacent thereto. The film 10 may not be provided. Moreover, it is not necessary to laminate | stack in step shape. It is also possible to provide only one layer composed of the low dielectric constant film 6 and the insulating film 8 adjacent thereto.
In each of the above-described embodiments, the opening 5A (gate lower opening) [see FIG. 2B] is provided in the passivation insulating film 5. However, the present invention is not limited to this, and the passivation insulating film 5 is not limited thereto. May not be provided with an opening. In this case, the gate electrode 2 is formed on the passivation insulating film 5. That is, the passivation insulating film 5 is not only on the surface of the semiconductor region 1 between the gate electrode 2 and the source electrode 3 and between the gate electrode 2 and the drain electrode 4 but also between the semiconductor region 1 and the gate electrode 2. Will also intervene.

DESCRIPTION OF SYMBOLS 1 Semiconductor region 2 Gate electrode 3 Source electrode 4 Drain electrode 5 Passivation insulating film 6 Low dielectric constant film 7 Interlayer insulating film 8, 9, 10 Insulating film 9A, 10A Curved part 9B Opening part 9C, 10B Curved end part 11 Insulation Film laminated structure 12 Insulating film laminated structure

Claims (11)

A semiconductor region;
A gate electrode formed above the semiconductor region;
A source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode,
A first insulating film covering a surface of the semiconductor region;
Provided above the first insulating film between at least one of the source electrode and the gate electrode and between the drain electrode and the gate electrode, and has a dielectric constant lower than that of the first insulating film. A second insulating film;
The second insulating film is provided at a position away from the gate electrode,
A third insulating film provided on the gate electrode side of the second insulating film and having a dielectric constant higher than that of the second insulating film;
A fourth insulating film provided above the second insulating film and having a lower dielectric constant than the first insulating film;
A fifth insulating film provided on the gate electrode side of the fourth insulating film and having a higher dielectric constant than the fourth insulating film;
An end of the fifth insulating film on the gate electrode side is shifted from an end of the third insulating film on the gate electrode side. A semiconductor region;
A gate electrode formed above the semiconductor region;
A source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode,
A first insulating film covering a surface of the semiconductor region;
Provided above the first insulating film between at least one of the source electrode and the gate electrode and between the drain electrode and the gate electrode, and has a dielectric constant lower than that of the first insulating film. A second insulating film;
The second insulating film is provided at a position away from the gate electrode,
A third insulating film provided on the gate electrode side of the second insulating film and having a dielectric constant higher than that of the second insulating film;
And a sixth insulating film that covers the second insulating film and the third insulating film, has a curved end on the gate electrode side, and has a dielectric constant higher than that of the second insulating film. A semiconductor device.   The end of the third insulating film on the gate electrode side is shifted from the end of the first insulating film on the gate electrode side. The semiconductor device described. Covering the first insulating film, the end on the gate electrode side is a curved surface, and includes a seventh insulating film having a higher dielectric constant than the second insulating film,
The end of the sixth insulating film on the gate electrode side is shifted from the end of the seventh insulating film on the gate electrode side. The semiconductor device described. A sixth insulating film that covers the second insulating film and the third insulating film, has a curved end on the gate electrode side, and has a higher dielectric constant than the second insulating film;
An eighth insulating film that covers the fourth insulating film and the fifth insulating film, has an end on the gate electrode side that is curved, and has a higher dielectric constant than the fourth insulating film;
The end of the eighth insulating film on the gate electrode side is shifted from the end of the sixth insulating film on the gate electrode side. The semiconductor device described. A semiconductor region;
A gate electrode formed above the semiconductor region;
A source electrode and a drain electrode formed above the semiconductor region and provided on both sides of the gate electrode,
A first insulating film covering a surface of the semiconductor region;
Provided above the first insulating film between at least one of the source electrode and the gate electrode and between the drain electrode and the gate electrode, and has a dielectric constant lower than that of the first insulating film. A second insulating film;
And a seventh insulating film covering a side surface of the first insulating film on the gate electrode side, an end portion on the gate electrode side being curved, and having a dielectric constant higher than that of the second insulating film. A semiconductor device. The semiconductor device according to claim 6, wherein the second insulating film is located on the seventh insulating film. The semiconductor device according to claim 6, wherein a curved surface of an end portion of the seventh insulating film on the gate electrode side has a convex portion protruding toward the gate electrode side and is in contact with the gate electrode. Forming a source electrode and a drain electrode on both sides across the gate electrode formation region above the semiconductor region; and
Forming a first insulating film covering a surface of the semiconductor region;
Dielectric constant lower than that of the first insulating film between the source electrode and the gate electrode forming region and above the first insulating film between at least one of the drain electrode and the gate electrode forming region. Forming a second insulating film having:
Forming a third insulating film having a dielectric constant higher than that of the second insulating film on the gate electrode forming region side of the second insulating film;
Burying the second insulating film and the third insulating film with a fourth insulating film;
Including at least one of curved surface portions formed on both sides of the gate electrode formation region of the fourth insulating film, and leaving a portion covering the second insulating film and the third insulating film, And a step of removing the fourth insulating film. Removing the first insulating film in the gate electrode formation region;
Burying the first insulating film with a fifth insulating film;
Removing the fifth insulating film in the gate electrode forming region so as to leave curved portions formed on both sides of the gate electrode forming region of the fifth insulating film,
In the step of forming the third insulating film, the end surface of the third insulating film on the gate electrode formation region side is shifted from the end surface of the first insulating film on the gate electrode formation region side. The method of manufacturing a semiconductor device according to claim 9 , wherein the third insulating film is formed. Forming a sixth insulating film having a lower dielectric constant than the first insulating film on the fourth insulating film above the second insulating film after the step of removing the fourth insulating film;
Forming a seventh insulating film having a dielectric constant higher than that of the sixth insulating film on the side of the gate electrode forming region of the sixth insulating film;
Burying the sixth insulating film and the seventh insulating film with an eighth insulating film;
Including at least one of curved surface portions formed on both sides of the gate electrode formation region of the eighth insulating film, and leaving a portion covering the sixth insulating film and the seventh insulating film, And a step of removing the eighth insulating film,
In the step of forming the seventh insulating film, the end surface of the seventh insulating film on the gate electrode formation region side is shifted from the end surface of the third insulating film on the gate electrode formation region side. The method of manufacturing a semiconductor device according to claim 9 , wherein the seventh insulating film is formed.

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