JP5723082B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device including a high electron mobility transistor (HEMT) using a compound semiconductor, a manufacturing method thereof, and the like.

  A monolithic microwave integrated circuit (MMIC) using a compound semiconductor has excellent performance as a device for a high-power and high-frequency amplifier. In the conventional HEMT used for MMIC or the like, as shown in FIG. 24, the compound semiconductor region 102, the source electrode 104, the drain electrode 105, and the gate electrode 106 constituting the transistor are made of silicon for the purpose of ensuring moisture resistance. The nitride films 110 and 111 are covered. This is because a high electric field is applied to the periphery of the gate electrode 106, so that the presence of moisture in the vicinity tends to cause corrosion, and the progress of such corrosion reduces the reliability of the compound semiconductor device. . However, in this conventional HEMT, since the dielectric constant of the silicon nitride film 111 is high, it is difficult to obtain sufficient high frequency characteristics.

  Therefore, a structure using a low dielectric constant film (Low-k film) instead of the inorganic insulating film has been proposed. For example, a structure in which a compound semiconductor layer, a gate electrode, and the like are covered with a thin insulating film and a thick single low dielectric constant film is formed thereon has been proposed. However, in general, a low dielectric constant film has a property that moisture is more easily contained as the dielectric constant is lower. That is, in many low dielectric constant films, a space is formed in the molecular structure or skeleton structure in order to reduce the dielectric constant, and as a result, the lower the dielectric constant, the lower the moisture resistance. For this reason, in this conventional structure, when it is going to acquire sufficient high frequency characteristics, moisture resistance and reliability will not be satisfied, and when it is going to acquire sufficient humidity resistance and reliability, high frequency characteristics will not be satisfied.

  In addition, a technique in which the interlayer insulating film is composed of a plurality of low dielectric constant films has been proposed. However, even when this technology is applied to a compound semiconductor device, it is impossible to achieve both high frequency characteristics and moisture resistance (reliability).

  Thus, it is difficult for conventional compound semiconductor devices and the like to achieve both moisture resistance (reliability) and high frequency characteristics. For this reason, in a compound semiconductor device used for an apparatus used outdoors such as a base station for mobile phone communication, a low dielectric constant film cannot be simply used as a substitute for an inorganic insulating film.

JP 2007-158256 A JP 2000-12690 A

  An object of the present invention is to provide a semiconductor device that can achieve both moisture resistance (reliability) and high-frequency characteristics, and a method for manufacturing the same.

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

In the semiconductor device, the compound semiconductor region, the source electrode and the drain electrode formed on the compound semiconductor region, and the first silicon nitride film are formed at a position between the source electrode and the drain electrode. A gate electrode formed on the compound semiconductor region is provided so as to be in contact with the compound semiconductor region through the opening or in contact with the first silicon nitride film . Further, in a region between the source electrode and the drain electrode, a low dielectric constant film that covers the gate electrode and a first silicon nitride film are formed on the first dielectric film and covers the upper surface and side surfaces of the low dielectric constant film . 2 and a low dielectric constant moisture-resistant film formed on the second silicon nitride film . The relative dielectric constant of the low dielectric constant film is lower than any of the relative dielectric constants of the first silicon nitride film, the second silicon nitride film, and the moisture resistant film. The low dielectric constant film is separated from the source electrode and the drain electrode. There is no cavity between the first silicon nitride film and the compound semiconductor region. The first silicon nitride film covers the compound semiconductor region under the low dielectric constant film in a region between the gate electrode and the drain electrode in plan view, and is continuous with the second silicon nitride film. To do .

In the method of manufacturing a semiconductor device, a compound semiconductor region, forms the shape of the source over the scan electrode and the drain electrode, wherein the compound semiconductor region, forming a first silicon nitride film covering the source electrode and the drain electrode, wherein In contact with the compound semiconductor region through an opening formed in the first silicon nitride film at a position between the source electrode and the drain electrode, or in contact with the first silicon nitride film, the compound forming a gate electrode on the semiconductor region, in a region between the source electrode and the drain electrode, it forms the shape of the low dielectric constant film that covers the front Symbol gate electrode, on the first silicon nitride film, A second silicon nitride film is formed to cover the top and side surfaces of the low dielectric constant film , and a low dielectric constant moisture-resistant film is formed on the second silicon nitride film . The dielectric constant of the low dielectric constant film is lower than any of the dielectric constants of the first silicon nitride film, the second silicon nitride film, and the moisture resistant film, and the low dielectric constant film is the source of the source. The first silicon nitride film is spaced apart from the electrode and the drain electrode, and there is no cavity between the first silicon nitride film and the compound semiconductor region, and the first silicon nitride film has the gate electrode and the drain electrode in plan view. In the region between the first and second layers, the compound semiconductor region is covered under the low dielectric constant film and is continuous with the second silicon nitride film .

  According to the semiconductor device or the like, since the low dielectric constant film, the inorganic insulating film, and the moisture resistant film are appropriately disposed, both moisture resistance (reliability) and high frequency characteristics can be achieved.

(First embodiment)
First, the first embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the first embodiment.

  In the first embodiment, as shown in FIG. 1, for example, a compound semiconductor region 2 is formed on a semi-insulating SiC substrate 1. The compound semiconductor region 2 includes a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c, and a surface layer 2d that are sequentially stacked. The buffer layer 2a and the electron transit layer 2b are, for example, GaN layers (i-GaN layers) that are not intentionally doped with impurities, and their total thickness is about 3 μm. Buffer layer 2a prevents the propagation of lattice defects existing on the surface of SiC substrate 1 to electron transit layer 2b. The electron supply layer 2c is, for example, an n-type AlGaN layer (n-AlGaN layer) and has a thickness of about 10 nm. The surface layer 2d is, for example, an n-type GaN layer (n-GaN layer) and has a thickness of 10 nm or less.

  An element isolation region 3 that defines an active region is formed around the compound semiconductor region 2. Two openings that expose the electron supply layer 2c are formed in the surface layer 2d, and an ohmic electrode is formed as the source electrode 4 or the drain electrode 5 in each of the openings. Further, a silicon nitride film 10 (inorganic insulating film) that covers the surface layer 2d, the source electrode 4, and the drain electrode 5 is formed. The thickness of the silicon nitride film 10 is, for example, about 50 nm. In the silicon nitride film 10, an opening 10 a is formed at a position approximately in the middle between the source electrode 4 and the drain electrode 5. A gate electrode 6 in contact with the surface layer 2d through the opening 10a is formed on the silicon nitride film 10.

  A low dielectric constant film 11 is formed on the silicon nitride film 10 to cover the gate electrode 6 at a position away from the source electrode 4 and the drain electrode 5. The low dielectric constant film 11 is, for example, a porous film, and the relative dielectric constant of the low dielectric constant film 11 is, for example, about 2.2. The thickness of the low dielectric constant film 11 is, for example, about 1 μm.

  Furthermore, a silicon nitride film 12 (inorganic insulating film) covering the upper surface and side surfaces of the low dielectric constant film 11 is formed on the silicon nitride film 10. The thickness of the silicon nitride film 12 is, for example, about 100 nm. The relative dielectric constant of the silicon nitride film 12 is about 7, for example. A low dielectric constant film 13 (moisture resistant film) is formed on the silicon nitride film 12. The low dielectric constant film 13 is, for example, a non-porous film containing an organic substance, and the relative dielectric constant of the low dielectric constant film 13 is higher than that of the low dielectric constant film 11 and is, for example, about 3.0. Further, the moisture resistance of the low dielectric constant film 13 is higher than that of the low dielectric constant film 11. The low dielectric constant film 13 is flattened, and the thickness thereof is about 2 μm at the thickest part.

  An opening reaching the source electrode 4 and an opening reaching the drain electrode are formed in the low dielectric constant film 13, the silicon nitride film 12, and the silicon nitride film 10. Wirings 14 and 15 connected to the source electrode 4 and the drain electrode 5 through these openings are formed on the low dielectric constant film 13. The wirings 14 and 15 are Au wirings, for example.

  In the first embodiment, since the low dielectric constant film 11 having a particularly low relative dielectric constant is provided around the gate electrode 6, good high frequency characteristics can be obtained by reducing the parasitic capacitance. For example, the parasitic capacitance near the gate electrode in the first embodiment is about 10% lower than that in the conventional HEMT shown in FIG. In addition, although the low dielectric constant film 11 has low moisture resistance, the upper surface and side surfaces of the low dielectric constant film 11 are covered with a silicon nitride film 12 that is extremely excellent in moisture resistance, and is further moisture resistant than the low dielectric constant film 11. Since it is covered with the low dielectric constant film 13 having high properties, it is possible to ensure high moisture resistance.

  In general, the low dielectric constant film has a property of low adhesion to the Au wiring, and in this embodiment as well, the wirings 14 and 15 and the low dielectric constant film 13 are shown by the arrow 50 in FIG. Moisture may penetrate between the two. However, in this embodiment, since the low dielectric constant film 11 and the gate electrode 6 are covered with the silicon nitride films 10 and 12, it is possible to suppress moisture from reaching the gate electrode 6.

  In consideration of ensuring water resistance, it is conceivable to use the thick silicon nitride film 12 instead of the low dielectric constant film 13, but in this case, good high frequency characteristics cannot be obtained. Further, it is difficult to ensure the flatness of the surface of the silicon nitride film 12, and the shape of the wirings 14 and 15 is likely to be difficult to control.

  Next, a method for manufacturing the GaN-based HEMT according to the first embodiment will be described. 2A to 2L are cross-sectional views showing a method of manufacturing the GaN-based HEMT according to the first embodiment in the order of steps.

  First, as shown in FIG. 2A, a buffer layer 2a, an electron transit layer 2b, an electron supply layer 2c are formed on a semi-insulating SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). And the surface layer 2d is epitaxially grown in this order. The buffer layer 2a, the electron transit layer 2b, the electron supply layer 2c, and the surface layer 2d are included in the compound semiconductor region 2.

  Next, as shown in FIG. 2B, by selectively implanting Ar toward the compound semiconductor region 2, an element isolation region 3 that defines an active region is formed in the compound semiconductor region 2 and the surface layer portion of the SiC substrate 1. .

Thereafter, a resist pattern is formed on the compound semiconductor region 2 to open a region where the source electrode is to be formed and a region where the drain electrode is to be formed. Subsequently, by using the resist pattern as a mask, dry etching using an inert gas and a chlorine-based gas such as Cl ₂ gas is performed on the surface layer 2d. Openings are formed. Regarding the depth of the opening, a part of the surface layer 2d may be left, or a part of the electron supply layer 2c may be removed. That is, the depth of the opening does not need to match the thickness of the surface layer 2d.

  Thereafter, as shown in FIG. 2C, the source electrode 4 is formed in one opening, and the drain electrode 5 is formed in the other opening. In forming the source electrode 4 and the drain electrode 5, for example, first, a Ti layer is formed by an evaporation method, and an Al layer is formed thereon by an evaporation method. The thickness of the Ti layer is about 20 nm, and the thickness of the Al layer is about 200 nm. Then, the resist pattern used for forming the opening is removed. That is, in forming the source electrode 4 and the drain electrode 5, for example, vapor deposition and lift-off techniques are used. Thereafter, a heat treatment at about 550 ° C. is performed to make ohmic contact between the electron supply layer 2 c and the source electrode 4 and the drain electrode 5.

  Next, as shown in FIG. 2D, a silicon nitride film 10 covering the source electrode 4 and the drain electrode 5 is formed on the entire surface of the compound semiconductor region 2 by a plasma chemical vapor deposition (CVD) method.

Thereafter, as shown in FIG. 2E, a resist pattern 21 having an opening 21a aligned with a region where the opening 10a is to be formed is formed on the silicon nitride film 10. Then, an opening 10a is formed in the silicon nitride film 10 by performing dry etching using the resist pattern 21 as a mask. In this dry etching, for example, SF ₆ gas is used. Subsequently, the resist pattern 21 is removed.

  Thereafter, as shown in FIG. 2F, the lower resist pattern 22 having an opening 22a aligned with the region where the gate electrode 6 is to be formed and the upper resist pattern 23 having an opening 23a narrower than the opening 22a are silicon nitrided. It is formed on the film 10.

  In forming the lower layer resist pattern 22 and the upper layer resist pattern 23, first, an alkali-soluble resin (trade name PMGI: manufactured by US Microchem Co., Ltd.) is applied on the silicon nitride film 10 by, for example, spin coating, and heat treatment is performed. By performing, a resist film is formed. Furthermore, a photosensitive resist agent (trade name PFI32-A8: manufactured by Sumitomo Chemical Co., Ltd.) is applied by, for example, a spin coat method, and heat treatment is performed to form a resist film. Next, an opening 23a having a width of about 0.8 μm is formed in the upper resist film by ultraviolet exposure. As a result, an upper resist pattern 23 having an opening 23a is obtained. Thereafter, using the upper resist pattern 23 as a mask, the lower resist film is wet etched using an alkali developer. As a result, the lower resist pattern 22 having the opening 22a is obtained. By these treatments, as shown in FIG. 2F, a multi-layer resist having a cage structure is obtained.

  After the formation of the lower layer resist pattern 22 and the upper layer resist pattern 23, as shown in FIG. 2F, the gate electrode 6 is formed in the opening 22a. In forming the gate electrode 6, for example, a Ni layer is formed by a vapor deposition method, and an Au layer is formed thereon by a vapor deposition method. The thickness of the Ni layer is about 10 nm, and the thickness of the Au layer is about 300 nm.

  Next, as shown in FIG. 2G, the resist patterns 22 and 23 are removed using a heated organic solvent. That is, even in the formation of the gate electrode 6, for example, vapor deposition and lift-off techniques are used.

  Thereafter, as shown in FIG. 2H, a low dielectric constant film 11 is formed on the silicon nitride film 10. In forming the low dielectric constant film 11, first, a coating liquid for the low dielectric constant film 11 (NCS (Nano-Crystalling Silica) manufactured by Catalytic Chemical Industry) is applied to the silicon nitride film 10 by, for example, spin coating at 2000 rpm. Apply at a rotational speed of. Next, baking is performed at 250 ° C. for 1 minute. By repeating the coating and baking processes about 8 times, the low dielectric constant film 11 having a thickness of about 1 μm is obtained.

After the low dielectric constant film 11 is formed, for example, a heat curing process at 350 ° C. is performed for 15 minutes while irradiating excimer light having a wavelength of 222 nm. Thereafter, as shown in FIG. 2I, a resist pattern 24 that covers the portion of the low dielectric constant film 11 that remains is formed on the low dielectric constant film 11 by, for example, an ultraviolet exposure method. Next, by performing dry etching using SF ₆ gas and CHF ₃ gas using the resist pattern 24 as a mask, the low dielectric constant film 11 is spaced from the source electrode 4 and the drain electrode 5 in plan view. To remain. Then, the resist pattern 24 is removed.

  Next, as shown in FIG. 2J, a silicon nitride film 12 (thickness: about 100 nm) covering the upper surface and side surfaces of the low dielectric constant film 11 is formed on the silicon nitride film 10 by plasma CVD.

  Thereafter, as shown in FIG. 2K, a low dielectric constant film 13 is formed on the silicon nitride film 12. In forming the low dielectric constant film 13, first, a coating liquid for the low dielectric constant film 13 (PTS-E manufactured by Honeywell) is applied onto the silicon nitride film 12 by, for example, spin coating at a rotational speed of 1500 rpm. To do. Next, heat curing is performed at 230 ° C. for 60 minutes.

  After the formation of the low dielectric constant film 13, as shown in FIG. 2L, an opening reaching the source electrode 4 and an opening reaching the drain electrode 5 are formed in the low dielectric constant film 13, the silicon nitride film 12, and the silicon nitride film 10. For example, it is formed by an ultraviolet exposure method and a dry etching method. Then, a wiring 14 connected to the source electrode 4 and a wiring 15 connected to the drain electrode 5 are formed on the low dielectric constant film 13. In forming the wirings 14 and 15, for example, Au plating is performed. In this way, a GaN-based HEMT (semiconductor device) is completed.

(Second Embodiment)
Next, a second embodiment will be described. FIG. 3 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the second embodiment.

  In the second embodiment, as shown in FIG. 3, the distance between the gate electrode 6 and the drain electrode 5 is larger than that in the first embodiment. That is, the distance between the gate electrode 6 and the drain electrode 5 is larger than the distance between the gate electrode 6 and the source electrode 4. That is, an offset gate structure is employed. Further, the wiring 14 extends above the gate electrode 6, and the wiring 14 and the gate electrode 6 overlap each other in plan view. That is, a source wall structure is adopted. Then, the low dielectric constant film 11 is formed wider on the drain electrode 5 side by the extent that the distance between the gate electrode 6 and the drain electrode 5 is increased. Other configurations are the same as those of the first embodiment.

  According to the second embodiment, the effects of the source wall structure and the offset gate structure can be obtained together with the same effects as those of the first embodiment. That is, the parasitic capacitance between the source and the drain can be reduced, and the gate-drain breakdown voltage can be improved. Therefore, it is particularly useful for a compound semiconductor device that requires high output.

  In order to reduce the parasitic capacitance between the gate and the drain, it is effective to bring the wiring 14 connected to the source electrode 4 closer to the gate electrode 6. However, when the wiring 14 is brought closer to the gate electrode 6, the wiring 14 gets closer to the drain electrode 5 and the parasitic capacitance between the source and the drain increases. On the other hand, in a compound semiconductor device that requires high output, it is preferable that not only the parasitic capacitance between the gate and the drain but also the parasitic capacitance between the source and the drain is low. In the present embodiment, not only the source wall structure but also the offset gate structure is employed, and the low dielectric constant film 11 is widely formed on the drain electrode 5 side, so that the parasitic capacitance between the source and the drain is increased. Is suppressed.

  Even if the source wall structure is not adopted in the second embodiment, the effects of the first embodiment and the offset gate structure can be obtained. Further, in the structure in which the source wall structure is adopted with respect to the first embodiment, the effects of the first embodiment and the source wall structure can be obtained. Therefore, only one of the source wall structure and the offset gate structure may be employed.

  Next, a method for manufacturing the GaN-based HEMT according to the second embodiment will be described. 4A to 4D are cross-sectional views showing a method of manufacturing the GaN-based HEMT according to the second embodiment in the order of steps.

  First, similarly to the first embodiment, the processes up to the formation of the silicon nitride film 10 are performed (FIG. 2D). However, the distance between the source electrode 4 and the drain electrode 5 is made larger than that in the first embodiment. Next, as shown in FIG. 4A, a resist pattern 21 having an opening 21 a that matches the region where the opening 10 a is to be formed is formed on the silicon nitride film 10. At this time, the position of the opening 21 a is set closer to the source electrode 4 than to the drain electrode 5. Then, an opening 10a is formed in the silicon nitride film 10 by performing dry etching using the resist pattern 21 as a mask. Subsequently, the resist pattern 21 is removed.

  Thereafter, in the same manner as in the first embodiment, a gate electrode 6 is formed as shown in FIG. 4B. Further, a low dielectric constant film 11 is formed on the silicon nitride film 10 and, for example, a heat curing process at 350 ° C. is performed for 15 minutes while irradiating excimer light having a wavelength of 222 nm. Subsequently, a resist pattern 24 is formed on the low dielectric constant film 11 to cover a portion where the low dielectric constant film 11 remains. At this time, the distance from the source electrode 4 and the distance from the drain electrode 5 of the resist pattern 24 in plan view are approximately equal to each other. That is, with respect to the resist pattern 24, the portion between the drain electrode 5 and the gate electrode 6 is made wider than the portion between the source electrode 4 and the gate electrode 6. Next, by performing dry etching using the resist pattern 24 as a mask, the low dielectric constant film 11 is left at a position separated from the source electrode 4 and the drain electrode 5 in plan view. Then, the resist pattern 24 is removed.

  Next, as in the first embodiment, as shown in FIG. 4C, a silicon nitride film 12 covering the upper surface and side surfaces of the low dielectric constant film 11 is formed on the silicon nitride film 10 by plasma CVD.

  Thereafter, the same processing as in the first embodiment is performed to complete a GaN-based HEMT (semiconductor device) as shown in FIG. 4D. However, in forming the wiring 14, the wiring 14 is extended to above the gate electrode 6.

(Third embodiment)
Next, a third embodiment will be described. FIG. 5 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the third embodiment.

  In the third embodiment, as shown in FIG. 5, the low dielectric constant film 11 is provided only in a region between the gate electrode 6 and the drain electrode 5 without covering the gate electrode 6. The gate electrode 6 is directly covered with the silicon nitride film 12. Other configurations are the same as those of the second embodiment.

  In the source wall structure as in the second embodiment, the portions of the low dielectric constant films 11 and 13 above the gate electrode 6 and the wiring 14 change the lines of electric force to reduce the parasitic capacitance. This means that if the total dielectric constant of the portions of the low dielectric constant films 11 and 13 above the gate electrode 6 is too low, the electric lines of force cannot be effectively changed, and the effect of the source wall structure ( (Reduction of parasitic capacitance between the gate and the drain) may not be sufficiently obtained. On the other hand, in this embodiment, since the low dielectric constant film 11 having a particularly low relative dielectric constant does not exist between the gate electrode 6 and the wiring 14, the effect of the source wall structure can be reliably obtained. That is, the parasitic capacitance between the gate and the drain is reduced. Moreover, even if it is narrower than the second embodiment, the low dielectric constant film 11 can contribute to the reduction of the parasitic capacitance between the source and the drain.

  As shown in FIG. 23, in order to further reduce the parasitic capacitance between the source and the drain, the low dielectric constant film 11 may be extended to an upper wiring layer.

  Next, a method for manufacturing a GaN-based HEMT according to the third embodiment will be described. 6A to 6C are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to the third embodiment in the order of steps.

  First, processing up to the formation of the gate electrode 6 is performed as in the second embodiment (FIG. 4B). Next, a low dielectric constant film 11 is formed on the silicon nitride film 10 and, for example, a thermal curing process at 350 ° C. is performed for 15 minutes while irradiating excimer light having a wavelength of 222 nm. As shown in FIG. A resist pattern 24 is formed on the low dielectric constant film 11 so as to cover a portion where the dielectric constant film 11 remains. At this time, the resist pattern 24 is formed only between the gate electrode 6 and the drain electrode 5 in plan view. Thereafter, dry etching is performed using the resist pattern 24 as a mask to leave the low dielectric constant film 11 between the gate electrode 6 and the drain electrode 5 in plan view. Then, the resist pattern 24 is removed.

  Next, as in the second embodiment, as shown in FIG. 6B, a silicon nitride film 12 covering the upper surface and side surfaces of the low dielectric constant film 11 is formed on the silicon nitride film 10 by plasma CVD.

  Thereafter, the same processing as in the second embodiment is performed to complete a GaN-based HEMT (semiconductor device) as shown in FIG. 6C.

(Fourth embodiment)
Next, a fourth embodiment will be described. FIG. 7 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the fourth embodiment. While the first embodiment is a Schottky gate type transistor, this embodiment is a MIS (metal insulator semiconductor) gate type transistor. That is, as shown in FIG. 7, the opening 10 a is not formed in the silicon nitride film 10, and the gate electrode 6 is not in contact with the compound semiconductor region 2. Other configurations are the same as those of the first embodiment.

  The present invention can also be applied to such a MIS gate type transistor, and the same effect as in the first embodiment can be obtained.

  Next, a method for manufacturing a GaN-based HEMT according to the fourth embodiment will be described. 8A to 8B are cross-sectional views showing a method of manufacturing a GaN-based HEMT according to the fourth embodiment in the order of steps.

  First, similarly to the first embodiment, the processes up to the formation of the silicon nitride film 10 are performed (FIG. 2D). Next, without forming the opening 10a, as shown in FIG. 8A, the lower resist pattern 22 having the opening 22a that matches the region where the gate electrode 6 is to be formed and the opening 23a narrower than the opening 22a are formed. The provided upper resist pattern 23 is formed on the silicon nitride film 10. Then, the gate electrode 6 is formed in the opening 22a. Thereafter, the resist patterns 22 and 23 are removed.

  Subsequently, by performing the same processing as in the first embodiment, as shown in FIG. 8B, a GaN-based HEMT (semiconductor device) is completed.

(Fifth embodiment)
Next, a fifth embodiment will be described. FIG. 9 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the fifth embodiment. While the second embodiment is a Schottky gate type transistor, the present embodiment is a MIS gate type transistor. That is, as shown in FIG. 9, the opening 10 a is not formed in the silicon nitride film 10, and the gate electrode 6 is not in contact with the compound semiconductor region 2. Other configurations are the same as those of the second embodiment.

  According to such 5th Embodiment, the effect similar to 2nd Embodiment can be acquired.

(Sixth embodiment)
Next, a sixth embodiment will be described. FIG. 10 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the sixth embodiment. While the third embodiment is a Schottky gate type transistor, the present embodiment is a MIS gate type transistor. That is, as shown in FIG. 10, the opening 10 a is not formed in the silicon nitride film 10, and the gate electrode 6 is not in contact with the compound semiconductor region 2. Other configurations are the same as those of the second embodiment.

  According to the sixth embodiment, the same effect as that of the third embodiment can be obtained.

(Seventh embodiment)
Next, a seventh embodiment will be described. FIG. 11 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the seventh embodiment. In this embodiment, a mushroom gate electrode 6 a is provided instead of the gate electrode 6. Other configurations are the same as those of the first embodiment.

  The present invention can also be applied to a transistor having such a mushroom gate electrode 6a, and the same effects as those of the first embodiment can be obtained.

  Next, a method for manufacturing a GaN-based HEMT according to the seventh embodiment will be described. 12A to 12D are cross-sectional views illustrating a method of manufacturing the GaN-based HEMT according to the seventh embodiment in the order of steps.

  First, similarly to the first embodiment, the processes up to the formation of the silicon nitride film 10 are performed (FIG. 2D). Next, as shown in FIG. 12A, a fine gate resist pattern 31, a lower layer resist pattern 32, and an upper layer resist pattern 33 are formed on the silicon nitride film 10. The fine gate resist pattern 31 has an opening 31a in a region where a pattern portion of the mushroom gate electrode 6a is to be formed. In the lower resist pattern 32, an opening 32a is formed in a region where an umbrella portion of the gate electrode 6 is to be formed. In the upper resist pattern 33, an opening 33a narrower than the opening 32a is formed.

  In forming the fine gate resist pattern 31, the lower layer resist pattern 32, and the upper layer resist pattern 33, first, a positive electron beam resist agent (trade name: ZEP520-A7: manufactured by Nippon Zeon Co., Ltd.) with a thickness of about 300 nm is used. For example, the resist film is formed by applying by a spin coating method and performing a heat treatment at 180 ° C. for 5 minutes. Next, an alkali-soluble resin (trade name PMGI: manufactured by US Microchem Co., Ltd.) is applied at a thickness of about 500 nm, for example, by spin coating, and heat-treated at 180 ° C. for 3 minutes to form a resist film. Thereafter, a positive electron beam resist agent (trade name: ZEP520-Al7: manufactured by Nippon Zeon Co., Ltd.) is applied at a thickness of about 200 nm, for example, by spin coating, and heat treated at 180 ° C. for 2 minutes to form a resist film. To do. Subsequently, an opening 33a having a diameter of about 0.8 μm is formed in the upper resist agent by an electron beam drawing method. As a result, an upper resist pattern 33 having an opening 33a is obtained. Next, using the upper resist pattern 33 as a mask, the underlying resist agent is wet etched using an alkali developer. As a result, a lower resist pattern 32 having an opening 32a is obtained. By these treatments, as shown in FIG. 12A, a multi-layer resist having a cage structure is obtained. In the present embodiment, the narrowest opening 31a is formed by processing the resist film located at the lowermost position by electron beam drawing. As a result, a fine gate resist pattern 31 having an opening 31a is obtained.

After the formation of the fine gate resist pattern 31, the lower layer resist pattern 32, and the upper layer resist pattern 33, the silicon nitride film 10 is dry-etched with SF ₆ gas using the fine gate resist pattern 31 as a mask, thereby matching with the opening 31a. Opening 10a is formed. Further, as shown in FIG. 12A, a gate electrode 6a is formed in the openings 33a, 32a and 31a. In forming the gate electrode 6a, for example, a Ni layer is formed by vapor deposition, and an Au layer is formed thereon by vapor deposition. The thickness of the Ni layer is about 10 nm, and the thickness of the Au layer is about 300 nm.

  Next, as shown in FIG. 12B, the resist patterns 31, 32, and 33 are removed using a heated organic solvent. That is, even in the formation of the gate electrode 6a, for example, vapor deposition and lift-off techniques are used.

  Subsequently, a low dielectric constant film 11 is formed on the silicon nitride film 10 and, for example, a heat curing process at 350 ° C. is performed for 15 minutes while irradiating excimer light having a wavelength of 222 nm. Further, as shown in FIG. 12C, a resist pattern 24 is formed on the low dielectric constant film 11 so as to cover a portion where the low dielectric constant film 11 remains. Thereafter, dry etching is performed using the resist pattern 24 as a mask to leave the low dielectric constant film 11 at a position spaced apart between the source electrode 4 and the drain electrode 5 in plan view. Then, the resist pattern 24 is removed.

  Thereafter, by performing the same process as in the first embodiment, as shown in FIG. 12D, a GaN-based HEMT (semiconductor device) is completed.

(Eighth embodiment)
Next, an eighth embodiment will be described. FIG. 13 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the eighth embodiment. In this embodiment, a mushroom gate electrode 6 a is provided instead of the gate electrode 6. Other configurations are the same as those of the second embodiment.

  According to the eighth embodiment, the same effect as that of the second embodiment can be obtained.

(Ninth embodiment)
Next, a ninth embodiment will be described. FIG. 14 is a cross-sectional view showing the structure of a GaN-based HEMT (semiconductor device) according to the ninth embodiment. In this embodiment, a mushroom gate electrode 6 a is provided instead of the gate electrode 6. Other configurations are the same as those of the third embodiment.

  According to such 9th Embodiment, the effect similar to 2nd Embodiment can be acquired.

  As shown in FIG. 15, the mushroom type gate electrode 6a may be used for the MIS gate type transistor by combining the fourth embodiment shown in FIG. 7 and the seventh embodiment shown in FIG. . Also, as shown in FIG. 16, the mushroom gate electrode 6a may be used for a MIS gate transistor by combining the fifth embodiment shown in FIG. 9 and the eighth embodiment shown in FIG. . Further, as shown in FIG. 17, the mushroom gate electrode 6a may be used for the MIS gate transistor by combining the sixth embodiment shown in FIG. 10 and the ninth embodiment shown in FIG. .

  Further, as shown in FIG. 18, in the seventh embodiment shown in FIG. 11, the surface layer 2d may be provided with a rectangular recess 2e. Similarly, in the embodiment shown in FIGS. 13, 14, 15, 16, and 17, the surface layer 2d may be provided with a rectangular recess 2e.

(Tenth embodiment)
Next, a tenth embodiment will be described. FIG. 19 is a cross-sectional view showing the structure of an InP-based HEMT (semiconductor device) according to the tenth embodiment.

  In the tenth embodiment, as shown in FIG. 19, for example, a compound semiconductor region 42 is formed on a semi-insulating InP substrate 41. The compound semiconductor region 42 includes a buffer layer 42a, an electron transit layer 42b, an electron supply layer 42c, an etching stopper layer 42d, and a low resistance layer 42e that are sequentially stacked. The buffer layer 42a prevents the propagation of lattice defects existing on the surface of the InP substrate 41 to the electron transit layer.

  In addition, a mesa etching region 30 that defines an active region is formed around the compound semiconductor region 42 as an element isolation region. An opening 42f exposing the etching stopper layer 42d is formed at the center of the low resistance layer 42e, and ohmic electrodes are formed on the low resistance layer 42e as the source electrode 4 or the drain electrode 5 on both sides thereof. Yes. Further, except for the inside of the opening 42 f of the low resistance layer 42 e, a silicon nitride film 40 covering the low resistance layer 42 e, the source electrode 4 and the drain electrode 5 is formed over the mesa etching region 30. Further, the silicon nitride film 10 is formed to cover the silicon nitride film 40 and the opening 42f of the low resistance layer 42e.

  In the silicon nitride film 10, an opening 10 a is formed at a position approximately in the middle between the source electrode 4 and the drain electrode 5. A mushroom gate electrode 6a is formed in contact with the etching stopper layer 42d through the opening 10a.

  A low dielectric constant film 11 is formed on the silicon nitride film 10 so as to cover the gate electrode 6 a at a position away from the source electrode 4 and the drain electrode 5. Further, a silicon nitride film 12 covering the upper surface and side surfaces of the low dielectric constant film 11 is formed on the silicon nitride film 10. Furthermore, a low dielectric constant film 13 is formed on the silicon nitride film 12.

  An opening reaching the source electrode 4 and an opening reaching the drain electrode are formed in the low dielectric constant film 13, the silicon nitride film 12, the silicon nitride film 10, and the silicon nitride film 40. Wirings 14 and 15 connected to the source electrode 4 and the drain electrode 5 through these openings are formed on the low dielectric constant film 13.

  According to the tenth embodiment, the same effect as that of the first embodiment can be obtained. That is, not only a GaN semiconductor device but also an InP semiconductor device can achieve both moisture resistance and high frequency characteristics.

  Next, a method for manufacturing the InP-based HEMT according to the tenth embodiment will be described. 20A to 20K are cross-sectional views illustrating a method of manufacturing an InP-based HEMT according to the tenth embodiment in the order of steps.

  First, as shown in FIG. 20A, a buffer layer 42a, an electron transit layer 42b, an electron supply layer 42c, an etching stopper layer 42d, and a low resistance layer 42e are formed in this order on a semi-insulating InP substrate 41 by, for example, the MOVPE method. Form with. The buffer layer 42a, the electron transit layer 42b, the electron supply layer 42c, the etching stopper layer 42d, and the low resistance layer 42e are included in the compound semiconductor region 42.

  Next, as shown in FIG. 20B, the compound semiconductor region 42 is selectively mesa-etched to form the mesa-etched region 30 that defines the active region in the compound semiconductor region 42 as an element isolation region.

  Thereafter, as shown in FIG. 20C, the source electrode 4 and the drain electrode 5 are formed on the compound semiconductor region 42. In forming the source electrode 4 and the drain electrode 5, first, a resist pattern is formed on the compound semiconductor region 42 to open a region where the source electrode 4 is to be formed and a region where the drain electrode 5 is to be formed. Subsequently, for example, a Ti layer is formed by an evaporation method, a Pt layer is formed thereon by an evaporation method, and an Au layer is further formed thereon by an evaporation method. The thickness of the Ti layer is about 20 nm, the thickness of the Pt layer is about 50 nm, and the thickness of the Au layer is about 200 nm. Then, the resist pattern is removed using a heated organic solvent. That is, in forming the source electrode 4 and the drain electrode 5, for example, vapor deposition and lift-off techniques are used. Thereafter, heat treatment is performed to make ohmic contact between the low resistance layer 42e and the source electrode 4 and the drain electrode 5.

  Next, as shown in FIG. 20D, a silicon nitride film 40 covering the source electrode 4 and the drain electrode 5 is formed by plasma CVD.

  Thereafter, as shown in FIG. 20E, a resist pattern 51 having an opening 51a aligned with a region where the gate electrode 6a is to be formed is formed on the silicon nitride film 40. In forming the resist pattern 51, first, a positive electron beam resist agent (trade name ZEP520-A7: manufactured by Nippon Zeon Co., Ltd.) is applied with a thickness of about 300 nm, for example, by spin coating, and heat-treated at 180 ° C. for 5 minutes. By doing so, a resist film is formed. Next, the opening 51a is formed by processing the resist film by electron beam drawing. As a result, a resist pattern 51 having an opening 51a is obtained.

Thereafter, using the resist pattern 51 as a mask, the silicon nitride film 40 is etched by a dry etching method using SF ₆ gas, and then the low resistance layer 42e is etched by a wet etching method. As shown in FIG. 20F, an opening 40a and an opening 42f are formed in each of the silicon nitride film 40 and the low resistance layer 42e. At this time, the etching stopper layer 42d functions as an etching stopper layer.

  Subsequently, as shown in FIG. 20G, the resist pattern 51 is removed. Next, the silicon nitride film 10 that covers the opening 42f of the low resistance layer 42e and the silicon nitride film 40 is formed.

  Next, as shown in FIG. 20H, a fine gate resist pattern 31, a lower layer resist pattern 32, and an upper layer resist pattern 33 are formed in the same manner as in the seventh embodiment. Thereafter, the silicon nitride film 10 is etched using the fine gate resist pattern 31 as a mask to form the opening 10a. Further, the gate electrode 6a is formed in the openings 33a, 32a and 31a.

  Subsequently, as shown in FIG. 20I, the resist patterns 31, 32, and 33 are removed using a heated organic solvent. That is, even in the formation of the gate electrode 6a, for example, vapor deposition and lift-off techniques are used.

  Next, a low dielectric constant film 11 is formed on the silicon nitride film 10 and, for example, a heat curing process at 350 ° C. is performed for 15 minutes while irradiating excimer light having a wavelength of 222 nm. Further, as shown in FIG. 20J, a resist pattern 24 is formed on the low dielectric constant film 11 so as to cover a portion where the low dielectric constant film 11 remains. Thereafter, dry etching is performed using the resist pattern 24 as a mask to leave the low dielectric constant film 11 at a position spaced apart between the source electrode 4 and the drain electrode 5 in plan view. Then, the resist pattern 24 is removed.

  Thereafter, by performing the same processing as in the first embodiment, as shown in FIG. 20K, an InP-based HEMT (semiconductor device) is completed.

  As shown in FIG. 21, an InP-based HEMT may have the same structure as that of the second embodiment shown in FIG. Further, as shown in FIG. 22, an InP-based HEMT may adopt the same structure as that of the third embodiment shown in FIG.

  In any of the embodiments, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, or the like may be used as a substrate instead of a compound semiconductor substrate such as a GaN substrate or an InP substrate. Further, the substrate may not be semi-insulating.

It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 1st Embodiment. It is sectional drawing which shows the method of manufacturing the GaN-type HEMT which concerns on 1st Embodiment following FIG. 2A. FIG. 2B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2B. FIG. 2C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2C. FIG. 2D is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2D. FIG. 2E is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2E. FIG. 2F is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2F. FIG. 2G is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2G. FIG. 2H is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2H. FIG. 2D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2I. 2J is a cross-sectional view illustrating a method of manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2J. FIG. 2D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the first embodiment, following FIG. 2K. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 2nd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 2nd Embodiment. FIG. 4B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 4A. FIG. 4B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment following FIG. 4B. FIG. 4C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the second embodiment, following FIG. 4C. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 3rd Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 3rd Embodiment. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 6A. FIG. 6B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the third embodiment, following FIG. 6B. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 4th Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 4th Embodiment. It is sectional drawing which shows the method of manufacturing the GaN-type HEMT which concerns on 4th Embodiment following FIG. 8A. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 5th Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 6th Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 7th Embodiment. It is sectional drawing which shows the method of manufacturing GaN-type HEMT which concerns on 7th Embodiment. FIG. 12D is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the seventh embodiment, following FIG. 12A. FIG. 12B is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the seventh embodiment, following FIG. 12B. FIG. 12C is a cross-sectional view illustrating a method for manufacturing the GaN-based HEMT according to the seventh embodiment, following FIG. 12C. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 8th Embodiment. It is sectional drawing which shows the structure of GaN-type HEMT which concerns on 9th Embodiment. It is sectional drawing which shows the structure of embodiment which combined 4th Embodiment and 7th Embodiment. It is sectional drawing which shows the structure of embodiment which combined 5th Embodiment and 8th Embodiment. It is sectional drawing which shows the structure of embodiment which combined 6th Embodiment and 9th Embodiment. It is sectional drawing which shows the structure of embodiment which provided the recess in 7th Embodiment. It is sectional drawing which shows the structure of InP type HEMT which concerns on 10th Embodiment. It is sectional drawing which shows the method of manufacturing InPN type HEMT which concerns on 10th Embodiment. FIG. 20B is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20A. FIG. 20B is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20B. FIG. 20C is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20C. FIG. 20D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20D. FIG. 20D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20E. FIG. 20D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20F. FIG. 20G is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20G. FIG. 20D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20H. FIG. 21D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20I. FIG. 20D is a cross-sectional view illustrating a method for manufacturing the InP-based HEMT according to the tenth embodiment, following FIG. 20J. It is sectional drawing which shows the structure of embodiment which employ | adopted the structure similar to 2nd Embodiment in InP type HEMT. It is sectional drawing which shows the structure of embodiment which employ | adopted the structure similar to 3rd Embodiment in InP type HEMT. It is sectional drawing which shows the structure of the modification of 3rd Embodiment. It is sectional drawing which shows the structure of the conventional HEMT.

Explanation of symbols

1: SiC substrate 2: Compound semiconductor region 2e: Recess 3: Element isolation region 4: Source electrode 5: Drain electrode 6, 6a: Gate electrode 10, 12: Silicon nitride film 10a: Opening portion 11, 13: Low dielectric constant film 14, 15: Wiring 41: InP substrate 42: Compound semiconductor region 30: Mesa etching region

Claims (5)

A compound semiconductor region;
A source electrode and a drain electrode formed on the compound semiconductor region;
A first silicon nitride film covering the compound semiconductor region, the source electrode and the drain electrode;
In contact with the compound semiconductor region through an opening formed in the first silicon nitride film at a position between the source electrode and the drain electrode, or in contact with the first silicon nitride film a gate electrode formed on the compound semiconductor region,
A low dielectric constant film covering the gate electrode in a region between the source electrode and the drain electrode;
Formed on the first silicon nitride film, a second silicon nitride film covering the upper and side surfaces of the low dielectric constant film,
A low dielectric constant moisture-resistant film formed on the second silicon nitride film ;
Have
The relative dielectric constant of the low dielectric constant film is lower than any of the relative dielectric constants of the first silicon nitride film, the second silicon nitride film, and the moisture resistant film,
The low dielectric constant film is separated from the source electrode and the drain electrode;
There is no cavity between the first silicon nitride film and the compound semiconductor region,
The first silicon nitride film covers the compound semiconductor region under the low dielectric constant film in a region between the gate electrode and the drain electrode in plan view, and is continuous with the second silicon nitride film. A semiconductor device comprising: The semiconductor device according to claim 1, wherein the gate electrode is provided at a position closer to the source electrode than the drain electrode. 3. The semiconductor device according to claim 1, further comprising a wiring connected to the source electrode and extending above the gate electrode on the moisture-resistant film. The moisture-resistant film, a semiconductor device according to any one of claims 1 to 3, characterized in that it contains organic matter. The compound semiconductor region, a step that form the source over source electrode and a drain electrode,
Forming a first silicon nitride film covering the compound semiconductor region, the source electrode and the drain electrode;
In contact with the compound semiconductor region through an opening formed in the first silicon nitride film at a position between the source electrode and the drain electrode, or in contact with the first silicon nitride film Forming a gate electrode on the compound semiconductor region;
In a region between the source electrode and the drain electrode, the steps that form the low dielectric constant film that covers the front Symbol gate electrode,
Forming a second silicon nitride film covering an upper surface and a side surface of the low dielectric constant film on the first silicon nitride film;
Forming a low dielectric constant moisture-resistant film on the second silicon nitride film ;
Have
The relative dielectric constant of the low dielectric constant film is lower than any of the relative dielectric constants of the first silicon nitride film, the second silicon nitride film, and the moisture resistant film,
The low dielectric constant film is separated from the source electrode and the drain electrode;
There is no cavity between the first silicon nitride film and the compound semiconductor region,
The first silicon nitride film covers the compound semiconductor region under the low dielectric constant film in a region between the gate electrode and the drain electrode in plan view, and is continuous with the second silicon nitride film. A method of manufacturing a semiconductor device.

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