JPH1065067A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device for achieving high-frequency characteristics, moisture resistance, and high reliability. SOLUTION: A semiconductor device where an active layer 2 including a channel region is formed at the surface part of a semiconductor chip 11 has a fluorine resin film 11 that is formed to cover at least the active layer 2, a polyimide resin film 12 that is formed to cover at least the peripheral part of the semiconductor chip 11, and an epoxy resin film 13 that is formed to cover the entire surface of the semiconductor chip 11. At this time, ε1<=ε2<=ε3 is established among dielectric constants ε1, ε2, and ε3 of the resin films 11, 12, and 13. Therefore, the semiconductor device has improved high-frequency characteristics since the active layer 2 is covered with the fluorine resin film 11 with a low dielectric constant and has a high moisture resistance since the epoxy resin film that cannot be peeled between other materials and has improved stabilization of ink is formed at a peripheral part, and no ink flows to the surrounding, thus improving reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a molded resin-sealed semiconductor device for a high electron transfer transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a compound semiconductor device, for example, there is a high electron transfer transistor (hereinafter referred to as HEMT) which is an amplifying semiconductor device used in a high frequency band. This HEM
At T, a ceramic package is used for the envelope in order to suppress deterioration of characteristics in a high frequency band. In the step of sealing a semiconductor chip using a ceramic package, the chip is placed in an inert gas atmosphere. The inert gas has a small relative dielectric constant of approximately 1, and a dielectric loss angle tangent (tan δ) of approximately zero. For this reason, by sealing with a ceramic package, a good characteristic that the power loss is small in a high frequency band can be obtained. However, when a ceramic package is used for the envelope, there is a problem that the product cost increases because the material cost is high and the production efficiency is low.

In recent years, therefore, HEMTs have been used to seal semiconductor chips with a molding resin having a low material cost. When using mold resin,
Since mechanical stress is applied to the semiconductor chip, a protective film is often provided between the semiconductor chip and the mold resin.
For example, CVD (CHEMICAL VAPOR DEPOS)
ITION) method.

However, the relative dielectric constant of a protective film made of a silicon compound is considerably large, such as about 7 as compared with the relative dielectric constant of an inert gas. For this reason, the parasitic capacitance of the gate electrode increases, and as a result, the high-frequency characteristics deteriorate. If the protective film is deposited to a thickness of 20 nm or more in an attempt to reduce the parasitic capacitance, film stress acts on the semiconductor chip, causing stress to be applied to the semiconductor chip, resulting in cuts at the gate portion and deterioration of characteristics. There is.
Furthermore, since the silicon compound used for the protective film is a dielectric, the high-frequency characteristics deteriorate.

Conversely, when a thin protective film is deposited, the chip cannot be sufficiently protected from the mechanical stress acting when the semiconductor chip is sealed with the mold resin, and the gate thin line electrode becomes a stepped line. Damage may occur.

Therefore, a conventional apparatus having a cross-sectional structure as shown in FIG. 10 has been proposed by the same applicant (Japanese Patent Application No. 5-185057). The semiconductor chip 1 is mounted on the bed of the lead frame 17, and the source electrode 3, the drain electrode 4 and the gate electrode 5 are formed on the upper surface of the active layer 2 on the surface of the semiconductor chip 1. Bonding pads 3a, 4a are formed on the source electrode 3 and the drain electrode 4, respectively, to which bonding wires 16 are connected. Here, the surface of the chip is covered with a fluororesin 11 as a protective film, and the entire surface is sealed with a mold resin 13.

As described above, by covering the surface of the semiconductor chip with a fluorine-based resin having a relative dielectric constant and a dielectric loss angle tangent smaller than that of the mold resin, high-frequency characteristics are improved.

However, fluorine-based resins do not have good adhesion to other materials, and are liable to peel off from semiconductor chips. Therefore, when the sealed device is humidified at a humidity of 60% or more and a test is performed under the reliability acceleration condition of pressurizing at a pressure of 2000 hPa or more, moisture enters from the interface between the surface of the semiconductor chip and the fluorine-based resin. I was As a result,
Moisture reached the channel portion, causing a short circuit in the gate electrode portion, resulting in destruction.

In addition, the characteristics of the semiconductor chip are tested using a DC tester, and a good product and a defective product are selected. Then, a mark is printed on the defective semiconductor chip with ink. However, since the fluorine-based resin shows the releasability also to the ink mark, the ink mark on the chip flows easily without being fixed on the surface. Also, HE
In the MT, an epitaxial growth substrate is used, and the price of the substrate is high, so that the chip area is reduced and the product cost is reduced. In a small device having a chip area of 1 mm × 1 mm or less, it is practically impossible to select and print defective products because the ink flows to the surrounding chips.

[0010]

As described above, the HE
In a semiconductor device for a high frequency band such as MT, when sealed with a ceramic package, there is a problem that the high frequency characteristics are excellent but the material cost is high.

When a molded package is used, the chip surface is covered with a silicon compound as a protective film so as not to damage the gate thin line electrode during sealing. Therefore, the high-frequency characteristics deteriorated, and when the film thickness was small, damage to the stepped line of the gate thin line electrode and the like was unavoidable.

Some devices have improved high-frequency characteristics by covering the chip surface with a fluorine-based resin. However, the device has low moisture resistance, lowers reliability, and displays the result of sorting good and defective products with ink on the surface. It was difficult.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device which is excellent in both high-frequency characteristics and moisture resistance and can contribute to cost reduction, and a method of manufacturing the same.

[0014]

According to the present invention, there is provided a semiconductor device comprising:
An element having a channel region formed on a surface portion of the semiconductor chip, a first resin film formed so as to cover at least the channel region of the semiconductor chip;
A second resin film formed so as to cover at least a peripheral portion of the semiconductor chip, and a third resin film formed so as to cover the entire surface of the semiconductor chip on which the first and second resin films are formed. A resin film is provided, and a relation of ε1 ≦ ε2 ≦ ε3 is established between the dielectric constants ε1, ε2, and ε3 of the first, second, and third resin films.

According to another aspect of the present invention, there is provided a semiconductor device comprising: an insulating protective film formed so as to cover a surface of the semiconductor chip;
A first resin film formed so as to cover at least the channel region on the surface of the semiconductor chip covered with the protective film, and cover at least a peripheral surface of the semiconductor substrate covered with the protective film; The second formed
A resin film, a lead frame on which the semiconductor chip is mounted, a bonding wire connected to a pad on the semiconductor chip, and the first and second resin films are formed and mounted on the lead frame; A third resin film covering the entire surface of the semiconductor substrate to which the bonding wires are connected; and a dielectric constant ε1, ε2, ε3 of each of the first, second, and third resin films, ε1
≦ ε2 ≦ ε3 holds, and the first, second and third relations are satisfied.
Dielectric loss tangents tan δ1, tan δ
2. Between tan δ3, tan δ1 ≦ tan δ2 ≦ tan δ3
Is established.

Here, it is preferable that the second resin film is formed so as to cover an interface between the semiconductor chip and an outer edge of the first resin film.

The first, second, and third resin films are made of a fluorine-based resin, a polyimide-based resin, and an epoxy-based resin, respectively, and further have a dielectric constant of each of the first, second, and third resin films. Loss angle tangent tan δ1, tan δ2, tan
The relationship of tan δ1 ≦ tan δ2 ≦ tan δ3 may be established between δ3.

According to a method of manufacturing a semiconductor device of the present invention, a plurality of elements each having a channel region are formed for each of a plurality of semiconductor chips on a surface portion of a semiconductor substrate; Forming a first resin film so as to cover a surface of the channel region; forming a second resin film so as to cover at least a surface of a peripheral portion of each semiconductor chip of the semiconductor substrate; Dividing the semiconductor substrate into a plurality of semiconductor chips using the portion covered by the resin film as a dicing surface, mounting the semiconductor chips on a lead frame, and performing wire bonding on pads of the semiconductor chips. And a step of forming a third resin film so as to cover the entire surface of each of the semiconductor chips. First, each of the dielectric constant of the second and third resin film .epsilon.1, .epsilon.2, during ε3 is, .epsilon.1 ≦ .epsilon.2 ≦
The relationship of ε3 is established.

In another method of manufacturing a semiconductor device according to the present invention, the method further comprises forming an insulating protective film so as to cover at least a surface of the channel region in each semiconductor chip of the semiconductor substrate; Forming a first resin film so as to cover at least a surface of the channel region covered with the protective film in the semiconductor chip;
Forming a second resin film so as to cover at least a peripheral surface of the semiconductor substrate covered with the protective film;
Dividing the semiconductor substrate into a plurality of semiconductor chips by using a portion covered with the second resin film as a dicing surface, mounting the semiconductor chips on a lead frame, and connecting wires to pads of the semiconductor chips. A bonding step; and a step of forming a third resin film so as to cover the entire surface of each of the semiconductor chips, wherein a dielectric constant ε1, The relationship of ε1 ≦ ε2 ≦ ε3 holds between ε2 and ε3.

Preferably, the second resin film is formed so as to cover an interface between the semiconductor chip and an outer edge of the first resin film, and further, the first, second and third resins are formed. The films are each made of a fluorine-based resin, a polyimide-based resin, and an epoxy-based resin. The dielectric loss tangents tan δ1, tan δ2, and ta of the first, second, and third resin films, respectively.
The relationship of tan δ1 ≦ tan δ2 ≦ tan δ3 may be established between n δ3.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, FIG. 2 shows a schematic longitudinal sectional structure of the semiconductor device according to the present embodiment. An active layer is formed on the surface of the semiconductor chip 1a mounted on the lead frame 17, and source, drain and channel regions are formed on the upper surface of the active layer. The top surface of the active layer,
In particular, the surface of the channel region is covered with a protective film made of a silicon compound or the like, and this protective film is covered with the fluorine-based resin 11. The outer periphery of the semiconductor substrate 1a is covered with a polyimide resin 12 so as to surround the fluorine-based resin 1, and is further covered with an epoxy resin 13 so as to surround the whole.

FIG. 1 shows a more detailed sectional structure of such a semiconductor device. An active layer 2 is formed on the surface of the semiconductor chip 1a, and a source electrode 3 and a drain electrode 4 are formed on the upper surface of the active layer 2 at a predetermined interval.
The active layer 2 during this period corresponds to a channel region. Bonding pads 10a and 10b are formed on the source electrode 3 and the drain electrode 4, respectively, and a gate electrode 5 is formed on the channel region.

The channel region in the active layer 2, the gate electrode 5, the source electrode 3 and the drain electrode 4
It is covered with a protective film 6 of a silicon compound or the like having a thickness of not more than nm. The upper surface of the protective film 6 is covered with a fluorine-based resin film 11 of 10 μm or less, and the outer periphery of the semiconductor chip 1 a is covered with a polyimide-based resin 12 so as to surround the fluorine-based resin film 11. Finally, the entire semiconductor chip 1 a, the bonding pads 16, the bed of the lead frame 17, and the inner leads are covered with the epoxy resin 13.

Here, assuming that the relative permittivity of the fluororesin is ε1, the relative permittivity of the polyimide resin is ε2, and the relative permittivity of the epoxy resin is ε3, ε1 is 2.2 or less and ε2
Is 4 or less, and ε3 is a value that satisfies the relationship of ε1 ≦ ε2 ≦ ε3. Further, the dielectric loss angle tangent of the fluororesin is tan δ1, and the dielectric loss tangent of the polyimide resin is ta.
Assuming that n δ2 and the dielectric loss angle tangent of the epoxy resin are tan δ3, tan δ1 is 0.001 and tan δ2 ≦
The relationship of tan δ3 holds.

Next, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG.
As shown in FIG. 1A, an impurity is implanted into a surface portion of a semiconductor substrate 1 to form an active layer 2, and a source electrode 3 and a drain electrode 4 are formed so as to make ohmic contact with the active layer 2. . A gate electrode 5 is formed on the upper surface of active layer 2 between source electrode 3 and drain electrode 4 so as to make Schottky contact. A bonding pad 10a is formed so as to be in contact with source electrode 3, and similarly, a bonding pad 10b is formed so as to be in contact with drain electrode 4.
Is formed. A protective film 6 is formed so as to cover the upper surfaces of the source electrode 3, the drain electrode 4, and the gate electrode 5.
As the protective film 6, for example, a silicon nitride film deposited by a plasma CVD method or the like is used.
Set to nm.

In the protective film 6, holes for making the source electrode 3 contact the bonding pad 10a and for making the drain electrode 4 contact the bonding pad 10b are formed, and gold is vapor-deposited and lifted off to form the bonding pad 10a. And 10b.

As shown in FIG. 3 (b), a solvent containing a fluorine-based polymer is spin-coated on the semiconductor substrate 1, cured and baked at a temperature of 150 ° C. or more to evaporate the solvent, thereby obtaining a fluorine-based polymer. The resin film 11 is formed. Here, the film thickness of the fluorine-based resin film 11 is set so as to be 10 μm or less after cure baking. A photoresist is applied to the entire surface, and the bonding pad 1 is formed by photolithography.
A resist film from which the bonding wire connection portions on the upper surfaces of 0a and 10b and the dicing lines are removed is formed, and the fluorine-based resin film 11 is subjected to dry etching and patterned using the resist film as a mask.

As shown in FIG. 3C, a polyimide resin 12 is applied to the entire surface, and the gate electrode 5 on the channel region of the active layer 2 on the surface of the semiconductor substrate and the source region 3 and the drain region 4 are formed. Top polyimide resin 1
Remove 2.

In order to set the thickness of the semiconductor substrate 1 to a set value, lapping is performed as necessary. As shown in FIG. 3D, the dicing line of the semiconductor substrate 1 including the polyimide resin 12 is cut using a dicing saw, and divided into a plurality of semiconductor chips 1a. Each of the divided semiconductor chips 1a is mounted on a bed of a frame, and wire bonding is performed on the bonding pads 10a and 10b.

The semiconductor chip 1a mounted on the frame is sealed with an epoxy resin by the transfer molding method. Thereafter, lead cutting, shaping, and the like of the lead frame are performed to complete the semiconductor device.

As described above, in the manufacturing method according to the present embodiment, the relative dielectric constant ε1 is 2.2 or less and the dielectric loss angle ta
By covering the vicinity of the gate electrode 5 with a fluorine resin having n δ of 0.001 or less, the capacitance floating on the gate electrode can be suppressed, and the characteristics in a high frequency band can be improved.

Furthermore, by covering the periphery of the semiconductor substrate with a polyimide resin, it is possible to prevent moisture from entering the interface between the surface of the semiconductor substrate and the fluorine resin, thereby improving the moisture resistance and the reliability of the product. it can. The surface of the polyimide-based resin has good ink fixability, and a test for selecting good or defective products is performed, and ink is prevented from flowing when defective products are printed and displayed.

In the step of dividing the semiconductor substrate into chips, the semiconductor substrate is diced with a dicing saw from the upper surface of the polyimide resin. Therefore, chipping of the semiconductor substrate around the dicing surface can be suppressed small, and the yield in this step is improved.

FIGS. 4 and 5 show the results of experiments performed on the semiconductor device according to the present embodiment. First, a reverse bias voltage is applied between the gate and the source before performing the process of leaving the semiconductor device of the present embodiment to be left for 50 hours in an atmosphere of 115 degrees Celsius, 85% of humidity, and 2000 hPa of air pressure, respectively. 4 shows the reverse current of the gate and source when the reverse bias voltage is applied between the gate and the source after the processing, and the vertical axis of FIG. 4 shows the reverse current of the gate and source when the reverse bias voltage is applied between the gate and the source after the processing. Show. FIG.
The horizontal axis of the gate / source reverse current before performing the same processing on 25 conventional semiconductor devices is shown on the horizontal axis, and the gate / source reverse current after the processing is performed on the vertical axis of FIG. Show.

As shown in FIG. 5, 22 out of 25 conventional semiconductor devices showed characteristic fluctuations before and after processing. That is, in the 22 devices, the gate-source reverse current increased after the processing, and the characteristics deteriorated. On the other hand, in the device according to the present embodiment, in all 25 devices, no change was observed in the gate / source reverse current before and after the processing, and it was found that the characteristics were not degraded.

Further, the InAlAs according to the present embodiment
Using In / InGaAs / InP compound semiconductor substrate
Similarly, a MESFET using MT or GaAs and a conventional semiconductor device using the same substrate are divided into a plurality of semiconductor chips by a dicing saw, the surface of the semiconductor chip is inspected with a microscope, and the semiconductor chip is subjected to a dicing process. FIG. 6 shows the result of measuring the yield. The dimensions of the semiconductor chip are 400 × 320 μm for a MESFET using an InAlAs / InGaAs / InP compound semiconductor substrate,
In the MESFET using the aAa compound semiconductor substrate, 56
0 × 400 μm, dicing width is InAlAsGaAs
In the MESFET using the / InP compound semiconductor substrate, 6
ME using 0 × 48 μm GaAs compound semiconductor substrate
SFET is 56 × 42 μm, blade width is 20 μm
m. As is apparent from FIG. 6, according to the present embodiment, the yield in the dicing step is improved as compared with the conventional apparatus. This is because, as described above, in the present embodiment, since dicing is performed in a state where the polyimide resin is coated on the semiconductor substrate, cracks or chips are prevented from being generated in the semiconductor substrate near the dicing surface. It is believed that there is. Furthermore, according to the present embodiment, even when the dicing width is set as narrow as 52 × 42 μm, it is possible to prevent chipping of the semiconductor chip in the dicing step, so that a large number of semiconductor wafers having the same dimensions can be formed. The semiconductor chip can be taken out.

Further, according to the present embodiment, even when the test result is displayed on the chip surface as ink, the ink does not flow to the adjacent chip without being fixed, thereby preventing the occurrence of a defect due to the ink. it can.

FIGS. 7A and 7B show the results obtained by measuring the noise figure at 12 GHz using 20 semiconductor devices according to the present embodiment and 20 conventional devices. Most of the devices according to this embodiment are 0.5 d
Although the noise figure is concentrated near B, the conventional apparatus has a noise figure of 0.1.
Many of them exceed 5 dB. As described above, according to the present embodiment, noise immunity can be improved.

Next, FIG. 8 shows a vertical sectional structure of a semiconductor device according to another embodiment of the present invention. In the embodiment shown in FIG. 1, the polyimide resin 12 covers the end surface of the fluorine-based resin 11 covering the upper surface of the active layer 2 including the channel region. On the other hand, in the embodiment shown in FIG. 8, the end surface of the fluorine-based resin 11 is formed on the periphery of the semiconductor substrate 11 without being covered with the polyimide-based resin 12. Further, in the device according to still another embodiment of the present invention shown in FIG. 9, the upper surface of the active layer 2 is covered with a fluorine-based resin 11, and the polyimide-based resin 12 is formed not only on the periphery of the semiconductor substrate 11 but also on the surface. It is formed so as to cover the whole.

The above embodiments are merely examples, and do not limit the present invention. For example, the device according to the embodiment shown in FIGS. 1, 8 and 9 has a structure for sealing an element having an active layer 2, a source electrode 3, a drain electrode 4, and bonding pads 10a and 10b. However, the present invention is not necessarily required to have the same configuration, and the present invention can be widely applied to a device that is sealed with a mold resin.

[0041]

As described above, according to the semiconductor device and the manufacturing method of the present invention, since at least the channel region is covered with the fluorine-based resin having a low dielectric constant, the high frequency characteristics are excellent, and at least the periphery of the semiconductor chip is formed. By being covered with a polyimide resin that has excellent moisture resistance and good ink fixability, it is possible to prevent intrusion of moisture and perform printing to determine good or bad, and improve reliability. it can.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing the overall schematic configuration of the semiconductor device.

FIG. 3 is a longitudinal sectional view showing a method of manufacturing the semiconductor device according to the embodiment of the present invention step by step.

FIG. 4 is a graph showing the results of measuring the gate / source reverse current before and after heating, humidification, and pressure treatment of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a graph showing the results of measuring the gate / source reverse current before and after heating, humidification, and pressure treatment of a conventional semiconductor device.

FIG. 6 is an explanatory diagram showing a result of measuring a yield rate when dicing is performed on the semiconductor device according to the embodiment of the present invention and a conventional semiconductor device.

FIG. 7 is a graph showing the results of measuring the noise figure of the semiconductor device according to the embodiment of the present invention and the conventional semiconductor device.

FIG. 8 is a longitudinal sectional view showing a sectional structure of a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a longitudinal sectional view showing a sectional structure of a semiconductor device according to still another embodiment of the present invention.

FIG. 10 is a longitudinal sectional view showing a sectional structure of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Semiconductor chip 2 Active layer 3 Source electrode 4 Drain electrode 5 Gate electrode 6 Protective film 10a, 10b Bonding pad 11 Fluorine resin 12 Polyimide resin 13 Epoxy resin 16 Bonding wire 17 Lead frame

Continuation of the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical indication location H01L 29/812 9447-4M H01L 29/80 H 29/778 // B29L 31:34 (72) Inventor Imamura Soichi 1 Komukai Toshiba-cho, Saiyuki-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Tamagawa Plant

Claims (8)

[Claims] 1. A semiconductor device in which an element having a channel region is formed on a surface portion of a semiconductor chip, wherein: a first resin film formed so as to cover at least the channel region of the semiconductor chip; A second resin film formed so as to cover at least a peripheral portion of the semiconductor chip; and a third resin film formed so as to cover the entire surface of the semiconductor chip on which the first and second resin films are formed. And a dielectric constant ε of each of the first, second, and third resin films.
1. A semiconductor device, wherein a relationship of ε1 ≦ ε2 ≦ ε3 is established between 1, ε2 and ε3. 2. A semiconductor device having an element having a channel region formed on a surface portion of a semiconductor chip, comprising: an insulating protective film formed so as to cover a surface of the semiconductor chip; A first resin film formed so as to cover at least the channel region on the surface of the semiconductor chip; and a second resin film formed so as to cover at least the peripheral surface of the semiconductor substrate covered with the protective film. A lead frame on which the semiconductor chip is mounted, a bonding wire connected to a pad on the semiconductor chip, and the first and second resin films are formed and mounted on the lead frame; A third resin film that covers the entire surface of the semiconductor substrate to which the bonding wires are connected, and that of the first, second, and third resin films. Dielectric constant ε
A relationship of ε1 ≦ ε2 ≦ ε3 is established between 1, ε2, and ε3, and a dielectric loss angle tangent tan δ1, tanδ2, tanδ3 of each of the first, second, and third resin films. Is a semiconductor device, wherein a relationship of tan δ1 ≦ tan δ2 ≦ tan δ3 is satisfied. 3. The semiconductor according to claim 1, wherein the second resin film is formed so as to cover an interface between the semiconductor chip and an outer edge of the first resin film. apparatus. 4. The first, second, and third resin films are made of a fluorine-based resin, a polyimide-based resin, and an epoxy-based resin, respectively, and each of the first, second, and third resin films has a dielectric constant. 4. The semiconductor device according to claim 1, wherein a relationship of tan δ1 ≦ tan δ2 ≦ tan δ3 is established among the loss angle tangents tan δ1, tan δ2, and tan δ3. 5. A step of forming a plurality of elements having a channel region for each of a plurality of semiconductor chips on a surface portion of a semiconductor substrate, and covering at least a surface of the channel region in each semiconductor chip of the semiconductor substrate. Forming a first resin film, forming a second resin film so as to cover at least a peripheral surface of each semiconductor chip of the semiconductor substrate, and forming a first resin film covered with the second resin film. Dividing the semiconductor substrate into a plurality of semiconductor chips, with the portion having the dicing surface as a dicing surface; mounting the semiconductor chips on a lead frame, respectively; and performing wire bonding to pads of the semiconductor chips; Forming a third resin film so as to cover the entire surface of each of the first, second and third resins. Each of the dielectric constant .epsilon.1 of, .epsilon.2, between .epsilon.3, a method of manufacturing a semiconductor device, wherein a relationship of ε1 ≦ ε2 ≦ ε3 is established. 6. A step of forming a plurality of elements having a channel region for each of a plurality of semiconductor chips on a surface portion of a semiconductor substrate; and covering at least a surface of the channel region in each semiconductor chip of the semiconductor substrate. Forming an insulating protective film on the semiconductor substrate; forming a first resin film so as to cover at least a surface of the channel region covered with the protective film in each semiconductor chip of the semiconductor substrate; Forming a second resin film so as to cover at least a surface of a peripheral portion of the substrate covered with the protective film; and using the portion covered with the second resin film as a dicing surface to form the semiconductor substrate. Dividing the semiconductor chip into a plurality of semiconductor chips; mounting each of the semiconductor chips on a lead frame; And a step of forming a third resin film so as to cover the entire surface of each of the semiconductor chips. The dielectric constant ε1 of each of the first, second and third resin films is provided. , Ε2, ε3, a relationship of ε1 ≦ ε2 ≦ ε3 holds. 7. The semiconductor device according to claim 5, wherein said second resin film is formed so as to cover an interface between said semiconductor chip and an outer edge portion of said first resin film. Manufacturing method. 8. The first, second, and third resin films are made of a fluorine resin, a polyimide resin, and an epoxy resin, respectively, and each of the first, second, and third resin films has a dielectric constant. 8. The method of manufacturing a semiconductor device according to claim 5, wherein a relationship of tan δ1 ≦ tan δ2 ≦ tan δ3 is established among the loss angle tangents tan δ1, tan δ2, and tan δ3.