JP3860717B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for coating a step surface, which is an element of a stepped structure, with an organic insulator.
[0002]
[Prior art]
Semiconductor elements are often coated with an organic insulator in order to protect (passivate) the surface and increase reliability. For example, the heterojunction bipolar transistor shown in FIG. 9 is covered with an organic insulator 508 on the surface side (referring to the upper surface side in FIG. 9) (Japanese Patent Laid-Open No. 11-186278). Specifically, the subcollector layer 502, the collector / base layer (including the collector layer on the lower side and the base layer on the upper side) 503, and the emitter layer 504 that are epitaxially grown on the semiconductor substrate 501 have a wider pattern in the lower layer. The mesa structure having a step-like cross section is formed by etching. Emitter ohmic electrode 505, base ohmic electrode 506, and collector ohmic electrode 507 are formed on the surfaces of emitter layer 504, collector / base layer 503, and subcollector layer 502, respectively. According to this publication, a cycloten resin (trade name) as a precursor to be converted into an organic insulator is applied on the entire surface of the wafer, and compared with the mesa step so that the surface side of the precursor becomes flat. It is thickly applied (spin coating). Subsequently, heat treatment at 250 ° C. is performed to cure the precursor, and the target organic insulator 508 is changed. Thereafter, an insulating film 509 made of silicon oxide is formed on the entire surface of the organic insulator 508, and reactive ion etching is performed to form contact holes, and wirings 510 reaching the lower electrodes 505, 506, and 507 are formed. is doing.
[0003]
[Problems to be solved by the invention]
By the way, the organic insulator 508 often has its own stress when it is formed on the semiconductor surface, that is, when the precursor is cured. In addition, the organic insulator 508 has a coefficient of thermal expansion that is different from that of the semiconductors 501, 502, 503, and 504, the inorganic insulating film 509 formed on the semiconductor surface, and the metal 510. May have stress due to.
[0004]
Therefore, when the organic insulator 508 is formed thick on the entire surface on the wafer as described above, the wafer is warped during the wafer process, pattern formation or the like cannot be performed accurately, or stress is partially concentrated and organic insulation is performed. There arises a problem that the body 508 is broken. Also, if the wafer is separated for each element in the scribe line section after the wafer process is completed, the separated individual elements (chips) are warped, and the subsequent mounting process cannot be performed, or the yield during mounting is reduced. Problems arise.
[0005]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of improving the reliability of a semiconductor device and suppressing problems caused by an organic insulator to solve problems during and after the wafer process. There is.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention has A stepped surface, A stepped structure including a first flat surface continuous with the lower edge of the step surface and a second flat surface continuous with the upper edge of the step surface; and a side beyond the upper edge of the step surface from the second flat surface. A step of applying a precursor having a predetermined viscosity and changing to a predetermined organic insulator on a semiconductor substrate having an eaves element projecting in the direction; and curing the precursor to change it to the organic insulator And step of reactive ion etching to remove portions of the organic insulator existing on the first and second flat surfaces, while the stepped surface is formed below the eaves element of the organic insulator. Forming a sidewall leaving the precursor covering the substrate.
[0007]
According to the method for manufacturing a semiconductor device of the present invention, the stepped surface, which is an element of the staircase structure, is covered with the sidewall made of an organic insulator, so that the reliability of the manufactured semiconductor device is improved. Moreover, on the first and second flat surfaces connected to the lower edge and the upper edge of the step surface, there is substantially no organic insulator except for the portion immediately below the eaves element. Warping can be suppressed. Therefore, no problem occurs during or after the wafer process. In other words, since there is no stress in the planar direction, the wafer warps during the process, the organic insulator and other parts crack, and the element warps even when it is separated for each element (chip) at the scribe line part. Will not occur. Therefore, the yield can be improved and the manufacturing cost can be reduced. Moreover, in this method of manufacturing a semiconductor device, when the precursor is applied, the precursor accumulates in a space surrounded by the eaves element, the step surface, and the first flat surface due to the surface tension of the precursor. . As a result, the sidewall is formed thick according to the projection amount of the eaves element. Therefore, the reliability of the semiconductor device is further increased.
[0008]
In another aspect, the method for manufacturing a semiconductor device according to the present invention is provided on the surface side. A stepped surface, A stepped structure including a first flat surface continuous with the lower edge of the step surface and a second flat surface continuous with the upper edge of the step surface; and a side beyond the upper edge of the step surface from the second flat surface. A step of applying a precursor having a predetermined viscosity and changing to a predetermined organic insulator on a semiconductor substrate having an eaves element protruding in the direction, and performing reactive ion etching, Removing a portion existing on the first and second flat surfaces, and forming a sidewall leaving the precursor covering the stepped surface under the eaves element of the organic insulator; And a step of curing the precursor forming the wall to change to the organic insulator.
[0009]
According to the method for manufacturing a semiconductor device of the present invention, the stepped surface, which is an element of the staircase structure, is covered with the sidewall made of an organic insulator, so that the reliability of the manufactured semiconductor device is improved. Moreover, on the first and second flat surfaces connected to the lower edge and the upper edge of the step surface, there is substantially no organic insulator except for the portion immediately below the eaves element. Warping can be suppressed. Therefore, no problem occurs during or after the wafer process. In addition, in this manufacturing method, the reactive ion etching is performed before the precursor is completely cured. Therefore, the precursor is etched as compared with the case where the reactive ion etching is performed after the precursor is completely cured. The speed can be increased. Therefore, the etching rate ratio with the underlying substrate or wiring material can be relatively increased. As a result, by adjusting the etching conditions and the etching time, damage to the base can be suppressed to a low level. Therefore, the yield can be improved and the manufacturing cost can be reduced. Moreover, in this method of manufacturing a semiconductor device, when the precursor is applied, the precursor accumulates in a space surrounded by the eaves element, the step surface, and the first flat surface due to the surface tension of the precursor. . As a result, the sidewall is formed thick according to the projection amount of the eaves element. Therefore, the reliability of the semiconductor device is further increased.
[0010]
In another aspect, the method for manufacturing a semiconductor device according to the present invention is provided on the surface side. A stepped surface, A stepped structure including a first flat surface continuous with the lower edge of the step surface and a second flat surface continuous with the upper edge of the step surface; and a side beyond the upper edge of the step surface from the second flat surface. A step of applying a precursor having a predetermined viscosity and changing to a predetermined organic insulator on a semiconductor substrate having an eaves element protruding in the direction, and dissolving with a solvent, and the first of the precursors Removing a portion existing on the first and second flat surfaces, and forming a sidewall leaving the precursor covering the stepped surface under the eaves element of the organic insulator; and the sidewall And a step of curing the precursor to form the organic insulator.
[0011]
According to the method for manufacturing a semiconductor device of the present invention, the stepped surface, which is an element of the staircase structure, is covered with the sidewall made of an organic insulator, so that the reliability of the manufactured semiconductor device is improved. Moreover, on the first and second flat surfaces connected to the lower edge and the upper edge of the step surface, there is substantially no organic insulator except for the portion immediately below the eaves element. Warping can be suppressed. Therefore, no problem occurs during or after the wafer process. In addition, in this manufacturing method, since the precursor is dissolved in the solvent, damage to the base can be suppressed as compared with the case where reactive ion etching is performed. In addition, when reactive ion etching is performed, the surface of the precursor (organic insulator) itself may change, and electrical characteristics such as conductivity and dielectric constant may be deteriorated. On the other hand, in this manufacturing method, since the precursor is dissolved in a solvent, it is possible to suppress deterioration of the electrical characteristics of the precursor (organic insulator) as compared with the case where reactive ion etching is performed. it can. Therefore, the yield can be improved and the manufacturing cost can be reduced. Moreover, in this method of manufacturing a semiconductor device, when the precursor is applied, the precursor accumulates in a space surrounded by the eaves element, the step surface, and the first flat surface due to the surface tension of the precursor. . As a result, the sidewall is formed thick according to the projection amount of the eaves element. Therefore, the reliability of the semiconductor device is further increased.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail.
[0013]
(Embodiment 1)
In this embodiment, an example in which a step surface of a Schottky diode having a mesa structure is covered with a sidewall made of an organic insulator will be described.
[0014]
i) First, as shown in FIG. 1A, a high impurity concentration ohmic junction forming semiconductor layer 102 and a low impurity concentration Schottky junction forming semiconductor layer 103 are stepped on a semi-insulating substrate 101. The two-stage mesa structure is formed, and the ohmic electrode 104 having a predetermined thickness is formed at a predetermined position on the ohmic junction forming semiconductor layer 102.
[0015]
Specifically, in this step, the ohmic junction forming semiconductor layer 102 and the Schottky junction forming semiconductor layer 103 are formed in this order by epitaxial growth over the entire area of the substrate 101. On top of this, an inorganic insulating film made of silicon nitride is formed as a mask, and the process of etching the epitaxial layer is performed twice by a known technique, so that the lower layer 102 is wider than the upper layer 103. Thus, the two-step mesa structure formed by the flat surface 103a of the semiconductor layer 103, the step surface 111 of the semiconductor layer 103, the flat surface 102a of the semiconductor layer 102, the step surface 107 of the semiconductor layer 102, and the flat surface 101a of the substrate 101 is formed. Form. At this time, the inorganic insulating film 105 used as a mask for etching the ohmic junction forming semiconductor layer 102 is left, and the inorganic insulating film 105 is located at a position corresponding to the flat surface 102 a of the ohmic junction forming semiconductor layer 102. An opening 150 is formed. On top of this, an ohmic electrode material is vapor-deposited to a predetermined thickness, and pattern processing and heat treatment are performed to form an ohmic electrode 104 in ohmic contact with the underlying semiconductor layer 102 for forming an ohmic junction.
[0016]
In this example, the inorganic insulating film 105 is left so as to form an eaves element 114 that protrudes laterally from the flat surface 102 a of the semiconductor layer 102 beyond the upper edge of the stepped surface 107.
[0017]
In this example, the distance 115 (see FIG. 1B) between the side surface of the ohmic electrode 104 and the stepped surface 111 of the semiconductor layer 103 is set to be relatively short, and the ohmic with respect to the flat surface 103a of the semiconductor layer 103 is set. The height 116 (see FIG. 1B) of the flat surface 104a of the electrode 104 is set high.
[0018]
ii) Next, as shown in FIG. 1B, a precursor 106 to be changed into a predetermined organic insulator is applied in a film shape over the entire area of the substrate 101 by a spin coating method.
[0019]
Specifically, in this step, the precursor 106 is appropriately thinned with a solvent so as to reduce the viscosity, whereby the substrate 101, the semiconductor layers 102 and 103, and the flat surfaces 101a, 102a, 103a, and 104a of the electrode 104 are formed. On the other hand, coating is performed so that the thickness gradually increases from the upper part to the lower part of the step surfaces 107 and 111 of the semiconductor layers 102 and 103 and the side surfaces 140 and 141 of the electrode 104. In this example, cycloten (trade name, manufactured by Dow Chemical Co., Ltd.) commercially available as a benzocyclobutene (BCB) group-containing compound was used as the precursor 106. The solution was made into a 5% solution, and the spin coating conditions were set so that the film thickness was about 0.1 μm on the flat surface 101a on the substrate 101.
[0020]
In this example, since the inorganic insulating film 105 is left so as to form the eaves element 114 projecting laterally from the flat surface 102a of the semiconductor layer 102 beyond the upper edge of the stepped surface 107, the precursor 106 is applied. Then, due to the surface tension of the precursor, the precursor 106 accumulates thickly in the space surrounded by the eaves element 114, the stepped surface 107 and the flat surface 101 a of the substrate 101. Therefore, the step surface 107 of the semiconductor layer 102 can be reliably covered with the precursor 106.
[0021]
Further, as described above, the distance 115 between the side surface 140 of the ohmic electrode 104 and the stepped surface 111 of the semiconductor layer 103 is set short, while the flat surface 104a of the ohmic electrode 104 with respect to the flat surface 103a of the semiconductor layer 103 is set. Since the height 116 is set high, the precursor 106 that covers the side surface 140 of the electrode 104 and the stepped surface 111 of the semiconductor layer 103 overlaps in common. Therefore, the step surface 111 of the semiconductor layer 103, particularly the upper portion of the step surface, can be reliably covered with the precursor 106.
[0022]
iii) Next, heat treatment is performed at 250 ° C. to completely cure the precursor 106 and change it into an organic insulator. After this, sulfur hexafluoride (SF ₆ ) And oxygen (O ₂ Anisotropic reactive ion etching is performed using a mixed gas. At this time, by adjusting the etching conditions and etching time, as shown in FIG. 1C, the portions of the organic insulator 106 existing on the flat surfaces of the substrate 101, the semiconductor layers 102 and 103, and the electrode 104 are removed. On the other hand, portions of the organic insulator 106 that cover the step surface 107 of the semiconductor layer 102, the step surface 111 of the semiconductor layer 103, and the side surfaces 140 and 141 of the electrode 104 are left. Thus, sidewalls 108, 109, and 110 made of an organic insulator are formed in a self-aligned manner on the step surface 107 of the semiconductor layer 102 and the side surfaces 140 and 141 of the electrode 104, respectively. At this time, the stepped surface 111 of the semiconductor layer 103 is covered with the sidewall 109 in common with the side surface 140 of the electrode 104.
[0023]
Here, since the inorganic insulating film 105 covers a region where the organic insulator 106 is removed by etching, damage to the underlying semiconductor active layer (the ohmic junction forming semiconductor layers 102 and 103) due to reactive ion etching is prevented. can do. Moreover, damage to the substrate 101 can be reduced by setting the etching time by reactive ion etching as short as possible.
[0024]
iv) Finally, as shown in FIG. 2A, an inorganic insulating film 112 made of silicon nitride is formed over the entire area of the substrate 101, and the Schottky junction forming semiconductor layer 103 of the inorganic insulating film 112 is formed. An opening 151 is formed at a position corresponding to the flat surface 103a. On top of this, a Schottky electrode material is vapor-deposited to a predetermined thickness, subjected to patterning and heat treatment, and has a predetermined thickness to make a Schottky contact with the underlying Schottky junction forming semiconductor layer 103. 113 is formed.
[0025]
In the Schottky diode manufactured as described above, the stepped surface 107 of the semiconductor layer 102 and the stepped surface 111 of the semiconductor layer 103 are covered with the sidewalls 108 and 109 made of organic insulators, respectively, so that the reliability is improved. . Moreover, since there is substantially no organic insulator on the flat surfaces 101a, 102a, and 103a of the substrate 101 and the semiconductor layers 102 and 103 except for the portion directly below the eaves element 114, warping caused by the organic insulator is eliminated. Can be suppressed. Therefore, no problem occurs during or after the wafer process. In other words, since there is no stress in the planar direction, the wafer warps during the process, the organic insulator and other parts crack, and the element warps even when it is separated for each element (chip) at the scribe line part. Will not occur.
[0026]
Note that the step surface 111 of the semiconductor layer 103 is covered with an inorganic insulating film 105 made of silicon nitride before being covered with an organic insulator, but the inorganic insulating film 105 is apt to be thin on the step surface. In many cases, the inorganic insulating film 105 alone cannot improve the water resistance of the element. Therefore, covering the stepped surface 111 of the semiconductor layer 103 with an organic insulator as in this embodiment is effective in improving the reliability of the element.
[0027]
The planar pattern layout of the manufactured Schottky diode is as shown in FIG. 2B (note that FIG. 2A described above corresponds to a cross section taken along line 117 in FIG. 2B). .) As can be seen from FIG. 2B, the patterns of the Schottky junction forming semiconductor layer 103 and the ohmic junction forming semiconductor layer 102 are each rectangular. The eaves element 114 of the inorganic insulating film 105 is provided over the entire circumference of the step surface 111 of the semiconductor layer 103. Therefore, when the precursor 106 is applied, the stepped surface 111 of the semiconductor layer 103 is thickly covered with the precursor 106 over the entire circumference due to the surface tension of the precursor. Therefore, the sidewall 108 is formed thick over the entire circumference of the stepped surface 111 of the semiconductor layer 103, and the reliability of the element can be reliably increased. In FIG. 2B, a portion of the sidewall 108 that exists immediately below the eaves element 114 is not drawn, and only a portion 108a that protrudes laterally from the eaves element 114 is represented by hatching.
[0028]
In addition, the pattern of the ohmic electrode 104 is set in a square shape so as to surround the semiconductor layer 103 having a rectangular pattern at regular intervals. Therefore, the entire periphery of the stepped surface 111 of the semiconductor layer 103 can be reliably covered with the sidewall 109, and the reliability of the element can be reliably increased.
[0029]
Furthermore, according to the manufacturing method described above, the sidewalls 108 and 109 are formed in a self-aligned manner on the step surface 107 of the semiconductor layer 102 and the step surface 111 of the semiconductor layer 103, respectively, so that the sidewalls are finished to a uniform width. . Therefore, the strength of the sidewalls 108 and 109 made of an organic insulator can be increased and stabilized.
[0030]
In the present embodiment, the stepped surface of the mesa structure of the Schottky diode is protected by the side wall made of an organic insulator. However, the present invention is not limited to this. The present invention can be applied to the protection of step surfaces of various types of semiconductor elements.
[0031]
For example, the sidewall made of the organic insulator according to the present embodiment is formed along the step surface to protect the step surface, or more reliably protected by using an eave-like protrusion on the upper portion of the semiconductor step. The configuration to be performed can be performed on the semiconductor step of the mesa structure formed of the semiconductor layer for forming the Schottky junction, the semiconductor step of the mesa structure of the heterojunction bipolar transistor or the field effect transistor, The same can be applied to the semiconductor step of the resistance element formed by the mesa structure.
[0032]
In particular, this configuration has an advantage that it is not necessary to form a wiring in the vicinity of the step, so that it is formed at an early stage of the process, and damage to the organic insulating film during the process can be avoided.
[0033]
In addition, there is an advantage that the degree of freedom of structure is high because it is not necessary to arrange electrodes around the steps.
[0034]
Therefore, it is particularly effective for a resistance element having a configuration in which ohmic electrodes are formed at both ends of the mesa structure and a semiconductor step located in a portion between different wiring electrodes of the element.
[0035]
On the other hand, the configuration in which the side wall made of an organic insulator formed along the side wall of the electrode located under the semiconductor step of the present embodiment protects the step surface is also in contrast to the mesa step made of the contact layer. The present invention can also be applied to a semiconductor step of a mesa structure of a heterojunction bipolar transistor or a field effect transistor, and further to a resistance element formed by a mesa structure.
[0036]
This configuration is particularly effective in a vertical structure device (such as a diode or a heterojunction bipolar transistor of this configuration) in which the electrodes are often close to a mesa semiconductor step.
[0037]
(Embodiment 2)
In this embodiment, an example in which a step surface of a Schottky diode having a mesa structure is covered with a sidewall made of an organic insulator will be described with reference to a method different from that in Embodiment 1.
[0038]
i) First, as shown in FIG. 1A, a high impurity concentration ohmic junction forming semiconductor layer 102 and a low impurity concentration Schottky junction forming semiconductor layer 103 are formed on a semi-insulating substrate 101. A two-step mesa structure having a step shape is formed, and an ohmic electrode 104 having a predetermined thickness is formed at a predetermined position on the ohmic junction forming semiconductor layer 102.
[0039]
ii) Next, as shown in FIG. 1B, the precursor 106 to be changed into a predetermined organic insulator is applied in a film form to the whole area on the substrate 101 by a spin coating method. The steps up to here are exactly the same as those in the first embodiment.
[0040]
iii) Next, in this embodiment, sulfur hexafluoride (SF) ₆ ) And oxygen (O ₂ Anisotropic reactive ion etching is performed using a mixed gas. At this time, by adjusting the etching conditions and the etching time, a portion of the precursor 106 on the flat surface of the substrate 101, the semiconductor layers 102 and 103, and the electrode 104, as shown in FIG. While the step 106 of the semiconductor layer 102, the step surface 111 of the semiconductor layer 103, and the side surfaces 140 and 141 of the electrode 104 are left.
[0041]
Thereafter, heat treatment is performed at 250 ° C. to completely cure the precursor 106 and change it into an organic insulator. Thus, sidewalls 108, 109, and 110 made of an organic insulator are formed in a self-aligned manner on the step surface 107 of the semiconductor layer 102 and the side surfaces 140 and 141 of the electrode 104, respectively. At this time, the stepped surface 111 of the semiconductor layer 103 is covered with the sidewall 109 in common with the side surface 140 of the electrode 104.
[0042]
iv) Finally, as shown in FIG. 2A, an inorganic insulating film 112 made of silicon nitride is formed over the entire area of the substrate 101, and the Schottky junction forming semiconductor in the inorganic insulating film 112 is formed. An opening 151 is formed at a position corresponding to the flat surface 103 a of the layer 103. On top of this, a Schottky electrode material is vapor-deposited to a predetermined thickness, subjected to patterning and heat treatment, and has a predetermined thickness to make a Schottky contact with the underlying Schottky junction forming semiconductor layer 103. 113 is formed.
[0043]
In the Schottky diode manufactured as described above, the stepped surface 107 of the semiconductor layer 102 and the stepped surface 111 of the semiconductor layer 103 are covered with the sidewalls 108 and 109 made of organic insulators, respectively, so that the reliability is improved. . In addition, since there is no organic insulator on the flat surfaces 101a, 102a, and 103a of the substrate 101 and the semiconductor layers 102 and 103, warpage caused by the organic insulator can be suppressed. Therefore, no problem occurs during or after the wafer process.
[0044]
In addition, in this embodiment, since the reactive ion etching is performed before the precursor 106 is completely cured, the precursor is compared with the case where the reactive ion etching is performed after the precursor 106 is completely cured. The rate at which 106 is etched can be increased. Therefore, the etching rate ratio with the base substrate 101, the inorganic insulating film 105 on the substrate 101, the material of the wiring 104, or the like can be relatively increased. As a result, by adjusting the etching conditions and the etching time, damage to the base can be suppressed to a low level.
[0045]
(Embodiment 3)
In this embodiment, an example in which a stepped surface of a Schottky diode having a mesa structure is covered with a sidewall made of an organic insulator will be described using a method different from that in Embodiments 1 and 2.
[0046]
i) First, as shown in FIG. 1A, a high impurity concentration ohmic junction forming semiconductor layer 102 and a low impurity concentration Schottky junction forming semiconductor layer 103 are formed on a semi-insulating substrate 101. A two-step mesa structure having a step shape is formed, and an ohmic electrode 104 having a predetermined thickness is formed at a predetermined position on the ohmic junction forming semiconductor layer 102.
[0047]
ii) Next, as shown in FIG. 1B, the precursor 106 to be changed into a predetermined organic insulator is applied in a film form to the whole area on the substrate 101 by a spin coating method. The steps up to here are exactly the same as those in the first and second embodiments.
[0048]
iii) Next, dissolution with a solvent is performed. At this time, by adjusting the composition of the solvent and the dissolution time, the substrate 101, the semiconductor layers 102 and 103, and the electrodes 104 are present on the flat surfaces of the precursor 106 as shown in FIG. While removing the portion, the portions of the precursor 106 covering the step surface 107 of the semiconductor layer 102, the step surface 111 of the semiconductor layer 103, and the side surfaces 140 and 141 of the electrode 104 are left.
[0049]
Thereafter, heat treatment is performed at 250 ° C. to completely cure the precursor 106 and change it into an organic insulator. Thus, sidewalls 108, 109, and 110 made of an organic insulator are formed in a self-aligned manner on the step surface 107 of the semiconductor layer 102 and the side surfaces 140 and 141 of the electrode 104, respectively. At this time, the stepped surface 111 of the semiconductor layer 103 is covered with the sidewall 109 in common with the side surface 140 of the electrode 104.
[0050]
iv) Finally, as shown in FIG. 2A, an inorganic insulating film 112 made of silicon nitride is formed over the entire area of the substrate 101, and the Schottky junction forming semiconductor in the inorganic insulating film 112 is formed. An opening 151 is formed at a position corresponding to the flat surface 103 a of the layer 103. On top of this, a Schottky electrode material is vapor-deposited to a predetermined thickness, subjected to patterning and heat treatment, and has a predetermined thickness to make a Schottky contact with the underlying Schottky junction forming semiconductor layer 103. 113 is formed.
[0051]
In the Schottky diode manufactured as described above, the stepped surface 107 of the semiconductor layer 102 and the stepped surface 111 of the semiconductor layer 103 are covered with the sidewalls 108 and 109 made of organic insulators, respectively, so that the reliability is improved. . In addition, since there is no organic insulator on the flat surfaces 101a, 102a, and 103a of the substrate 101 and the semiconductor layers 102 and 103, warpage caused by the organic insulator can be suppressed. Therefore, no problem occurs during or after the wafer process.
[0052]
In addition, in this embodiment, since the precursor 106 is dissolved with a solvent, damage to the base can be suppressed as compared with the case where reactive ion etching is performed.
[0053]
In addition, when reactive ion etching is performed, the surface of the precursor (organic insulator) 106 itself may be altered, and electrical characteristics such as conductivity and dielectric constant may be deteriorated. In contrast, in this embodiment, since the precursor 106 is dissolved with a solvent, the deterioration of the electrical characteristics of the precursor (organic insulator) 106 is suppressed as compared with the case where reactive ion etching is performed. be able to.
[0054]
In addition, after apply | coating the above-mentioned precursor 106, before the process melt | dissolved with a solvent, you may perform preliminary heat processing at the temperature which the precursor 106 does not harden | cure completely. Thereby, the dissolving power with respect to the solvent of the precursor 106 can be dropped moderately, and the dissolution time can be easily controlled.
[0055]
In addition, after the precursor 106 is dissolved with a solvent, it is desirable to perform cleaning with another solvent (cleaning agent) having a low dissolving power before performing the original heat treatment at 250 ° C. Thereby, it is possible to reduce the reattachment of the piece of the precursor 106 once detached from the substrate 101 to the element on the substrate 101. In addition, when the piece of the precursor 106 once detached from the substrate 101 is reattached to the element on the substrate 101, reactive ion etching may be performed to remove the reattached material. Therefore, ashing (ashing) using oxygen plasma may be employed because etching is not performed. Thereby, damage to the base can be suppressed to a small level.
[0056]
(Embodiment 4)
In this embodiment, an example in which a step surface of a heterojunction bipolar transistor having a mesa structure is covered with a sidewall made of an organic insulator will be described.
[0057]
i) First, as shown in FIG. 3A, a three-step mesa structure having a sub-collector layer 203, a collector layer 205, a base layer 206, and an emitter layer 208 in a step shape is formed on a semi-insulating substrate 201. . Specifically, in this step, the subcollector layer 203, the collector layer 205, the base layer 206, and the emitter layer 208 are formed in this order by epitaxial growth over the entire area of the substrate 201. On this, an inorganic insulating film made of silicon nitride is formed as a mask, and the step of etching the epitaxial layer by a known method is performed three times to form an upper emitter layer 208, a lower base layer 206 and a collector layer 205, Further, pattern processing is performed so that the subcollector layer 203 in the lower layer gradually becomes wider in order. Thus, the flat surface 208a of the emitter layer 208, the step surface 209 of the emitter layer 208, the flat surface 206a of the base layer 206, the step surface 207 of the base layer 206 and the collector layer 205, the flat surface 203a of the subcollector layer 203, and the subcollector. The three-step mesa structure formed by the step surface 204 of the layer 203 and the flat surface 201a of the substrate 201 is formed. Note that the base layer 206 and the collector layer 205 are processed in the same pattern.
[0058]
Next, an emitter ohmic electrode 210, a base ohmic electrode 211, and a collector ohmic electrode 212 having a predetermined thickness are formed at predetermined positions on the emitter layer 208, the base layer 206, and the subcollector layer 203, respectively. , 211 and 212, an emitter wiring electrode 213, a base wiring electrode 214, and a collector wiring electrode 215 having a predetermined thickness are formed at predetermined positions, respectively. In this example, the thickness of each wiring electrode 213, 214, 215 was set to 1.5 μm, and the thickness of each ohmic electrode 210, 211, 212 was set sufficiently thinner than that. As will be described in detail later, the emitter ohmic electrode 210 and the emitter wiring electrode 213 occupy the entire area on the flat surface 208 a of the emitter layer 208.
[0059]
Thereafter, an inorganic insulating film 202 made of silicon nitride is formed over the entire area of the substrate 201. Note that, as described in connection with the first embodiment, it is often impossible to improve the water resistance of the element by using only the inorganic insulating film 202 made of silicon nitride.
[0060]
ii) Next, as shown in FIG. 3B, a precursor 216 to be changed into a predetermined organic insulator is applied in a film shape over the entire area of the substrate 201 by a spin coating method.
[0061]
Specifically, in this step, the precursor 216 is appropriately thinned with a solvent so as to reduce the viscosity, whereby the flat surfaces 201a, 203a, 206a of the substrate 201, the semiconductor layers 203, 206, and the electrodes 213, 214, 215 are obtained. , 213a, 214a, 215a are thinned, while the step surfaces 204, 207, 209 of the semiconductor layers 203, 205, 206, 208 and the side surfaces 240, 241, 242, 243, 244 of the electrodes 213, 214, 215 are viewed from above. It is applied so as to gradually become thicker at the bottom. In this example, as the precursor 216, as in the first embodiment, cycloten (trade name, manufactured by Dow Chemical Co., Ltd.) commercially available as a benzocyclobutene (BCB) group-containing compound was used. This was used as a solution of about 5%, and the spin coating conditions were set so that the film thickness was about 0.1 μm on the flat surface 201 a on the substrate 201.
[0062]
In this example, since the side surface 244 of the emitter wiring electrode 213 is positioned immediately above the step surface 209 of the emitter layer 208, the precursor 216 connects the side surface 244 of the emitter wiring electrode 213 and the step surface 209 of the emitter layer 208. Covered. Further, since the distance 227 between the side surface 243 of the base wiring electrode 214 and the step surface 207 of the base layer 206 and the collector layer 205 is set short, the height of the base wiring electrode 214 is set high. The precursor 216 covers the side surface 243 of the electrode 214, the base layer 206, and the stepped surface 207 of the collector layer 205 in a row. Similarly, the distance 229 between the side surface 241 of the collector wiring electrode 215 and the stepped surface 204 of the sub-collector layer 203 is set short, while the height of the collector wiring electrode 215 is set high. The side surface 241 and the stepped surface 204 of the subcollector layer 203 are continuously covered with the precursor 216. Accordingly, the step surface 209 of the emitter layer 208, the base layer 206, the step surface 207 of the collector layer 205, the step surface 204 of the subcollector layer 203, particularly the upper portions of these step surfaces can be reliably covered with the precursor 216. .
[0063]
iii) Next, a heat treatment is performed at 250 ° C. to completely cure the precursor 216 and change it into an organic insulator. After this, sulfur hexafluoride (SF ₆ ) And oxygen (O ₂ Anisotropic reactive ion etching is performed using a mixed gas. At this time, by adjusting the etching conditions and the etching time, as shown in FIG. 4, the portions of the organic insulator 216 that exist on the flat surfaces of the substrate 201, the semiconductor layers 203 and 206, and the electrodes 213, 214, and 215 On the other hand, the portion of the organic insulator 216 that covers the side surface 244 of the emitter wiring electrode 213 and the stepped surface 209 of the emitter layer 208, the portion that covers the side surface 242 of the base wiring electrode 214, and the side surface 243 of the base wiring electrode 214 are removed. And a portion covering and covering the step surface 207 of the base layer 206 and the collector layer 205 and a portion covering and covering the side surface 241 of the collector wiring electrode 215 and the step surface 204 of the sub-collector layer 203 are left. As a result, sidewalls 218, 220, 219, and 221 made of an organic insulator are formed in the respective locations in a self-aligning manner.
[0064]
Here, since the inorganic insulating film 202 covers a region where the organic insulator 216 is removed by etching, the underlying semiconductor active layer (emitter layer 208, base layer 206, collector layer 205, subcollector by reactive ion etching) is used. Damage to the layer 203) can be prevented. Further, the damage to the substrate 201 can be reduced by setting the etching time by the reactive ion etching as short as necessary.
[0065]
iv) Finally, an inorganic insulating film 217 made of silicon nitride is formed over the entire area of the substrate 201.
[0066]
In the heterojunction bipolar transistor thus fabricated, the step surface 209 of the emitter layer 208, the base layer 206, the step surface 207 of the collector layer 205, and the step surface 204 of the subcollector layer 203 are sidewalls each made of an organic insulator. Since it is covered with 218, 219, 221, the reliability increases. In addition, since there is no organic insulator on the flat surfaces 201a, 203a, 206a, 213a, 214a, and 215a of the substrate 201, the semiconductor layers 203 and 206, and the electrodes 213, 214, and 215, warping caused by the organic insulator is caused. Can be suppressed. Therefore, no problem occurs during or after the wafer process. In other words, since there is no stress in the planar direction, the wafer warps during the process, the organic insulator and other parts crack, and the element warps even when it is separated for each element (chip) at the scribe line part. Will not occur.
[0067]
Furthermore, according to the manufacturing method described above, the side walls 218, 219, and 221 are self-aligned with the step surface 209 of the emitter layer 208, the step surface 207 of the base layer 206, the collector layer 205, and the step surface 204 of the subcollector layer 203, respectively. As a result, the sidewalls are finished to a uniform width. Therefore, the strength of the sidewalls 218, 219, and 221 made of an organic insulator can be increased and stabilized.
[0068]
When the precursor 216 is applied, the precursor 216 may continuously cover the side surface 240 of the collector wiring electrode 215 and the step surface 207 of the base layer 206 and the collector layer 205. In that case, the side surface 240 of the collector wiring electrode 215 is also covered with a sidewall made of an organic insulator.
[0069]
The planar pattern layout of the manufactured Schottky diode is as shown in FIG. 5 (note that FIG. 4 described above corresponds to a cross section taken along line 222 in FIG. 5). The pattern of the emitter layer 208 and the emitter wiring electrode 213 (and the emitter ohmic electrode 210) thereon is a rectangular shape elongated in the vertical direction in FIG. The emitter wiring 224E extends from the end of the emitter wiring electrode 213 (lower end in FIG. 5) continuously to the left and right sides in FIG. 5 with a constant width wider than the width of the emitter wiring electrode 213, and reaches the element peripheral portion 223E. Yes.
[0070]
The pattern of the base layer 206 (and the collector layer 205) is a rectangular shape wider than the pattern of the emitter layer 208. The pattern of the base wiring electrode 214 (and the base ohmic electrode 210) is a long and narrow rectangular shape extending in parallel with the emitter wiring electrode 213 at the surface of the base layer 206 that protrudes on both sides of the emitter layer 208. Yes. The base wiring 224B continuously extends upward in FIG. 5 with a constant width wider than the width of the base wiring electrode 214 from the end portions (upper ends in FIG. 5) of the pair of base wiring electrodes 214, and the element peripheral portion 223B. Has reached.
[0071]
The pattern of the subcollector layer 203 is a rectangular shape wider than the base layer 206. The pattern of the collector wiring electrode 215 (and the collector ohmic electrode 212) is such that the surface of the portion of the subcollector layer 203 that protrudes on both sides of the base layer 206 is an elongated substantially rectangular shape that extends parallel to the base wiring electrode 214. Has been. The collector wiring 224C extends continuously downward from the end of the pair of collector wiring electrodes 215 (the lower end in FIG. 5) with a constant width wider than the width of the collector wiring electrode 215 in the element peripheral portion 223C. Has reached.
[0072]
Note that portions of the emitter wiring 224E, the base wiring 224B, and the collector wiring 224C that exceed the step surfaces 209, 207, and 204 forming the mesa structure are aerial wiring. Therefore, when the precursor 216 is applied, the precursor (organic insulator) 216 is also filled immediately below that portion. Moreover, since the aerial wiring exists, the precursor 216 reliably covers the step surfaces 209, 207, and 204, particularly the upper portion of the step surface, thanks to the surface tension of the precursor 216. Therefore, the entire circumference of the step surfaces 209, 207, and 204 forming the mesa structure can be reliably covered with the sidewalls 218, 219, and 221, and the reliability of the element can be reliably increased.
[0073]
In the present embodiment, the stepped surface of the mesa structure of the heterojunction bipolar transistor is protected by the side wall made of an organic insulator. However, the present invention is not limited to this. The present invention can be applied to the protection of step surfaces of various types of semiconductor elements.
[0074]
For example, the structure of the present embodiment in which an electrode is formed on a flat surface continuous with the upper edge of the step surface and the precursor is continuously covered with the side surface of the electrode and the step surface is a heterojunction bipolar. In addition to a transistor, the present invention can be similarly applied to a diode or a semiconductor step of a field effect transistor, and further to a resistance element formed by a mesa structure.
[0075]
In particular, in this configuration, since the electrode is formed on the mesa step close to the mesa step, the structure is more effective in a structure in which the step and the wiring electrode are formed in parallel in a fine element region like a heterojunction bipolar transistor. Demonstrate the effect.
[0076]
(Embodiment 5)
In this embodiment, an example in which a step surface of a field effect transistor having a mesa structure is covered with a sidewall made of an organic insulator will be described.
[0077]
i) First, as shown in the cross-sectional view of FIG. 6A, a one-stage mesa structure including a channel layer of a field effect transistor is formed on a semi-insulating substrate 301.
[0078]
Specifically, it is formed by epitaxial growth having a multilayer structure of a buffer layer, a channel layer for generating a two-dimensional electron gas channel, a donor layer, a Schottky layer, and a cap layer over the entire region of the substrate 301. The semiconductor layer 302 is etched and patterned by a known method. Thus, the one-step mesa structure formed by the flat surface 301a of the substrate 301, the step surface 305 of the semiconductor layer 302, and the flat surface 302a of the semiconductor layer 302 is formed.
[0079]
When viewed in a plan view, the pattern of the semiconductor layer 302 has a U-shape that opens downward in the figure as shown in FIG. 6B (note that FIG. 6A shows FIG. 6). (This corresponds to a cross section taken along line 303 in (b).)
[0080]
Next, as shown in FIG. 6B, a pair of source electrode 306, drain electrode 307, gate electrode 308, and gate electrode lead-out wiring 310 are formed on the substrate 301.
[0081]
Specifically, first, a source electrode 306 and a drain electrode 307 are formed. Each pattern of the source electrode 306 covers the side portion 320 of the semiconductor layer 302. The pattern of the drain electrode 307 covers the central portion 321 of the semiconductor layer 302 and is separated from the source electrode 306 by a certain distance. Next, a recess groove 330 is formed in a region corresponding to the gap between the source electrode 306 and the drain electrode 307 in a portion (side portion) 320 corresponding to two sides of the semiconductor layer 302 (a cap layer (not shown) is recessed etched). And expose the Schottky layer.) A gate electrode material that forms a Schottky junction is deposited on the recess groove 330 to form the gate electrode 308. The pattern of the gate electrode 308 is elongated in the horizontal direction in FIG. 6B with a small distance from the source electrode 306 and the drain electrode 307. As a result, as shown in FIG. 6C (as viewed from the right side in FIG. 6B), the gap between the source electrode 306 and the drain electrode 307 is recessed by the recess groove 330. It has become. That is, a step surface 315 (see FIG. 7B) of the semiconductor layer 302 is generated there.
[0082]
ii) Next, as shown in FIG. 1B, a precursor 309 to be changed into a predetermined organic insulator is applied in a film shape over the entire area of the substrate 301 by a spin coating method.
[0083]
Specifically, in this step, the precursor 309 is appropriately thinned with a solvent so as to reduce the viscosity, whereby the flat surfaces 301a, 302a, 306a, 307a of the substrate 301, the semiconductor layer 302, and the electrodes 306, 307, 310 are obtained. , 310a, while being thinned, it is applied so as to gradually become thicker from the top to the bottom of the step surface 305 of the semiconductor layer 302 and the side surfaces 341, 342, 343 of the electrodes 306, 307, 310. At this time, the recess groove 330 is also completely filled with the precursor 309. In this example, as the precursor 309, as in the first embodiment, a cycloten commercially available as a benzocyclobutene (BCB: benzocyclobutene) group-containing compound (trade name, manufactured by Dow Chemical Company) was used. This was used as a 5% solution, and spin coating conditions were set so that the film thickness was about 0.1 μm on the flat surface 301 a on the substrate 301.
[0084]
iii) Next, heat treatment is performed at 250 ° C. to completely cure the precursor 309 and change it into an organic insulator. After this, sulfur hexafluoride (SF ₆ ) And oxygen (O ₂ Anisotropic reactive ion etching is performed using a mixed gas. At this time, by adjusting the etching conditions and the etching time, the substrate 301, the semiconductor layer 302, and the electrodes 306, 307, 310 of the organic insulator 309 are adjusted as shown in FIGS. A portion of the organic insulator 309 covering the step surface 305 of the semiconductor layer 302, the side surfaces 341, 342, 343 of the electrodes 306, 307, 310, and the step surface 315 in the recess groove 330 while removing the portion existing on the flat surface. Leave. As a result, the side walls 312, 313, made of organic insulators are respectively self-aligned with the step surface 305 of the semiconductor layer 302, the side surfaces 341, 342, 343 of the electrodes 306, 307, 310 and the step surface 315 in the recess groove 330. 314, 319, 312 'are formed. In FIG. 7B, the gate electrode 308 is not shown in order to represent the step surface 315 in the recess groove 330.
[0085]
iv) Finally, an inorganic insulating film 311 made of silicon nitride is formed over the entire area of the substrate 301.
[0086]
In the field effect transistor thus fabricated, the step surface 305 of the semiconductor layer 302, the side surfaces 341, 342, and 343 of the electrodes 306, 307, and 310, and the step surface 315 in the recess groove 330 are each a side made of an organic insulator. Since it is covered with the walls 312, 313, 314, 319, 312 ', the reliability is improved. In particular, the exposed portion of the step surface 305 of the semiconductor layer 302 between the source electrode 306 and the drain electrode 307 and the step surface 315 in the recess groove 330 can be covered with an organic insulator, so that reliability is ensured. Can be increased.
[0087]
In addition, since there is no organic insulator on the flat surfaces 301a, 302a, 306a, 307a, and 310a of the substrate 301, the semiconductor layer 302, and the electrodes 306, 307, and 310, warping caused by the organic insulator can be suppressed. Therefore, no problem occurs during or after the wafer process. In other words, since there is no stress in the planar direction, the wafer warps during the process, the organic insulator and other parts crack, and the element warps even when it is separated for each element (chip) at the scribe line part. Will not occur.
[0088]
Furthermore, according to the manufacturing method described above, the side surfaces 312, 313, 314, 319 are formed on the step surface 305 of the semiconductor layer 302, the side surfaces 341, 342, 343 of the electrodes 306, 307, 310, and the step surface 315 in the recess groove 330. , 312 'are formed in a self-aligned manner, so that the side walls are finished to a uniform width. Therefore, the strength of the side walls 312, 313, 314, 319, 312 'made of an organic insulator can be increased and stabilized.
[0089]
In this embodiment, the step surface of the mesa structure of the field effect transistor is protected by the side wall made of an organic insulator, but the present invention is not limited to this. The present invention can be applied to the protection of step surfaces of various types of semiconductor elements.
[0090]
For example, in the present embodiment, a configuration in which a side wall made of an organic insulator is formed along the side wall of an electrode formed continuously from the upper part to the lower part of the semiconductor step, and the step surface is protected by the side wall, In addition to the field effect transistor, the present invention can be similarly applied to a semiconductor step of a mesa structure of a diode or a heterojunction bipolar transistor or a resistance element formed by a mesa structure. In addition, the electrode may have an aerial wiring shape, and a portion crossing a mesa step on the side wall of the aerial wiring portion 224 in the fourth embodiment corresponds to that.
[0091]
In particular, this configuration has an advantage that the stepped surface of the portion where the electrode cannot be disposed above and below the step can be more reliably protected. Therefore, the present invention can be effectively applied to a semiconductor step exposed from a gap between a plurality of different wirings. In this case, when the electrodes are opposed to each other as in the present configuration, there is an advantage that the stepped surface therebetween can be protected more reliably.
In Embodiments 2 to 4, reference is not made to the eaves element 114 shown in FIGS. 1B and 2B, but naturally the eaves element 114 is also used in each embodiment. The precursor can be stored directly under the eaves element. As a result, the sidewall can be formed thicker according to the projection amount of the eaves element, and therefore the reliability of the semiconductor device can be further improved.
[0092]
(Modification common to Embodiments 1 to 5)
In Embodiments 1 to 5 described above, a cured product of a resin composition containing a benzocyclobutene group-containing compound is used as the organic insulator. As this benzocyclobutene group-containing compound, various compounds such as a monomer type having a benzocyclobutene group in the molecule and a partial reactant type such as an oligomer or a polymer can be used.
[0093]
In addition, since these materials have organosiloxane crosslinks and naphthalene rings in the molecule, the heat resistance is improved, so that they can be easily used in a semiconductor process and have a higher protective effect. Among them, a polyorganosiloxane crosslinked bisbenzocyclobutene monomer (Japanese Patent Laid-Open No. 1-197491), a composition comprising arylcyclobutene, and a polymer composition produced therefrom (Japanese Patent Laid-Open No. 63-501157). Gazette) or oligomers thereof are more preferred.
[0094]
Benzocyclobutene resin (polymer) is an organic material having a low dielectric constant, and has a low dielectric constant of about 2.7.
[0095]
In the present invention, since the organic insulator is formed on the side wall of the portion where electrolysis concentrates, such as the semiconductor element portion and the wiring portion, the organic insulator preferably has a low dielectric constant.
[0096]
In that aspect, in addition to benzocyclobutene resin (polymer), it is possible to use a material having a low dielectric constant, such as organic SOG (Spin On Glass, relative dielectric constant of about 3 to 3.5), polyaryl ether, Heat-resistant resin such as polyimide (relative dielectric constant of about 3 to 3.5), fluorinated polyimide (relative dielectric constant of about 2.7), flare (Flear, trade name), parylene fluoride (AF-4, trade name, Relative permittivity about 2.4), Cytop (trade name, relative permittivity 2.1), fluorinated polyaryl ether (relative permittivity 2.6), Teflon (trade name, relative permittivity 2.1-1) .9), fluorocarbon resins such as fluorinated amorphous carbon can also be used.
[0097]
However, benzocyclobutene resin (polymer) has a low water absorption of about one-tenth compared to polyimide resin, so that when used as a surface protective film, the effect of improving the moisture resistance of the semiconductor device is large and more preferable.
[0098]
In the above embodiment, an example of a material that forms an organic insulating film from a precursor by thermal curing is given. However, in addition to thermal curing, an organic insulating material that is cured by ultraviolet irradiation or the like should be used. You can also.
[0099]
In general, many organic insulators have low resistance to oxygen, and when heated in the air, they are significantly deteriorated even at a temperature of 100 ° C. to 200 ° C., and electrical characteristics such as dielectric constant and electrical conductivity. May change. In particular, when a resist removal process using oxygen plasma, which is usually used in a semiconductor process, is performed, significant unevenness may occur on the surface of the organic insulator. In the conventional structure, since the organic insulator is formed on the entire surface of the element or wafer, a process of exposing the organic insulator inevitably occurs, and the processing temperature is inevitably lowered than usual, or the resist of the above-described oxygen plasma is used. Since removal of the residue is omitted, it has been a factor of reducing the manufacturing yield of the element. Alternatively, in order to prevent deterioration of the organic insulating film due to oxygen, when an inorganic insulating film is formed on the surface of the organic insulating film formed on the entire surface, stress due to the difference in thermal expansion coefficient between the organic insulating film and the inorganic insulating film is locally concentrated. In many cases, the inorganic insulating film breaks, and this is also a factor in reducing the product yield.
[0100]
On the other hand, in the present invention, as shown in FIG. 4, the organic insulator is covered by covering the whole with an inorganic insulating film, and the next formation of the Schottky electrode can be performed without exposing the organic insulator. Yes. In other words, by forming the organic insulator only on the stepped surface, there is no organic insulating film in most places on the wiring. Therefore, after coating with the inorganic insulating film, the organic insulator is not exposed and the next A process can be performed.
[0101]
Although not mentioned in the above description, actually, a process of drawing a wiring from a Schottky electrode or an ohmic electrode, or a process of forming a thicker wiring on the wiring to reduce the wiring resistance, A step of connecting and configuring a circuit, a step of forming a scribe line, a step of cutting out from a wafer, separating each element, and mounting on a package or the like are performed. In these steps, the structure of the present invention can be similarly performed without exposing the organic insulator.
[0102]
(Embodiment 6)
In this embodiment, an example of an antenna-integrated radio communication circuit device including the semiconductor devices of Embodiments 1 to 5 will be described.
[0103]
As shown in FIG. 8, the wireless communication circuit device of the present embodiment forms an IC (integrated circuit chip) 401A constituting a wireless transmission circuit device mounted side by side on a ceramic substrate 402, and a wireless reception circuit device. IC 401B. These ICs 401 </ b> A and 401 </ b> B are covered with a metal cover 405 that is bonded to a ceramic substrate 402 with a resin adhesive 406. An antenna 407 is integrally provided on the back surface of the substrate. In particular, in ultra-high frequency communication from 30 GHz to 90 GHz, such an antenna-integrated configuration is required in order to avoid transmission loss due to a cable.
[0104]
The IC 401A constituting the wireless transmission circuit device multiplies the local signal, inputs it to the mixer, converts the frequency of the input signal from 1 GHz to 3 GHz into a millimeter wave band from 60 GHz to 64 GHz, amplifies it by an amplifier circuit, and an antenna on the back side of the substrate 407 to transmit. The IC 401B constituting the wireless reception circuit device receives a radio signal in the millimeter wave band from 60 GHz to 64 GHz by the antenna 407 on the back surface of the substrate, amplifies it by the amplifier circuit, and 1 GHz by the mixer circuit to which the multiplied local signal is input. Is converted to a 3 GHz signal and output.
[0105]
The ICs 401A and 401B include the semiconductor devices manufactured in the first to fifth embodiments, respectively. In manufacturing these ICs 401A and 401B, an input / output circuit connected to each electrode of the semiconductor device is formed on a semiconductor substrate, an amplifier circuit using HBT or FET, a local oscillator, and a signal multiplier circuit for multiplying a local signal frequency. Each of the diode mixer circuits is configured. Such a semiconductor substrate is polished to a thickness of 50 μm, gold-tin alloys 403A and 403B are vapor-deposited on the back surface, and cut with a scribe line. In this way, ICs 401A and 401B in the form of chips are obtained.
[0106]
When mounting the ICs 401A and 401B, a gold-tin alloy 403A and 403B on the back surface of each IC is brought into contact with a gold circuit pattern (not shown) on the ceramic substrate 402, and heating is performed at 250 ° C. or higher to join the two. To do. Next, electrode pads (not shown) on the surfaces of the ICs 401 </ b> A and 401 </ b> B and a circuit pattern made of gold on the ceramic substrate 402 are wired by bonding wires 404. Thereafter, a metal cover 405 is attached to the ceramic substrate 402 with a resin adhesive 406 to seal the ICs 401A and 401B.
[0107]
In this antenna-integrated wireless communication circuit device, since the ICs 401A and 401B are configured using the semiconductor devices of the first to fifth embodiments, the water resistance of the ICs 401A and 401B is increased. Therefore, sealing with the resin adhesive 406 as described above and a resin package can be used. Therefore, the manufacturing cost can be reduced. Conventionally, since the water resistance of the element was insufficient, it was necessary to perform hermetic sealing of the package with molten metal, which was expensive.
[0108]
Further, since the gold-tin alloy is used for joining the IC 401A, 401B and the ceramic substrate 402, heat is easily transmitted from the IC 401A, 401B to the ceramic substrate 402. Therefore, the temperature rise of the ICs 401A and 401B can be suppressed, and the apparatus can operate without a long time failure.
[0109]
Further, in this wireless communication circuit device integrated with an antenna, the ICs 401A and 401B are configured using the semiconductor devices of the first to fifth embodiments, so that the ICs 401A and 401B are mounted on the ceramic substrate 402 and the gold-tin alloy 403A. , 403B, when heating and bonding at 250 ° C. or higher, the element does not deteriorate due to the organic insulator. Therefore, the yield at the time of mounting can be improved and the manufacturing cost can be further reduced. On the other hand, in the structure in which the organic insulator is formed on the entire surface of the element as in the prior art, the inorganic insulating film may be cracked and deteriorated due to the thermal expansion of the organic insulator. As a result, the manufacturing cost increased.
[0110]
【The invention's effect】
As is clear from the above, according to the method for manufacturing a semiconductor device of the present invention, the stepped surface, which is an element of the stepped structure, is covered with the sidewall made of an organic insulator. Increased reliability. Moreover, on the first and second flat surfaces connected to the lower edge and the upper edge of the step surface, there is substantially no organic insulator except for the portion immediately below the eaves element. Warping can be suppressed. Therefore, no problem occurs during or after the wafer process. Therefore, the yield can be improved and the manufacturing cost can be reduced. Moreover, in this method of manufacturing a semiconductor device, when the precursor is applied, the precursor accumulates in a space surrounded by the eaves element, the step surface, and the first flat surface due to the surface tension of the precursor. . As a result, the sidewall is formed thick according to the projection amount of the eaves element. Therefore, the reliability of the semiconductor device is further increased.
[Brief description of the drawings]
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a Schottky diode according to an embodiment of the present invention.
FIG. 2 is a view showing a cross section and a planar pattern layout of a Schottky diode manufactured by the above manufacturing method.
FIG. 3 is a process cross-sectional view illustrating a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a heterojunction bipolar transistor manufactured by the above manufacturing method.
FIG. 5 is a diagram showing a planar pattern layout of a heterojunction bipolar transistor manufactured by the above manufacturing method.
FIG. 6 is a diagram illustrating a method for manufacturing a field effect transistor according to one embodiment of the present invention.
FIG. 7 is a diagram showing a field effect transistor manufactured by the above manufacturing method.
[Fig. 8] Consists of semiconductor devices manufactured by the above manufacturing methods It is a figure which shows the structure of a radio | wireless communication circuit apparatus.
FIG. 9 is a diagram illustrating a conventional technique for coating a semiconductor element with an organic insulator.
[Explanation of symbols]
102 Semiconductor layer for forming ohmic junction
103 Semiconductor layer for forming a Schottky junction
104 Ohmic electrode
106,216,309 precursor
107, 111, 204, 207, 209, 305, 315 Step surface
108, 109, 110, 218, 219, 220, 221, 312, 312 ', 313, 314 Sidewall made of organic insulator
114 eaves element
203 Subcollector layer
205 Collector layer
206 Base layer
208 Emitter layer
213 Emitter wiring electrode
214 Base wiring electrode
215 Collector wiring electrode
302 Semiconductor layer
401A, 401B IC

Claims (3)

On the surface side, a stepped structure including a step surface, a first flat surface continuing to the lower edge of the step surface, and a second flat surface continuing to the upper edge of the step surface, and the step from the second flat surface Applying a precursor to a predetermined organic insulator having a predetermined viscosity on a semiconductor substrate having an eaves element protruding laterally beyond the upper edge of the surface;
Curing the precursor to change to the organic insulator;
Reactive ion etching is performed to remove portions of the organic insulator that are present on the first and second flat surfaces, while covering the stepped surface under the eaves element of the organic insulator. Forming a sidewall that leaves a precursor, and a method for manufacturing a semiconductor device. On the surface side, a stepped structure including a step surface, a first flat surface continuing to the lower edge of the step surface, and a second flat surface continuing to the upper edge of the step surface, and the step from the second flat surface Applying a precursor to a predetermined organic insulator having a predetermined viscosity on a semiconductor substrate having an eaves element protruding laterally beyond the upper edge of the surface;
Reactive ion etching is performed to remove portions of the precursor existing on the first and second flat surfaces, and the precursor covering the stepped surface under the eaves element of the organic insulator. Forming a sidewall that leaves a body;
And a step of curing the precursor forming the sidewall to change to the organic insulator. On the surface side, a stepped structure including a step surface, a first flat surface continuing to the lower edge of the step surface, and a second flat surface continuing to the upper edge of the step surface, and the step from the second flat surface Applying a precursor to a predetermined organic insulator having a predetermined viscosity on a semiconductor substrate having an eaves element protruding laterally beyond the upper edge of the surface;
Dissolving with a solvent to remove portions of the precursor existing on the first and second flat surfaces, while covering the stepped surface under the eaves element of the organic insulator. Forming a sidewall that leaves
And a step of curing the precursor forming the sidewall to change to the organic insulator.

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