JP2016085999A - Nitride semiconductor device - Google Patents

Nitride semiconductor device Download PDF

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JP2016085999A
JP2016085999A JP2013031975A JP2013031975A JP2016085999A JP 2016085999 A JP2016085999 A JP 2016085999A JP 2013031975 A JP2013031975 A JP 2013031975A JP 2013031975 A JP2013031975 A JP 2013031975A JP 2016085999 A JP2016085999 A JP 2016085999A
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insulating film
gate electrode
nitride semiconductor
electrode
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敬久 藤井
Yoshihisa Fujii
敬久 藤井
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    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor device capable of effectively suppressing electric field concentration at an end of a gate field plate part, and improving off-state withstand voltage.SOLUTION: A gate electrode 13 includes a base part 13a Schottky-coupled to the uppermost layer of a nitride semiconductor layer 10, and a gate field plate part 13b extending on a first insulating film 14 from an upper part of the base part 13a toward the drain electrode 12 side. A source electrode 11 includes a source field plate part 21 extending on an interlayer insulating film 16 toward the drain electrode 12 side so as to cover the gate electrode 13. A second insulating film 15 is formed at least on the first insulating film 14 and the gate electrode 13. An interlayer insulating film 16 made of a material containing at least SiOis formed on the second insulating film 15. The dielectric constant of the second insulating film 15 is set higher than the dielectric constant of the interlayer insulating film 16.SELECTED DRAWING: Figure 1

Description

この発明は、窒化物半導体装置に関し、詳しくは、窒化物半導体層上にソース電極とドレイン電極およびゲート電極が形成された窒化物半導体装置に関する。   The present invention relates to a nitride semiconductor device, and more particularly to a nitride semiconductor device in which a source electrode, a drain electrode, and a gate electrode are formed on a nitride semiconductor layer.

従来の第１の窒化物半導体装置としては、ゲート電極にフィールドプレート部を形成することにより、ゲート電極端の電界強度を緩和するものがある(例えば、特開２００４−２００２４８号公報(特許文献１)参照)。   As a conventional first nitride semiconductor device, there is one in which a field plate portion is formed in a gate electrode to reduce the electric field strength at the gate electrode end (for example, Japanese Patent Application Laid-Open No. 2004-200248 (Patent Document 1). )reference).

また、従来の第２の窒化物半導体装置としては、ゲート電極とドレイン電極との間のパッシベーション膜の上に、パッシベーション膜よりも誘電率の高い高誘電率膜を形成することで、ゲート電極端への電界集中を緩和するものがある(例えば、特開２０１１−２０４７８０号公報(特許文献２)参照)。   Further, as a conventional second nitride semiconductor device, a gate electrode terminal is formed by forming a high dielectric constant film having a dielectric constant higher than that of the passivation film on the passivation film between the gate electrode and the drain electrode. There is one that relieves the electric field concentration on the surface (for example, see Japanese Patent Application Laid-Open No. 2011-204780 (Patent Document 2)).

特開２００４−２００２４８号公報JP 2004-200248 A 特開２０１１−２０４７８０号公報JP 2011-204780 A

ところで、上記従来の第１の窒化物半導体装置では、ゲート電極のフィールドプレート部の端での電界集中により、所望のオフ耐圧まで保たないという問題がある。ここで、オフ耐圧は、例えばノーマリオンのＧａＮ系ＨＦＥＴにおいて、ゲート電極に−１０Ｖを印加し続けているオフ状態において、ソース電極に０Ｖを印加すると共にドレイン電極に印加する電圧が何ボルトのときに絶縁破壊に至るのかを表す。   However, the first conventional nitride semiconductor device has a problem that the desired off breakdown voltage cannot be maintained due to the electric field concentration at the end of the field plate portion of the gate electrode. Here, for example, in a normally-on GaN-based HFET, the off-breakdown voltage is 0 V applied to the source electrode and the voltage applied to the drain electrode in an off state in which −10 V is continuously applied to the gate electrode. Represents the dielectric breakdown.

また、上記従来の第２の窒化物半導体装置では、ゲート電極のフィールドプレート部が無いため、ゲート電極端に電界が集中して、ゲートリーク電流が増大すると共に、オフ耐圧が所望の電圧まで保たないという問題がある。   In the second conventional nitride semiconductor device, since there is no field plate portion of the gate electrode, the electric field is concentrated on the gate electrode end, the gate leakage current increases, and the off breakdown voltage is maintained at a desired voltage. There is a problem of not.

そこで、この発明の課題は、ゲートフィールドプレート部の端での電界集中を効果的に抑制でき、オフ耐圧を向上できる窒化物半導体装置を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a nitride semiconductor device capable of effectively suppressing electric field concentration at the end of a gate field plate portion and improving off breakdown voltage.

上記課題を解決するため、この発明の窒化物半導体装置は、
窒化物半導体層と、
上記窒化物半導体層上に、または、上記窒化物半導体層内に少なくとも一部が形成されると共に、互いに間隔をあけて配置されたソース電極およびドレイン電極と、
上記ソース電極と上記ドレイン電極との間かつ上記窒化物半導体層上に形成されたゲート電極と、
上記ソース電極と上記ゲート電極との間および上記ドレイン電極と上記ゲート電極との間で上記窒化物半導体層上に形成された第１の絶縁膜と、
少なくとも上記第１の絶縁膜上および上記ゲート電極上に形成された第２の絶縁膜と、
上記第２の絶縁膜上に形成され、少なくともＳiＯ２を含む材料からなる層間絶縁膜と
を備え、
上記ゲート電極は、上記窒化物半導体層の最上層とショットキー接合された基部と、その基部の上部から上記ドレイン電極側に向かって上記第１の絶縁膜上に延在するゲートフィールドプレート部とを有すると共に、
上記ソース電極は、上記ゲート電極を覆うように上記ドレイン電極側に向かって上記層間絶縁膜上に延在するソースフィールドプレート部を有し、
上記第２の絶縁膜の誘電率は、上記層間絶縁膜の誘電率よりも高いことを特徴とする。 In order to solve the above problems, a nitride semiconductor device of the present invention is
A nitride semiconductor layer;
A source electrode and a drain electrode which are formed on the nitride semiconductor layer or in the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
A first insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
A second insulating film formed on at least the first insulating film and the gate electrode;
An interlayer insulating film formed on the second insulating film and made of a material containing at least SiO 2 ;
The gate electrode includes a base portion that is Schottky-bonded to the uppermost layer of the nitride semiconductor layer, a gate field plate portion that extends on the first insulating film from the upper portion of the base portion toward the drain electrode side, and And having
The source electrode has a source field plate portion extending on the interlayer insulating film toward the drain electrode so as to cover the gate electrode,
The dielectric constant of the second insulating film is higher than the dielectric constant of the interlayer insulating film.

また、一実施形態の窒化物半導体装置では、
上記第２の絶縁膜の誘電率が５以上である。 In the nitride semiconductor device of one embodiment,
The dielectric constant of the second insulating film is 5 or more.

また、一実施形態の窒化物半導体装置では、
上記第２の絶縁膜の膜厚が３０ｎｍ以上である。 In the nitride semiconductor device of one embodiment,
The film thickness of the second insulating film is 30 nm or more.

以上より明らかなように、この発明によれば、ソース電極とゲート電極との間およびドレイン電極とゲート電極との間で窒化物半導体層上に第１の絶縁膜を形成し、その第１の絶縁膜およびゲート電極上に層間絶縁膜の誘電率よりも誘電率が高い第２の絶縁膜を形成することによって、ゲートフィールドプレート部の端での電界集中を効果的に抑制でき、オフ耐圧を向上できる窒化物半導体装置を実現することができる。   As apparent from the above, according to the present invention, the first insulating film is formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode. By forming a second insulating film having a dielectric constant higher than that of the interlayer insulating film on the insulating film and the gate electrode, electric field concentration at the edge of the gate field plate portion can be effectively suppressed, and the off breakdown voltage can be reduced. An improved nitride semiconductor device can be realized.

図１はこの発明の第１実施形態の窒化物半導体装置の一例としてのＧａＮ系ＨＦＥＴの断面図である。FIG. 1 is a cross-sectional view of a GaN-based HFET as an example of a nitride semiconductor device according to the first embodiment of the present invention. 図２は上記ＧａＮ系ＨＦＥＴの要部の拡大断面図である。FIG. 2 is an enlarged cross-sectional view of the main part of the GaN-based HFET. 図３は第１比較例のＧａＮ系ＨＦＥＴの要部の拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a main part of the GaN-based HFET of the first comparative example. 図４は第２比較例のＧａＮ系ＨＦＥＴの要部の拡大断面図である。FIG. 4 is an enlarged cross-sectional view of a main part of the GaN-based HFET of the second comparative example. 図５は上記ＧａＮ系ＨＦＥＴのゲート電極端の電界強度を説明するための断面図である。FIG. 5 is a cross-sectional view for explaining the electric field strength at the gate electrode end of the GaN-based HFET. 図６はゲート電極カバー絶縁膜の誘電率に対するゲート電極端の電界強度のシミュレーション結果を示す図である。FIG. 6 is a diagram showing a simulation result of the electric field strength at the gate electrode end with respect to the dielectric constant of the gate electrode cover insulating film. 図７は上記電界強度のシミュレーションの条件を示す図である。FIG. 7 is a diagram showing conditions for the simulation of the electric field strength. 図８はゲート電極カバー絶縁膜の誘電率に対するゲートフィールドプレート部の端の電界強度の緩和率のシミュレーション結果を示す図である。FIG. 8 is a diagram showing a simulation result of the relaxation rate of the electric field strength at the end of the gate field plate portion with respect to the dielectric constant of the gate electrode cover insulating film. 図９はゲート電極カバー絶縁膜(誘電率４)の膜厚に対するゲートフィールドプレート部の端の電界強度のシミュレーション結果を示す図である。FIG. 9 is a diagram showing a simulation result of the electric field strength at the end of the gate field plate portion with respect to the film thickness of the gate electrode cover insulating film (dielectric constant 4). 図１０はゲート電極カバー絶縁膜(誘電率２０)の膜厚に対するゲートフィールドプレート部の端の電界強度のシミュレーション結果を示す図である。FIG. 10 is a diagram showing a simulation result of the electric field strength at the end of the gate field plate portion with respect to the film thickness of the gate electrode cover insulating film (dielectric constant 20). 図１１はこの発明の第２実施形態の窒化物半導体装置の一例としてのＧａＮ系ＨＦＥＴの断面図である。FIG. 11 is a cross-sectional view of a GaN-based HFET as an example of a nitride semiconductor device according to the second embodiment of the present invention.

以下、この発明の窒化物半導体装置を図示の実施の形態により詳細に説明する。   The nitride semiconductor device of the present invention will be described in detail below with reference to the illustrated embodiments.

〔第１実施形態〕
図１はこの発明の第１実施形態の窒化物半導体装置の一例としてのノーマリーオンタイプのＧａＮ系ＨＦＥＴの断面図を示し、図２は上記ＧａＮ系ＨＦＥＴの要部の拡大断面図を示している。 [First Embodiment]
FIG. 1 shows a sectional view of a normally-on type GaN-based HFET as an example of the nitride semiconductor device according to the first embodiment of the present invention, and FIG. 2 shows an enlarged sectional view of the main part of the GaN-based HFET. Yes.

この第１実施形態のＧａＮ系ＨＦＥＴは、図１,図２に示すように、Ｓi基板(図示せず)上に形成された窒化物半導体層１０と、窒化物半導体層１０上に形成され、互いに間隔をあけて配置されたＴi／Ａlからなるソース電極１１,ドレイン電極１２と、ソース電極１１とドレイン電極１２との間かつ窒化物半導体層１０上に形成されたＷＮ／ＷまたはＴiＮからなるゲート電極１３とを備えている。   As shown in FIGS. 1 and 2, the GaN-based HFET of the first embodiment is formed on a nitride semiconductor layer 10 formed on a Si substrate (not shown), and on the nitride semiconductor layer 10. Ti / Al source electrode 11, drain electrode 12, and WN / W or TiN formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor layer 10 are spaced apart from each other. And a gate electrode 13.

上記窒化物半導体層１０は、Ｓi基板(図示せず)上に順に形成されたアンドープＧaＮ層１とアンドープＡlＧaＮ層２で構成されている。このアンドープＧaＮ層１とアンドープＡlＧaＮ層２との界面に２ＤＥＧ(２次元電子ガス)が発生する。   The nitride semiconductor layer 10 includes an undoped GaN layer 1 and an undoped AlGaN layer 2 that are sequentially formed on a Si substrate (not shown). 2DEG (two-dimensional electron gas) is generated at the interface between the undoped GaN layer 1 and the undoped AlGaN layer 2.

なお、上記基板は、Ｓi基板に限らず、サファイヤ基板やＳiＣ基板を用いてもよく、サファイヤ基板やＳiＣ基板上に窒化物半導体層を成長させてもよいし、ＧaＮ基板にＡlＧaＮ層を成長させる等のように、窒化物半導体からなる基板上に窒化物半導体層を成長させてもよい。また、適宜、バッファ層を基板と各層間に形成してもよい。また、上記アンドープＧaＮ層１とアンドープＡlＧaＮ層２との間に層厚１ｎｍ程度のＡlＮ層をヘテロ改善層として形成してもよい。また、上記ＡlＧaＮ層２上にＧaＮキャップ層を形成してもよい。   The substrate is not limited to the Si substrate, and a sapphire substrate or SiC substrate may be used. A nitride semiconductor layer may be grown on the sapphire substrate or SiC substrate, or an AlGaN layer is grown on the GaN substrate. As described above, a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor. Further, a buffer layer may be appropriately formed between the substrate and each layer. Further, an AlN layer having a thickness of about 1 nm may be formed as a hetero improvement layer between the undoped GaN layer 1 and the undoped AlGaN layer 2. Further, a GaN cap layer may be formed on the AlGaN layer 2.

ここでは、上記窒化物半導体層１０のアンドープＡlＧaＮ層２の厚さを例えば１０ｎｍとしてソース電極１１とドレイン電極１２をアニールすることでオーミックコンタクト可能にしている。なお、上記アンドープＡlＧaＮ層の厚さを例えば３０ｎｍとしてアンドープＡlＧaＮ層のオーミックコンタクト部分に予めＳiドープをしてｎ型化させることで電極のオーミックコンタクトを可能としてもよい。また、アンドープＡlＧaＮ層のうちのソース電極が形成される領域およびドレイン電極が形成される領域に予めリセスを形成し、このリセスにソース電極およびドレイン電極を蒸着,アニールすることでオーミックコンタクトを可能としてもよい。   Here, the thickness of the undoped AlGaN layer 2 of the nitride semiconductor layer 10 is set to 10 nm, for example, and the source electrode 11 and the drain electrode 12 are annealed to enable ohmic contact. The thickness of the undoped AlGaN layer may be set to 30 nm, for example, and the ohmic contact portion of the undoped AlGaN layer may be preliminarily Si-doped so as to be n-type to enable ohmic contact of the electrode. In addition, a recess is formed in advance in a region of the undoped AlGaN layer where the source electrode is formed and a region where the drain electrode is formed, and the source electrode and the drain electrode are deposited and annealed in this recess, thereby enabling ohmic contact. Also good.

一方、上記ゲート電極１３は、窒化物半導体層１０のアンドープＡlＧaＮ層２にショットキー接合している。   On the other hand, the gate electrode 13 is in Schottky junction with the undoped AlGaN layer 2 of the nitride semiconductor layer 10.

また、電流コラプスを抑制するための第１の絶縁膜の一例としてのコラプス抑制膜１４が、ソース電極１１とゲート電極１３との間およびドレイン電極１２とゲート電極１３との間で窒化物半導体層１０上に形成されている。   Further, a collapse suppression film 14 as an example of a first insulating film for suppressing current collapse is formed between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13. 10 is formed.

上記コラプス抑制膜１４は、一例として、Ｓiリッチなシリコン窒化膜で作製されている。このＳiリッチなシリコン窒化膜とは、Ｓi：Ｎ＝０.７５：１のストイキオメトリなシリコン窒化膜よりもシリコンＳiの比率の大きいＳiＮ膜であり、例えば、ＳiとＮとの組成比はＳi：Ｎ＝１.１〜１.９：１である。また、好ましい一例では、ＳiとＮとの組成比はＳi：Ｎ＝１.３〜１.５：１である。   For example, the collapse suppression film 14 is made of a Si-rich silicon nitride film. This Si-rich silicon nitride film is a SiN film having a larger ratio of silicon Si than that of a stoichiometric silicon nitride film of Si: N = 0.75: 1. For example, the composition ratio of Si and N is Si: N = 1.1 to 1.9: 1. In a preferred example, the composition ratio of Si and N is Si: N = 1.3 to 1.5: 1.

上記ゲート電極１３は、窒化物半導体層１０のアンドープＡlＧaＮ層２にショットキー接合する基部１３aと、その基部１３aの上部からドレイン電極１２側に向かってコラプス抑制膜１４上に延在するゲートフィールドプレート部１３bとを有する。   The gate electrode 13 includes a base portion 13a that is in Schottky junction with the undoped AlGaN layer 2 of the nitride semiconductor layer 10, and a gate field plate that extends on the collapse suppression film 14 from the upper portion of the base portion 13a toward the drain electrode 12 side. Part 13b.

また、ストイキオメトリなＳiＮ膜で作製されたゲート電極カバー絶縁膜１５を、ソース電極１１の一部の上、ドレイン電極１２の一部の上、ゲート電極１３上およびコラプス抑制膜１４上に形成している。   Further, the gate electrode cover insulating film 15 made of stoichiometric SiN film is formed on part of the source electrode 11, on part of the drain electrode 12, on the gate electrode 13, and on the collapse suppression film 14. doing.

なお、この第１実施形態では、一例として、第２の絶縁膜であるゲート電極カバー絶縁膜１５をＳiＮ膜で作製したが、第２の絶縁膜はこれに限らず、層間絶縁膜の誘電率よりも誘電率が高い絶縁材料であればよい。   In the first embodiment, as an example, the gate electrode cover insulating film 15 as the second insulating film is made of a SiN film. However, the second insulating film is not limited to this, and the dielectric constant of the interlayer insulating film is used. Any insulating material having a higher dielectric constant than the above may be used.

次に、上記ＧaＮ系ＨＦＥＴの製造工程を説明する。   Next, a manufacturing process of the GaN HFET will be described.

まず、図示しないＳi基板上に、ＭＯＣＶＤ(有機金属気相成長)法を用いて、アンドープＧaＮ層１とアンドープＡlＧaＮ層２を順に形成する。   First, an undoped GaN layer 1 and an undoped AlGaN layer 2 are sequentially formed on a Si substrate (not shown) by using MOCVD (metal organic chemical vapor deposition).

次に、上記アンドープＡlＧaＮ層２上に、プラズマＣＶＤ法を用いて、コラプス抑制膜１４となるシリコン窒化膜を形成する。   Next, a silicon nitride film to be the collapse suppression film 14 is formed on the undoped AlGaN layer 2 by using a plasma CVD method.

この電流コラプスとは、特に、ＧaＮ系半導体素子において顕著に表れるもので、低電圧動作でのトランジスタのオン抵抗と比べて、高電圧動作でのトランジスタのオン抵抗が著しく高くなってしまう現象である。   This current collapse is particularly prominent in a GaN-based semiconductor element, and is a phenomenon in which the on-resistance of a transistor in a high voltage operation is significantly higher than the on-resistance of the transistor in a low voltage operation. .

次に、フォトレジストをマスクとしてウェットエッチングを行うことにより、コラプス抑制膜１４となるシリコン窒化膜のうちのゲート電極１３の基部１３aを形成すべき領域を除去して、この領域にアンドープＡlＧaＮ層２を露出させる。   Next, by performing wet etching using a photoresist as a mask, a region where the base portion 13a of the gate electrode 13 is to be formed is removed from the silicon nitride film to be the collapse suppression film 14, and an undoped AlGaN layer 2 is formed in this region. To expose.

次に、上記フォトレジストを除去し、コラプス抑制膜１４を熱処理する(例えば５００℃で３０分間)。   Next, the photoresist is removed, and the collapse suppression film 14 is heat-treated (for example, at 500 ° C. for 30 minutes).

その後、ＷＮ／Ｗ(またはＴiＮ)を全面スパッタし、フォトリソグラフィでゲート電極１３を形成すべきゲート電極形成領域にエッチングマスク(図示せず)を形成し、このエッチングマスクを用いてドライエッチングまたはウェットエッチングを行なって、ゲート電極形成領域以外のＷＮ／Ｗ膜(またはＴiＮ膜)を除去して、基部１３aとゲートフィールドプレート部１３bを有するゲート電極１３を形成する。このゲート電極１３の基部１３aは、ＡlＧaＮ層１２にショットキー接合している。   Thereafter, WN / W (or TiN) is sputtered over the entire surface, an etching mask (not shown) is formed in the gate electrode formation region where the gate electrode 13 is to be formed by photolithography, and dry etching or wet is performed using this etching mask. Etching is performed to remove the WN / W film (or TiN film) other than the gate electrode formation region, thereby forming the gate electrode 13 having the base portion 13a and the gate field plate portion 13b. The base 13 a of the gate electrode 13 is Schottky joined to the AlGaN layer 12.

その後、上記ゲート電極１３上およびコラプス抑制膜１４上に、プラズマＣＶＤ(化学的気相成長)法により、ゲート電極カバー絶縁膜１５となるＳiＮ膜を形成する。   Thereafter, an SiN film to be the gate electrode cover insulating film 15 is formed on the gate electrode 13 and the collapse suppression film 14 by plasma CVD (chemical vapor deposition).

次に、フォトリソグラフィにより、ソース電極１１,ドレイン電極１２を形成すべき領域にレジストパターン(図示せず)を形成して、このレジストパターン上にＴi/Ａl(またはＨf／Ａi)を順に蒸着し、リフトオフによりＴi/Ａl(またはＨf／Ａi)からなるソース電極１１,ドレイン電極１２を形成する。   Next, a resist pattern (not shown) is formed in a region where the source electrode 11 and the drain electrode 12 are to be formed by photolithography, and Ti / Al (or Hf / Ai) is sequentially deposited on the resist pattern. Then, the source electrode 11 and the drain electrode 12 made of Ti / Al (or Hf / Ai) are formed by lift-off.

次に、上記ソース電極１１,ドレイン電極１２を、熱処理(オーミックアニール)してオーミック電極にする(例えば５００℃で３０分)。   Next, the source electrode 11 and the drain electrode 12 are heat-treated (ohmic annealing) to form ohmic electrodes (for example, at 500 ° C. for 30 minutes).

次に、ゲート電極カバー絶縁膜１５上およびソース電極１１,ドレイン電極１２,ゲート電極１３上に、ＬＴＯ(Low Temperature Oxide：低温酸化膜)などのシリコン酸化膜で層間絶縁膜１６を形成する。   Next, an interlayer insulating film 16 is formed of a silicon oxide film such as LTO (Low Temperature Oxide) on the gate electrode cover insulating film 15 and on the source electrode 11, the drain electrode 12, and the gate electrode 13.

次に、エッチングマスクを用いたドライエッチングまたはウェットエッチングにより、ソース電極１１上およびドレイン電極１２上にコンタクトホールを形成する。   Next, contact holes are formed on the source electrode 11 and the drain electrode 12 by dry etching or wet etching using an etching mask.

そして、上記コンタクトホール内にＡlまたはＣuなどからなる配線層を形成し、ソース電極１１側の配線層からゲート電極１３を覆うようにドレイン電極１２側に向かって延びるソースフィールドプレート部２１を形成している。一方、ドレイン電極１２側の配線層からソース電極１１側に向かって延びるドレインフィールドプレート部２２を形成している。なお、ドレインフィールドプレート部２２は無くてもよい。   Then, a wiring layer made of Al or Cu or the like is formed in the contact hole, and a source field plate portion 21 extending from the wiring layer on the source electrode 11 side to the drain electrode 12 side so as to cover the gate electrode 13 is formed. ing. On the other hand, a drain field plate portion 22 extending from the wiring layer on the drain electrode 12 side toward the source electrode 11 side is formed. The drain field plate portion 22 may not be provided.

図３は第１比較例のＧａＮ系ＨＦＥＴの要部の拡大断面図を示している。この第１比較例のＧａＮ系ＨＦＥＴは、第２の絶縁膜であるゲート電極カバー絶縁膜１１５が層間絶縁膜１６と同じシリコン酸化膜で形成されている点を除いて、図１,図２に示すＧａＮ系ＨＦＥＴと同一の構成をしている。なお、この第１比較例のＧａＮ系ＨＦＥＴは、この発明の窒化物半導体装置ではない。   FIG. 3 shows an enlarged cross-sectional view of the main part of the GaN-based HFET of the first comparative example. The GaN-based HFET of the first comparative example is shown in FIGS. 1 and 2 except that the gate electrode cover insulating film 115 as the second insulating film is formed of the same silicon oxide film as the interlayer insulating film 16. It has the same configuration as the GaN-based HFET shown. Note that the GaN-based HFET of the first comparative example is not the nitride semiconductor device of the present invention.

また、図４は第２比較例のＧａＮ系ＨＦＥＴの要部の拡大断面図を示している。この第２比較例のＧａＮ系ＨＦＥＴは、ゲート電極１１３にゲートフィールドプレート部がない点を除いて、図１,図２に示すＧａＮ系ＨＦＥＴと同一の構成をしている。なお、この第２比較例のＧａＮ系ＨＦＥＴは、この発明の窒化物半導体装置ではない。   FIG. 4 shows an enlarged cross-sectional view of the main part of the GaN-based HFET of the second comparative example. The GaN-based HFET of the second comparative example has the same configuration as the GaN-based HFET shown in FIGS. 1 and 2 except that the gate electrode 113 does not have a gate field plate portion. Note that the GaN-based HFET of the second comparative example is not the nitride semiconductor device of the present invention.

図５は上記ＧａＮ系ＨＦＥＴのゲート電極端の電界強度を説明するための断面図を示している。図５において、図１,図２に示す構成と同一の構成部には同一参照番号を付している。また、Ａはゲート電極１３のゲートフィールドプレート部１３bの端(ドレイン電極１２側の端縁部)の領域であり、Ｂはゲート電極１３直下の領域である(基部１３aのドレイン電極１２側の端縁部の直下)。   FIG. 5 is a cross-sectional view for explaining the electric field strength at the gate electrode end of the GaN-based HFET. In FIG. 5, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals. A is a region at the end of the gate field plate portion 13b of the gate electrode 13 (edge portion on the drain electrode 12 side), and B is a region immediately below the gate electrode 13 (the end of the base portion 13a on the drain electrode 12 side). Just below the edge).

また、図６はゲート電極カバー絶縁膜１５の誘電率に対するゲート電極１３端の電界強度のシミュレーション結果を示している。図６において、横軸はゲート電極カバー絶縁膜１５の誘電率εを表し、縦軸はゲート電極１３直下の領域Ｂの電界強度[ＭＶ／ｃｍ]を表している。   FIG. 6 shows a simulation result of the electric field strength at the end of the gate electrode 13 with respect to the dielectric constant of the gate electrode cover insulating film 15. In FIG. 6, the horizontal axis represents the dielectric constant ε of the gate electrode cover insulating film 15, and the vertical axis represents the electric field strength [MV / cm] in the region B immediately below the gate electrode 13.

上記シミュレーションの条件を図７に示しており、詳しくは、次のとおりである。なお、図７において、１００はＳi基板である。   The simulation conditions are shown in FIG. 7, and the details are as follows. In FIG. 7, reference numeral 100 denotes an Si substrate.

ゲート電極・ドレイン電極間の距離(Ｌgd) ： １０μｍ
ゲート長(Ｌg) ： ２．２μｍ
シートキャリア濃度Ｎs ： ５．５×１０１２／ｃｍ２
ゲート電極カバー絶縁膜の誘電率(ε) ： ２〜２０(パラメータ)
層間絶縁膜の膜厚(１層目) ： ８２００Å(８２０ｎｍ)
層間絶縁膜の膜厚(２層目) ： ３００００Å(３０００ｎｍ)
ゲートフィールドプレート長(Ｌgfp) ： １μｍまたはなし(パラメータ)
ソースフィールドプレート長(Ｌsfp) ： Ｌg＋３μｍ
ソースフィールドプレート部の厚さ ： １５０００Å(１５００ｎｍ)
ドレインフィールドプレート長(Ｌdfp) ： Ｌgd−３μｍ
ソース電極 印加電圧(Ｖs) ： ０Ｖ
ドレイン電極 印加電圧(Ｖd) ： ６００Ｖ
ゲート電極 印加電圧(Ｖg) ： −１０Ｖ
基板電位 ： ０Ｖ(基板グラウンド) Distance between gate electrode and drain electrode (Lgd): 10 μm
Gate length (Lg): 2.2μm
Sheet carrier concentration Ns: 5.5 × 10 12 / cm 2
Dielectric constant (ε) of gate electrode cover insulating film: 2 to 20 (parameter)
Interlayer insulation film thickness (first layer): 8200 mm (820 nm)
Interlayer insulation film thickness (second layer): 30000 mm (3000 nm)
Gate field plate length (Lgfp): 1 μm or none (parameter)
Source field plate length (Lsfp): Lg + 3μm
Source field plate thickness: 15000 mm (1500 nm)
Drain field plate length (Ldfp): Lgd-3μm
Source electrode Applied voltage (Vs): 0V
Drain electrode Applied voltage (Vd): 600V
Gate electrode applied voltage (Vg): -10V
Substrate potential: 0V (substrate ground)

また、図６に示す「○」(丸印)は第２比較例のゲートフィールドプレート部がないゲート電極１１３を備えたＧａＮ系ＨＦＥＴにおいて、ゲート電極カバー絶縁膜１５の誘電率εを４および２０としたときのゲート電極１１３直下の電界強度のデータである。また、図６に示す「□」(四角印)はこの第１実施形態のＧａＮ系ＨＦＥＴにおいて、ゲート電極カバー絶縁膜１５の誘電率εを２,３,４,７,１０,１５,２０としたときのゲート電極１３直下の領域Ｂの電界強度のデータである。なお、層間絶縁膜１６が誘電率４のＳiＯ２からなるとき、ゲート電極カバー絶縁膜１５の誘電率εが２,３,４については、この発明に含まれない。 Also, “◯” (circle) shown in FIG. 6 indicates that the dielectric constant ε of the gate electrode cover insulating film 15 is 4 and 20 in the GaN-based HFET having the gate electrode 113 without the gate field plate portion of the second comparative example. Data of the electric field intensity directly under the gate electrode 113. Further, “□” (square marks) shown in FIG. 6 indicate that the dielectric constant ε of the gate electrode cover insulating film 15 is 2, 3, 4, 7, 10, 15, 20 in the GaN-based HFET of the first embodiment. It is the data of the electric field strength of the area | region B right under the gate electrode 13 at that time. Note that when the interlayer insulating film 16 is made of SiO 2 having a dielectric constant of 4, the dielectric constant ε of the gate electrode cover insulating film 15 of 2, 3, 4 is not included in the present invention.

ここで、各誘電率εの具体的な絶縁材料の一例として、
誘電率ε＝２〜３： ＳｉＯＣ、ポリイミド等
誘電率ε＝４ ： ＳiＯ２
誘電率ε＝６ ： ＳiＮ
誘電率ε＝７ ： ＳiＮｘ(N-rich)
誘電率ε＝１０ ： Ａl２Ｏ３
誘電率ε＝２０（〜２５）： Ｔa２Ｏ５
がある。 Here, as an example of a specific insulating material of each dielectric constant ε,
Dielectric constant ε = 2 to 3: SiOC, polyimide, etc. Dielectric constant ε = 4: SiO 2
Dielectric constant ε = 6: SiN
Dielectric constant ε = 7: SiNx (N-rich)
Dielectric constant ε = 10: Al 2 O 3
Dielectric constant ε = 20 (˜25): Ta 2 O 5
There is.

図６に示すように、ゲート電極１１３にゲートフィールドプレート部がない構造では、ゲート電極１３のゲートフィールドプレート部１３bがある場合に比べて、ゲート電極１３直下の領域Ｂの電界強度が著しく増大する(１．５〜１．８倍)。ゲート電極１３直下の領域Ｂでは、２ＤＥＧとゲート電極とが近接しており、比較的低い電界強度でも絶縁破壊となる。   As shown in FIG. 6, in the structure in which the gate electrode 113 does not have the gate field plate portion, the electric field strength in the region B immediately below the gate electrode 13 is remarkably increased as compared with the case where the gate field plate portion 13b of the gate electrode 13 is present. (1.5 to 1.8 times). In the region B immediately below the gate electrode 13, 2DEG and the gate electrode are close to each other, and dielectric breakdown occurs even at a relatively low electric field strength.

図８はゲート電極カバー絶縁膜の誘電率に対するゲートフィールドプレート部の端の電界強度の緩和率のシミュレーション結果を示している。図８において、横軸はゲート電極カバー絶縁膜１５の誘電率εを表し、縦軸は電界強度の緩和率を表している。この「電界強度の緩和率」とは、ゲート電極カバー絶縁膜１５の誘電率εが２のときのＧａＮ系ＨＦＥＴの領域Ａ(ゲートフィールドプレート部１３bの端)の電界強度に対して、ゲート電極カバー絶縁膜１５の誘電率εが３,４,６,１０,２０のときのＧａＮ系ＨＦＥＴの領域Ａ(ゲートフィールドプレート部１３bの端)の電界強度の比率を百分率で表したものである。   FIG. 8 shows a simulation result of the relaxation rate of the electric field strength at the end of the gate field plate portion with respect to the dielectric constant of the gate electrode cover insulating film. In FIG. 8, the horizontal axis represents the dielectric constant ε of the gate electrode cover insulating film 15, and the vertical axis represents the relaxation rate of the electric field strength. This “relaxation rate of electric field strength” means that the gate electrode cover insulating film 15 has a gate electrode with respect to the electric field strength of the region A (end of the gate field plate portion 13b) of the GaN-based HFET when the dielectric constant ε is 2. The ratio of the electric field strength of the region A (the end of the gate field plate portion 13b) of the GaN-based HFET when the dielectric constant ε of the cover insulating film 15 is 3, 4, 6, 10, 20 is expressed as a percentage.

このシミュレーションの条件は、図６,図７に示すシミュレーションの条件と同じである。   The simulation conditions are the same as the simulation conditions shown in FIGS.

図８に示すように、ゲート電極カバー絶縁膜１５の誘電率εが大きくなるほど、ゲートフィールドプレート部１３bの端の領域Ａの電界強度の緩和率が大きくなり、特に誘電率εが５よりも大きい絶縁材料(ＳiＮ,ＳiＮｘ(N-rich),Ａl２Ｏ３など)で電界強度の緩和効果が高い。上記構成のＧａＮ系ＨＦＥＴでは、ゲートフィールドプレート部１３bの端の領域Ａの電界強度を下げるほど、高電圧印加状態での信頼性(寿命)が向上する。 As shown in FIG. 8, as the dielectric constant ε of the gate electrode cover insulating film 15 increases, the relaxation rate of the electric field strength in the region A at the end of the gate field plate portion 13b increases. In particular, the dielectric constant ε is greater than 5. Insulating materials (SiN, SiNx (N-rich), Al 2 O 3 etc.) have a high effect of reducing the electric field strength. In the GaN-based HFET configured as described above, the reliability (lifetime) in a high voltage application state is improved as the electric field strength in the region A at the end of the gate field plate portion 13b is lowered.

次に、図９はゲート電極カバー絶縁膜１５(誘電率４)の膜厚に対するゲートフィールドプレート部１３bの端の電界強度(図５の領域Ａ)のシミュレーション結果を示し、図１０はゲート電極カバー絶縁膜１５(誘電率２０)の膜厚に対するゲートフィールドプレート部１３bの端(図５の領域Ａ)の電界強度のシミュレーション結果を示している。   Next, FIG. 9 shows a simulation result of the electric field strength (region A in FIG. 5) at the end of the gate field plate portion 13b with respect to the film thickness of the gate electrode cover insulating film 15 (dielectric constant 4), and FIG. The simulation result of the electric field strength of the edge (area A in FIG. 5) of the gate field plate portion 13b with respect to the film thickness of the insulating film 15 (dielectric constant 20) is shown.

このシミュレーションの条件は、ゲート電極カバー絶縁膜１５(誘電率４)の膜厚をパラメータとした点を除いて図６,図７に示すシミュレーションの条件と同じである。   The simulation conditions are the same as the simulation conditions shown in FIGS. 6 and 7 except that the film thickness of the gate electrode cover insulating film 15 (dielectric constant 4) is used as a parameter.

図９,図１０において、横軸はゲート電極カバー絶縁膜１５の膜厚[Å]を表し、縦軸は電界強度[ＭＶ／ｃｍ]を表している。   9 and 10, the horizontal axis represents the film thickness [Å] of the gate electrode cover insulating film 15, and the vertical axis represents the electric field strength [MV / cm].

また、図９,図１０に示す「◇」(菱形印)は、領域Ａにおけるゲートフィールドプレート部１３b側の電界強度であり、図９,図１０に示す「□」(四角印)は、領域Ａにおけるゲート電極カバー絶縁膜１５側の電界強度である。   Further, “◇” (diamond mark) shown in FIGS. 9 and 10 is the electric field intensity on the gate field plate portion 13b side in the region A, and “□” (square mark) shown in FIGS. A is the electric field strength on the gate electrode cover insulating film 15 side in A.

図９,図１０に示すように、ゲート電極カバー絶縁膜１５の膜厚が薄くなると、領域Ａの電界強度が緩和されにくくなる。   As shown in FIGS. 9 and 10, when the thickness of the gate electrode cover insulating film 15 is reduced, the electric field strength in the region A is hardly relaxed.

したがって、上記ＧａＮ系ＨＦＥＴでは、ゲート電極カバー絶縁膜１５の膜厚は３００Å(＝３０ｎｍ)以上であることが好ましい。これにより、ゲートフィールドプレート部１３b端での電界強度を確実に緩和することができる。   Therefore, in the GaN-based HFET, the thickness of the gate electrode cover insulating film 15 is preferably 300 mm (= 30 nm) or more. As a result, the electric field strength at the end of the gate field plate portion 13b can be reliably reduced.

上記構成の窒化物半導体装置によれば、ソース電極１１のソースフィールドプレート部２１が、ゲート電極１３を覆うようにドレイン電極１２側に向かって層間絶縁膜１６上に延在する窒化物半導体装置において、ソース電極１１とゲート電極１３との間およびドレイン電極１２とゲート電極１３との間で窒化物半導体層１０上にコラプス抑制膜１４(第１の絶縁膜)を形成し、少なくともコラプス抑制膜１４およびゲート電極１３上に層間絶縁膜１６の誘電率よりも誘電率が高いゲート電極カバー絶縁膜１５(第２の絶縁膜)を形成することによって、ゲートフィールドプレート部１３bの端での電界集中を効果的に抑制でき、オフ耐圧を向上できる。   According to the nitride semiconductor device having the above configuration, in the nitride semiconductor device in which the source field plate portion 21 of the source electrode 11 extends on the interlayer insulating film 16 toward the drain electrode 12 so as to cover the gate electrode 13. A collapse suppression film 14 (first insulating film) is formed on the nitride semiconductor layer 10 between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13, and at least the collapse suppression film 14. Further, by forming a gate electrode cover insulating film 15 (second insulating film) having a dielectric constant higher than that of the interlayer insulating film 16 on the gate electrode 13, the electric field concentration at the end of the gate field plate portion 13b is reduced. It can be effectively suppressed and the off breakdown voltage can be improved.

また、誘電率が５以上のゲート電極カバー絶縁膜１５(第２の絶縁膜)によりコラプス抑制膜１４(第１の絶縁膜)上およびゲート電極１３上を覆うことによって、ゲートフィールドプレート部１３bの端での電界強度を効果的に緩和することができる。   Further, by covering the collapse suppression film 14 (first insulating film) and the gate electrode 13 with a gate electrode cover insulating film 15 (second insulating film) having a dielectric constant of 5 or more, the gate field plate portion 13b The electric field strength at the edge can be effectively reduced.

上記第１実施形態では、層間絶縁膜１６の材料としてＳiＯ２を用いたが、ポリイミドやＳＯＧ(Spin On Glass;スピン・オン・グラス)またはＢＰＳＧ(Boron Phosphorus Silicon Glass;ホウ素・リン・シリケート・ガラス)などの絶縁材料を用いてもよい。また、層間絶縁膜として、例えばＳiＯ２とＳＯＧからなる多層膜構造としてもよい。 In the first embodiment, SiO 2 is used as the material of the interlayer insulating film 16, but polyimide, SOG (Spin On Glass) or BPSG (Boron Phosphorus Silicon Glass) is used. An insulating material such as) may be used. Further, the interlayer insulating film may have a multilayer film structure made of, for example, SiO 2 and SOG.

〔第２実施形態〕
図１１はこの発明の第２実施形態の窒化物半導体装置の一例としてのノーマリーオンタイプのＧａＮ系ＨＦＥＴの断面図を示している。 [Second Embodiment]
FIG. 11 shows a sectional view of a normally-on type GaN-based HFET as an example of a nitride semiconductor device according to the second embodiment of the present invention.

この第２実施形態のＧａＮ系ＨＦＥＴは、図１１に示すコラプス抑制膜１１４が多層絶縁膜構造である点とゲート絶縁膜２０を有する点が第１実施形態のＧａＮ系ＨＦＥＴと異なる。図１１では、第１実施形態のＧａＮ系ＨＦＥＴと同一の構成部に同一参照番号を付している。   The GaN-based HFET of the second embodiment is different from the GaN-based HFET of the first embodiment in that the collapse suppression film 114 shown in FIG. 11 has a multilayer insulating film structure and a gate insulating film 20. In FIG. 11, the same reference numerals are assigned to the same components as those of the GaN-based HFET of the first embodiment.

上記ＧaＮ系ＨＦＥＴの製造工程は、アンドープＧaＮ層１とアンドープＡlＧaＮ層２を順に形成した後、アンドープＡlＧaＮ層２上にプラズマＣＶＤ法を用いてＳiＯ２やＳiＮを積層して、多層絶縁膜構造のコラプス抑制膜１１４を形成する。 The manufacturing process of the GaN-based HFET is to form an undoped GaN layer 1 and an undoped AlGaN layer 2 in this order, and then stack SiO 2 or SiN on the undoped AlGaN layer 2 using a plasma CVD method to form a multilayer insulating film structure. A collapse suppression film 114 is formed.

次に、上記コラプス抑制膜１１４のうち、ゲート電極１３の基部１３aを形成すべき領域をウェットエッチングにより除去して、この領域にアンドープＡlＧaＮ層２を露出させる。   Next, a region of the collapse suppression film 114 where the base portion 13a of the gate electrode 13 is to be formed is removed by wet etching, and the undoped AlGaN layer 2 is exposed in this region.

次に、露出したアンドープＡlＧaＮ層２上にプラズマＣＶＤ法を用いてゲート絶縁膜２０を形成する。   Next, a gate insulating film 20 is formed on the exposed undoped AlGaN layer 2 using a plasma CVD method.

次に、ＷＮ／Ｗ(またはＴiＮ)を全面スパッタし、フォトリソグラフィでゲート電極１３を形成すべきゲート電極形成領域にエッチングマスク(図示せず)を形成し、このエッチングマスクを用いてドライエッチングまたはウェットエッチングを行なって、ゲート電極形成領域以外のＷＮ／Ｗ膜(またはＴiＮ膜)およびゲート絶縁膜２０を除去して、ＷＮ／Ｗ(またはＴiＮ)からなるゲート電極１３を形成する。   Next, WN / W (or TiN) is sputtered over the entire surface, and an etching mask (not shown) is formed in the gate electrode formation region where the gate electrode 13 is to be formed by photolithography. Using this etching mask, dry etching or Wet etching is performed to remove the WN / W film (or TiN film) and the gate insulating film 20 other than the gate electrode formation region, and the gate electrode 13 made of WN / W (or TiN) is formed.

上記第２実施形態のＧａＮ系ＨＦＥＴは、第１実施形態のＧａＮ系ＨＦＥＴと同様の効果を有する。   The GaN HFET of the second embodiment has the same effect as the GaN HFET of the first embodiment.

また、上記第１,第２実施形態では、窒化物半導体層を、ＧaＮ層やＡlＧaＮ層で構成したが、ＡlxＩnyＧa1-x-yＮ(ｘ≧０、ｙ≧０、０≦ｘ＋ｙ＜１)で表されるＧａＮ系半導体層を含むものでもよい。すなわち、上記窒化物半導体層は、ＡlＧaＮ、ＧaＮ、ＩnＧaＮ等を含むものとしてもよい。また、上記第１,第２実施形態では、ノーマリーオンタイプのＨＦＥＴについて説明したが、ノーマリオフタイプでも同様の効果が得られる。 In the first and second embodiments, the nitride semiconductor layer is composed of a GaN layer or an AlGaN layer. However, Al x In y Ga 1-xy N (x ≧ 0, y ≧ 0, 0 ≦ x + y < It may include a GaN-based semiconductor layer represented by 1). That is, the nitride semiconductor layer may contain AlGaN, GaN, InGaN, or the like. In the first and second embodiments, the normally-on type HFET has been described. However, the normally-off type can achieve the same effect.

この発明の具体的な実施の形態について説明したが、この発明は上記第１,第２実施形態に限定されるものではなく、この発明の範囲内で種々変更して実施することができる。   Although specific embodiments of the present invention have been described, the present invention is not limited to the first and second embodiments described above, and various modifications can be made within the scope of the present invention.

この発明の窒化物半導体装置は、
窒化物半導体層１０と、
上記窒化物半導体層１０上に、または、上記窒化物半導体層１０内に少なくとも一部が形成されると共に、互いに間隔をあけて配置されたソース電極１１およびドレイン電極１２と、
上記ソース電極１１と上記ドレイン電極１２との間かつ上記窒化物半導体層１０上に形成されたゲート電極１３と、
上記ソース電極１１と上記ゲート電極１３との間および上記ドレイン電極１２と上記ゲート電極１３との間で上記窒化物半導体層１０上に形成された第１の絶縁膜１４と、
少なくとも上記第１の絶縁膜１４上および上記ゲート電極１３上に形成された第２の絶縁膜１５と、
上記第２の絶縁膜１５上に形成され、少なくともＳiＯ２を含む材料からなる層間絶縁膜１６と
を備え、
上記ゲート電極１３は、上記窒化物半導体層１０の最上層とショットキー接合された基部と、その基部の上部から上記ドレイン電極１２側に向かって上記第１の絶縁膜１４上に延在するゲートフィールドプレート部１３bとを有すると共に、
上記ソース電極１１は、上記ゲート電極１３を覆うように上記ドレイン電極１２側に向かって上記層間絶縁膜１６上に延在するソースフィールドプレート部を有し、
上記第２の絶縁膜１５の誘電率は、上記層間絶縁膜１６の誘電率よりも高いことを特徴とする。 The nitride semiconductor device of the present invention is
A nitride semiconductor layer 10;
A source electrode 11 and a drain electrode 12 which are formed at least partially on the nitride semiconductor layer 10 or in the nitride semiconductor layer 10 and are spaced apart from each other;
A gate electrode 13 formed between the source electrode 11 and the drain electrode 12 and on the nitride semiconductor layer 10;
A first insulating film 14 formed on the nitride semiconductor layer 10 between the source electrode 11 and the gate electrode 13 and between the drain electrode 12 and the gate electrode 13;
A second insulating film 15 formed on at least the first insulating film 14 and the gate electrode 13;
An interlayer insulating film 16 formed on the second insulating film 15 and made of a material containing at least SiO 2 ;
The gate electrode 13 includes a base that is Schottky-bonded to the uppermost layer of the nitride semiconductor layer 10, and a gate that extends on the first insulating film 14 from the upper portion of the base toward the drain electrode 12 side. And a field plate portion 13b,
The source electrode 11 has a source field plate portion extending on the interlayer insulating film 16 toward the drain electrode 12 so as to cover the gate electrode 13;
The dielectric constant of the second insulating film 15 is higher than the dielectric constant of the interlayer insulating film 16.

上記構成によれば、ソース電極１１のソースフィールドプレート部２１が、ゲート電極１３を覆うようにドレイン電極１２側に向かって層間絶縁膜１６上に延在する窒化物半導体装置において、ソース電極１１とゲート電極１３との間およびドレイン電極１２とゲート電極１３との間で窒化物半導体層１０上に第１の絶縁膜１４を形成し、少なくとも第１の絶縁膜１４およびゲート電極１３上に、少なくともＳiＯ２を含む材料からなる層間絶縁膜１６の誘電率よりも誘電率が高い第２の絶縁膜１５を形成することによって、ゲートフィールドプレート部１３bの端での電界集中を効果的に抑制でき、オフ耐圧を向上できる。なお、上記ソース電極１１およびドレイン電極１２は、窒化物半導体層１０上に互いに間隔をあけて形成してもよいし、窒化物半導体層１０内に少なくとも一部が埋め込まれるようにかつ互いに間隔をあけて形成してもよい。 According to the above configuration, in the nitride semiconductor device in which the source field plate portion 21 of the source electrode 11 extends on the interlayer insulating film 16 toward the drain electrode 12 so as to cover the gate electrode 13, A first insulating film is formed on the nitride semiconductor layer between the gate electrode and between the drain electrode and the gate electrode, and at least on the first insulating film and the gate electrode. by forming the second insulating film 15 having a higher dielectric constant than the dielectric constant of the interlayer insulating film 16 made of a material containing SiO 2, it can be effectively suppressed electric field concentration at the edge of the gate field plate portion 13b, Off breakdown voltage can be improved. The source electrode 11 and the drain electrode 12 may be formed on the nitride semiconductor layer 10 so as to be spaced from each other, or at least partially embedded in the nitride semiconductor layer 10 and spaced from each other. You may open and form.

また、一実施形態の窒化物半導体装置では、
上記第２の絶縁膜１５の誘電率が５以上である。 In the nitride semiconductor device of one embodiment,
The dielectric constant of the second insulating film 15 is 5 or more.

上記実施形態によれば、誘電率が５以上の第２の絶縁膜１５により第１の絶縁膜１４上およびゲート電極１３上を覆うことによって、ゲートフィールドプレート部１３bの端での電界強度を効果的に緩和することができる。   According to the embodiment, the electric field strength at the end of the gate field plate portion 13b is effectively obtained by covering the first insulating film 14 and the gate electrode 13 with the second insulating film 15 having a dielectric constant of 5 or more. Can be relaxed.

また、一実施形態の窒化物半導体装置では、
上記第２の絶縁膜１５の膜厚が３０ｎｍ以上である。 In the nitride semiconductor device of one embodiment,
The film thickness of the second insulating film 15 is 30 nm or more.

上記実施形態によれば、膜厚が３０ｎｍ以上の第２の絶縁膜１５により第１の絶縁膜１４上およびゲート電極１３上を覆うことによって、ゲートフィールドプレート部１３bの端での電界強度を確実に緩和することができる。   According to the embodiment, the electric field strength at the end of the gate field plate portion 13b is ensured by covering the first insulating film 14 and the gate electrode 13 with the second insulating film 15 having a thickness of 30 nm or more. Can be relaxed.

１…アンドープＧaＮ層
２…アンドープＡlＧaＮ層
１０…窒化物半導体層
１１…ソース電極
１２…ドレイン電極
１３…ゲート電極
１３a…基部
１３b…ゲートフィールドプレート部
１４…コラプス抑制膜
１５…ゲート電極カバー絶縁膜
１６…層間絶縁膜
２０…ゲート絶縁膜
２１…ソースフィールドプレート部
２２…ドレインフィールドプレート部
１００…Ｓi基板 DESCRIPTION OF SYMBOLS 1 ... Undoped GaN layer 2 ... Undoped AlGaN layer 10 ... Nitride semiconductor layer 11 ... Source electrode 12 ... Drain electrode 13 ... Gate electrode 13a ... Base part 13b ... Gate field plate part 14 ... Collapse suppression film | membrane 15 ... Gate electrode cover insulating film 16 ... Interlayer insulating film 20 ... Gate insulating film 21 ... Source field plate part 22 ... Drain field plate part 100 ... Si substrate

Claims (3)

窒化物半導体層と、
上記窒化物半導体層上に、または、上記窒化物半導体層内に少なくとも一部が形成されると共に、互いに間隔をあけて配置されたソース電極およびドレイン電極と、
上記ソース電極と上記ドレイン電極との間かつ上記窒化物半導体層上に形成されたゲート電極と、
上記ソース電極と上記ゲート電極との間および上記ドレイン電極と上記ゲート電極との間で上記窒化物半導体層上に形成された第１の絶縁膜と、
少なくとも上記第１の絶縁膜上および上記ゲート電極上に形成された第２の絶縁膜と、
上記第２の絶縁膜上に形成され、少なくともＳiＯ２を含む材料からなる層間絶縁膜と
を備え、
上記ゲート電極は、上記窒化物半導体層の最上層とショットキー接合された基部と、その基部の上部から上記ドレイン電極側に向かって上記第１の絶縁膜上に延在するゲートフィールドプレート部とを有すると共に、
上記ソース電極は、上記ゲート電極を覆うように上記ドレイン電極側に向かって上記層間絶縁膜上に延在するソースフィールドプレート部を有し、
上記第２の絶縁膜の誘電率は、上記層間絶縁膜の誘電率よりも高いことを特徴とする窒化物半導体装置。 A nitride semiconductor layer;
A source electrode and a drain electrode which are formed on the nitride semiconductor layer or in the nitride semiconductor layer and spaced apart from each other;
A gate electrode formed between the source electrode and the drain electrode and on the nitride semiconductor layer;
A first insulating film formed on the nitride semiconductor layer between the source electrode and the gate electrode and between the drain electrode and the gate electrode;
A second insulating film formed on at least the first insulating film and the gate electrode;
An interlayer insulating film formed on the second insulating film and made of a material containing at least SiO 2 ;
The gate electrode includes a base portion that is Schottky-bonded to the uppermost layer of the nitride semiconductor layer, a gate field plate portion that extends on the first insulating film from the upper portion of the base portion toward the drain electrode side, and And having
The source electrode has a source field plate portion extending on the interlayer insulating film toward the drain electrode so as to cover the gate electrode,
The nitride semiconductor device, wherein a dielectric constant of the second insulating film is higher than a dielectric constant of the interlayer insulating film. 請求項１に記載の窒化物半導体装置において、
上記第２の絶縁膜の誘電率が５以上であることを特徴とする窒化物半導体装置。 The nitride semiconductor device according to claim 1,
A nitride semiconductor device, wherein the second insulating film has a dielectric constant of 5 or more. 請求項１または２に記載の窒化物半導体装置において、
上記第２の絶縁膜の膜厚が３０ｎｍ以上であることを特徴とする窒化物半導体装置。 The nitride semiconductor device according to claim 1 or 2,
The nitride semiconductor device, wherein the second insulating film has a thickness of 30 nm or more.
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