JP2010118515A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently relax electrolytic concentration between a gate electrode and a drain electrode of a semiconductor device by providing a field plate. <P>SOLUTION: The semiconductor device has a ground 11, and first and second main electrodes 29a and 29b formed on a ground surface 11a of the ground, separated from, and opposing to each other. Further, the semiconductor device has a gate electrode 27 formed on the ground surface while sandwiched between the first and second main electrodes. Furthermore, a first ground surface protective film 31a is formed on the ground surface exposed between the gate electrode and first main electrode. Further, a second ground surface protective film 31b is formed on the ground surface exposed between the gate electrode and second main electrode. Then a field plate 43 is formed covering an upper surface 27a of the gate electrode to a side surface 27b of the gate electrode opposed to the second main electrode and the second ground surface protective film in one body. Further, a border surface 47 between the field plate and second ground surface protective film is an inclined surface curved convexly toward the ground surface. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a method for reducing electric field concentration generated between a gate electrode and a drain electrode by providing a field plate.

  Conventionally, HEMT (High Electron Mobility Transistor) is well known as a field effect transistor using a two-dimensional electron gas (hereinafter also referred to as 2DEG) layer as a current path. The HEMT has, for example, a base including an electron transit layer made of GaN in which no impurities are introduced, and an electron supply layer formed of AlGaN on the upper side of the electron transit layer. The HEMT has a gate electrode on the upper side of a base, and a source electrode and a drain electrode arranged with the gate electrode interposed therebetween. As is well known, in such a HEMT, a 2DEG layer is generated in the electron transit layer based on one or both of piezoelectric polarization and spontaneous polarization at the heterojunction surfaces of the electron transit layer and the electron supply layer. Since the resistance value in the film thickness direction of the electron supply layer is small and the resistance value in the direction orthogonal to the film thickness direction is large, the current between the drain electrode and the source electrode flows through the 2DEG layer.

  Thus, by using the 2DEG layer, the HEMT has been expected as a material for realizing an excellent electronic device in terms of high-temperature operation, high-speed switching operation, high-power operation, and the like.

  By the way, in the HEMT, a negative charge is generated on the surface of the electron supply layer during an AC operation. Due to the generation of the negative charge, a so-called current collapse phenomenon occurs in which the maximum drain current flowing through the electron transit layer is reduced from the maximum drain current during DC operation.

  In order to suppress this current collapse, a method of forming a base surface protective film made of SiN on the upper surface of the base exposed from the gate electrode, the source electrode, and the drain electrode is conventionally known. However, the HEMT has a problem that the breakdown voltage between the source and the drain is lowered due to the provision of the SiN base surface protective film on the upper surface of the electron supply layer.

  Therefore, in order to suppress such a decrease in breakdown voltage, a semiconductor device is intended to reduce the concentration of the electric field by providing a field plate on the side surface facing the drain electrode of the gate electrode from the upper surface of the gate electrode, thereby improving the breakdown voltage. Is well known (see, for example, Non-Patent Document 1).

  Hereinafter, the semiconductor device disclosed in Non-Patent Document 1 will be described with reference to FIG.

  FIG. 5 is a diagram for explaining the above-described conventional semiconductor device, and shows a cut surface of a cross section of the semiconductor device taken along the gate length direction indicated by an arrow.

  The semiconductor device 119 disclosed in Non-Patent Document 1 includes a base 101 and first and second main electrodes 103a and 103b formed on the lower ground 101a of the base 101 so as to be spaced apart from each other. It is. The semiconductor device 119 includes a gate electrode 105 formed on the base surface 101a so as to be sandwiched between the first and second main electrodes 103a and 103b. Further, the first base surface protective film 107 is exposed between the gate electrode 105 and the second main electrode 103b on the base surface 101a exposed between the gate electrode 105 and the first main electrode 103a. A second base surface protection film 109 is formed on the ground surface 101a. Then, the gate electrode 105 is formed so as to be integrally covered from the upper surface 105 a to the side surface 105 b of the gate electrode 105 facing the second main electrode 103 b and the second base surface protective film 109. And a field plate 111.

  In the semiconductor device 119 described above, in such a configuration, the first main electrode 103a is used as a source electrode, and the second main electrode 103b is used as a drain electrode. As a result, when the semiconductor device 119 is driven, the electric field concentration generated between the gate electrode 105 and the second main electrode 103 b, that is, the drain electrode is caused by the side surface 105 b of the gate electrode 105 and the upper surface 109 a of the second base surface protective film 109. And the boundary 113 between the field plate 111 and the upper surface 109a of the second underlayer protection film 109, and the end 115 on the second main electrode 103b side in the gate length direction. Is done.

On the other hand, in a semiconductor device including a field plate, a structure in which a boundary surface between the field plate and the upper surface of the second base surface protective film is inclined with respect to the base surface is known (for example, Non-Patent Document 2). reference).
TECHNICICAL REPORT of IEICE ED2002-214, CPM2002-105 (2002-10) pp. 29-34 IEICE Technical Report ED2007-165, CPM2007-91, LQE2007-66 (2007-10) pp. 47-51

  However, the relaxation of the electric field concentration is insufficient only by dispersing the electric field concentration at the two points 113 and 115 described above.

  Further, in the semiconductor device disclosed in Non-Patent Document 2, the boundary surface between the field plate 111 and the upper surface of the second base surface protective film is a flat inclined surface, and the relaxation of the electric field concentration is insufficient. there were.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including a field plate that can alleviate electric field concentration between a gate electrode and a drain electrode more efficiently than a semiconductor device according to the prior art, and a manufacturing method thereof. is there.

  In order to achieve the above object, according to a first aspect of the present invention, a semiconductor device has the following characteristics.

  That is, the semiconductor device according to the first aspect includes a base and first and second main electrodes formed on the ground under the base and spaced apart from each other and facing each other. The semiconductor device according to the first aspect includes a gate electrode formed on a base surface so as to be sandwiched between the first and second main electrodes. Further, a first base surface protective film is formed on the base surface exposed between the gate electrode and the first main electrode. A second base surface protective film is formed on the base surface exposed between the gate electrode and the second main electrode. A field plate is formed so as to be integrally covered from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode and the second base surface protective film. Further, the boundary surface between the field plate and the second base surface protective film is an inclined surface curved in a convex shape toward the base surface side.

  The method for manufacturing a semiconductor device according to the first aspect of the present invention includes the following steps from a first step to a third step.

  That is, first, in the first step, the first and second main electrodes that are spaced apart from and opposed to each other on the lower ground of the base and the first and second main electrodes are sandwiched between the first and second main electrodes. The formed gate electrode, the first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode, and the base surface exposed between the gate electrode and the second main electrode A base having a second base surface protective film formed on the base is prepared.

  Next, in the second step, the second base surface protective film in the peripheral region of the gate electrode on the side facing the second main electrode is partially removed. Then, the removal region is formed by an inclined surface convexly convex toward the base surface from the upper surface of the second base surface protective film toward the gate electrode, and a side surface of the gate electrode on the side facing the second main electrode. Let it be a defined groove.

  Next, in the third step, the field plate is formed so as to cover the groove portion and to cover the entire surface from the upper surface of the gate electrode to the side surface facing the second main electrode.

  According to the second aspect of the present invention, the semiconductor device has the following characteristics.

  That is, the semiconductor device according to the second aspect includes a base and first and second main electrodes formed on the base and the ground below the base so as to be spaced apart from each other. The semiconductor device according to the first aspect includes a gate electrode formed on a base surface so as to be sandwiched between the first and second main electrodes. Further, a first base surface protective film is formed on the base surface exposed between the gate electrode and the first main electrode. A second base surface protective film is formed on the base surface exposed between the gate electrode and the second main electrode. A field plate is integrally formed covering from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode. Further, the field plate is separated from the second base surface protective film as an inclined surface in which the surface facing the base surface is concavely curved with respect to the base surface.

  A semiconductor device manufacturing method according to the second aspect of the present invention includes the following steps from a first step to a fourth step.

  That is, first, in the first step, the first and second main electrodes that are spaced apart from and opposed to each other on the lower ground of the base and the first and second main electrodes are sandwiched between the first and second main electrodes. The formed gate electrode, the first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode, and the base surface exposed between the gate electrode and the second main electrode A base having a second base surface protective film formed on the base is prepared.

  Next, in the second step, the first resist layer is a first resist layer that exposes the gate electrode and covers the first and second main electrodes and the first and second base surface protective films. The first resist layer having a thickness that gradually decreases from the region covering the gate electrode toward the gate electrode and whose surface is concavely curved with respect to the base surface is formed.

  Next, in the third step, the second resist layer covers the surface of the first resist layer, and sequentially extends from the opening end in the thickness direction of the second resist layer and reaches the surface of the first resist layer. The second resist layer is formed to expose the upper surface of the gate electrode, the side surface of the gate electrode facing the second main electrode, and the surface of the first resist layer on the side surface from the opening.

  Next, in the fourth step, a field plate is integrally covered from the upper surface of the gate electrode to the side surface facing the second main electrode of the gate electrode and the surface of the first resist layer on the side surface side. After the formation, the first and second resist layers are removed.

  In the semiconductor device according to the first aspect, the boundary surface between the field plate and the second base surface protective film is a curved inclined surface. By adopting such a structure, in the semiconductor device according to the first aspect, when the semiconductor device is driven, the electric field concentration occurs on the boundary surface that is a curved inclined surface between the field plate and the second base surface protective film. Distributed throughout. Therefore, as compared with the conventional semiconductor device (see FIG. 5) in which the electric field concentrates at the two points 113 and 115 described above, or the boundary surface 117 is a flat inclined surface, the first gist. In the semiconductor device according to, the electric field concentration between the gate electrode and the drain electrode can be relaxed more efficiently.

  In the semiconductor device according to the second aspect, the field plate is formed such that the surface facing the base surface is curved in a concave shape with respect to the base surface. Accordingly, when the semiconductor device is driven, the electric field concentration is dispersed entirely on the surface facing the base surface, while the electric field concentration between the second main electrodes used as the gate electrode and the drain electrode is distributed.

  In the semiconductor device according to the second aspect, the surface of the field plate facing the lower ground is separated from the second base surface protective film. That is, a space is formed between the surface facing the lower ground of the field plate and the upper surface of the second base surface protective film. Therefore, there is no insulating film between the field plate and the second main electrode used as the drain electrode. Therefore, the capacitance between the field plate and the second main electrode, which is generated due to the dielectric constant of the insulating film, can be suppressed.

  Therefore, in the semiconductor device according to the second aspect, the electric field concentration between the gate electrode and the second main electrode can be relaxed efficiently, and the capacitance between the field plate and the second main electrode can be reduced.

  A semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be described below with reference to the drawings. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Therefore, the configuration of the present invention is not limited to the illustrated configuration example.

<First Embodiment>
In the first embodiment, a semiconductor device including a field plate whose boundary surface with a second base surface protective film formed on the base surface is a curved inclined surface and a manufacturing method thereof will be described. This manufacturing method includes the first to third steps. Hereinafter, each step will be described in order from the first step.

  1A and 1B are process diagrams for explaining a first embodiment of the present invention. 2A and 2B are process diagrams following FIG. 1B. In each of these drawings, the structure obtained in each manufacturing stage is shown by a cut surface in a cross section taken along the gate length direction indicated by an arrow in each drawing.

  First, in the first step, a base 11 as shown in FIG.

  The base 11 is a conventionally known semiconductor substrate, for example, a base having a heterojunction surface, for example, a base on which an AlGaN layer and a GaN layer are deposited, a base on which an AlGaAs layer and a GaAs layer are deposited, or a Si substrate, A suitable substrate may be used among SOI substrates and other semiconductor substrates depending on the design. In the first embodiment, a process for manufacturing an AlGaN / GaN-HEMT will be described as an example. In view of this, the case of using a base having an AlGaN / GaN heterojunction surface as the base 11 will be illustrated and described.

  In the configuration example shown in FIG. 1A, first, the base 11 is formed of a substrate 13 made of, for example, Si, SiC, sapphire, or the like, and AlN formed by a well-known MOCVD method on the substrate 13. A buffer layer 15 such as GaN is provided. Further, on the upper side of the buffer layer 15, as an electron transit layer, a UID (Un-Intentionally-Doped: impurity-free) -GaN layer (hereinafter also simply referred to as a GaN layer) 17, and as an electron supply layer, a UID-AlGaN layer. 19 (hereinafter also simply referred to as an AlGaN layer) are sequentially formed by a well-known MOCVD method or MBE method. When such a laminated structure is formed, a two-dimensional electron gas layer (hereinafter also referred to as a 2DEG layer) is formed near the boundary between the GaN layer 17 and the AlGaN layer 19 due to the difference in energy band gap between the GaN layer 17 and the AlGaN layer 19. ) 21 is formed.

  An element isolation region 25 is formed on the base 11 for the purpose of partitioning the element region 23.

  The element isolation region 25 is formed for the purpose of electrically isolating the element regions 25 on the base 11 from each other. For example, the element isolation region 25 is formed as an ion implantation region for Ar ions or the like. In the element isolation region 25, ions are implanted from the base surface 11 a, that is, the upper surface 19 a of the AlGaN layer 19 to the lower side of the 2DEG layer 21 in order to reliably isolate each element region 23. Is formed.

  Further, the base 11 prepared in the first step includes a gate electrode 27, first and second main electrodes 29a and 29b, and first and second base surface protective films 31a and 31b.

  The first and second main electrodes are formed on the base surface 11a so as to be separated from each other and face each other. These first and second main electrodes 29a and 29b are formed by depositing, for example, Ti and Al by well-known EB (Electron Beam) vapor deposition. The first and second main electrodes 29a and 29b are in ohmic contact with the element region 23 on the contact surface with the base surface 11a. As a result, the first and second main electrodes 29a and 29b function as ohmic electrodes, one functions as a source electrode and the other functions as a drain electrode. In this embodiment, the first main electrode 29a is used as a source electrode, and the second main electrode 29b is used as a drain electrode.

  The gate electrode 27 is formed on the base surface 11a so as to be sandwiched between the first and second main electrodes 29a and 29b. The gate electrode 27 is formed by depositing, for example, Ni and Au using, for example, the well-known EB vapor deposition.

  The first base surface protection film 31a is formed to cover the base surface 11a exposed between the gate electrode 27 and the first main electrode 29a. The second base surface protective film 31b is formed to cover the base surface 11a exposed between the gate electrode 27 and the second main electrode 29b. The first and second base surface protection films 31a and 31b are formed for the purpose of preventing the base surface 11a from being contaminated during the manufacturing process of the semiconductor device according to the first embodiment. The first and second base surface protection films 31a and 31b are formed by using a known plasma CVD method, for example, with a SiN film as a material.

  Next, in the second step, as shown in FIG. 1B, the second base surface protection film 31b in the peripheral region 33 of the gate electrode 27 on the side facing the second main electrode 29b is partially removed. A simple structure.

  Here, in the first embodiment, a field plate that covers from the gate electrode 27 to the second base surface protection film 31b is formed in the third process, and the field plate drives the semiconductor device. The electric field concentration between the gate electrode and the drain electrode at the time is reduced. In the first embodiment, the boundary surface between the field plate and the second base surface protective film 31b is a curved surface, so that the electric field concentration is efficiently reduced.

  Therefore, in this second step, by the above-described removal, a region serving as a boundary surface between the field plate and the second base surface protection film 31b, that is, a peripheral region on the side of the gate electrode 27 facing the second main electrode 29b. 33 is a groove 35, and a curved inclined surface 35 a is formed on the inner wall surface of the groove 35.

  Therefore, in this second step, first, a negative resist layer 37 that covers the entire surface of the base 11 is formed by using a well-known coating technique and photolithography technique.

  The resist layer 37 functions as a mask when the peripheral region 33 is partially removed in the second step. Therefore, an opening 39 is formed in the resist layer 37 to expose the peripheral region 33 to be removed.

  Since the resist layer 37 is a negative resist layer, the opening 39 is sequentially opened in the thickness direction of the resist layer 37 from the opening end 39a by forming an opening in the resist layer 37 using a known exposure technique. The so-called reverse taper shape is obtained.

  In this embodiment, the end portion 39aa on the first main electrode 29a side along the gate length direction of the opening end 39a is in the first main direction along the gate length direction of the upper surface 27a of the gate electrode 27. The opening 39 is formed so as to be a position immediately above the end portion 27aa on the electrode 29a side or a position shifted by about 0.1 to 0.2 μm from the position just above the gate length direction. As a result, the region given by the orthogonal projection of the opening end 39 a with respect to the region exposed in the opening 39 becomes the etched region 41 including the gate electrode 27 and the peripheral region 33.

Then, using the resist layer 37 as a mask, the gate electrode 27 is left in the etched region 41 and the peripheral region 33 is selectively anisotropically etched. Therefore, in the first embodiment, for example, anisotropic etching is performed using a well-known ICP-RIE (inductively coupled plasma-reactive ion etching) method using SF ₆ as an etching gas.

  At this time, the peripheral region 33 is anisotropically etched in the thickness direction of the second base surface protection film 31b and is slightly isotropically etched by radical ions contained in the etching gas. As a result, the removed region in which the second base surface protection film 31b in the peripheral region 33 is partially removed is convex from the upper surface 31ba of the second base surface protection film 31b toward the gate electrode 27 toward the base surface 11a. The groove 35 is defined by the inclined surface 35a curved to the side and the side surface 27b of the gate electrode 27 facing the second main electrode 29b.

  Then, at the stage of forming the groove 35, the groove 35 and the side surface 27 b of the gate electrode 27 facing the second main electrode 29 b and the upper surface 27 a of the gate electrode 27 are formed in the resist layer 37. Is exposed from.

  Next, in the third step, a field plate 43 is formed to obtain a structure as shown in FIG.

  In the first embodiment, the resist layer 37 formed in the second step described above is used as a mask, for example, by depositing, for example, Ni, Pt, and Au using a known rotary evaporation method or a static evaporation method. A field plate 43 is formed. As a result, the field plate 43 is formed so as to cover the region given by the orthogonal projection of the opening end 39 a with respect to the region exposed in the opening 39, that is, the gate electrode 27 and the groove 35. Therefore, the field plate 43 is formed so as to cover the groove portion 35 and integrally cover the upper surface 27a of the gate electrode 27 from the side surface 27b on the side facing the second main electrode 29b. At this time, the material of the field plate 43 is deposited on the upper surface 37a of the resist layer 37, and the metal film 45 is undesirably formed.

  Thereafter, the resist layer 37 is removed using an organic solvent such as acetone to obtain a structure as shown in FIG. At this time, the metal film 45 is also removed together with the resist layer 37.

  The remaining field plate 43 covers the second base surface protection film 31b in the portion where the groove 35 is buried. Therefore, the curved inclined surface 35a of the groove portion 35 becomes the boundary surface 47 between the field plate 43 and the second base surface protective film 31b.

  The semiconductor device manufactured through the steps of the first embodiment described above has a first base layer 11 and a first ground layer 11 and a lower ground surface 11a of the base layer 11 which are formed to be spaced apart from each other and face each other. Main electrodes 29a and 29b are provided. The semiconductor device according to the first embodiment includes a gate electrode 27 formed on the base surface 11a so as to be sandwiched between the first and second main electrodes 29a and 29b. Further, a first base surface protective film 31a is formed on the base surface 11a exposed between the gate electrode 27 and the first main electrode 29a. A second base surface protective film 31b is formed on the base surface 11a exposed between the gate electrode 27 and the second main electrode 29b. Then, a field plate 43 is integrally formed covering the upper surface 27a of the gate electrode 27 from the side surface 27b of the gate electrode 27 facing the second main electrode 29b and the second base surface protection film 31b. Has been. Further, the boundary surface between the field plate 43 and the second base surface protection film 31b is an inclined surface that is curved in a convex shape toward the base surface 11a.

  In the semiconductor device according to the first embodiment, the boundary surface 47 between the field plate 43 and the second base surface protection film 31b is a curved inclined surface. By adopting such a structure, in the semiconductor device according to the first embodiment, when the semiconductor device is driven, the electric field concentration is caused by the curved inclined surface between the field plate 43 and the second base surface protective film 31b. The entire boundary surface 47 is dispersed. Therefore, the first embodiment is compared with the conventional semiconductor device (see FIG. 5) in which the electric field concentrates at the two points 113 and 115 described above or the boundary surface 117 is a flat inclined surface. In the semiconductor device according to the embodiment, the electric field concentration between the second main electrode 29b used as the gate electrode 27 and the drain electrode can be reduced more efficiently.

<Second Embodiment>
In the second embodiment, the field plate is integrally covered from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode, and is formed on the base surface. A semiconductor device including a field plate having a field plate spaced from the second base surface protective film, the surface facing the second base surface protective film being curved concavely with respect to the base surface, and a method for manufacturing the same To do. This manufacturing method includes the first to fourth steps. Hereinafter, each step will be described in order from the first step.

  The semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment described above in that two resist layers, that is, first and second resist layers are formed. Thus, a field plate is formed. Since other components and operational effects are the same as those of the first embodiment, the common components will be referred to by the same reference numerals and the same reference numerals will be given, and duplicate descriptions thereof will be omitted. .

  3A and 3B are process diagrams for explaining the second embodiment of the present invention. 4A and 4B are process diagrams following FIG. 3B. In each of these drawings, the structure obtained in each manufacturing stage is shown by a cut surface in a cross section taken along the gate length direction indicated by an arrow in each drawing.

  First, in the first step in the second embodiment, the first step in the first embodiment described above is performed to prepare the base 11 (see FIG. 1A).

  Next, in the second step, a first resist layer 49 is formed to obtain a structure as shown in FIG.

  In the second embodiment, first, a positive resist that covers the entire surface of the base 11 is deposited by using a well-known coating technique and photolithography technique. Thereafter, the resist is partially removed using a well-known exposure technique to form a first resist layer 49. The gate electrode 27 is exposed from the removed portion, that is, the first opening 51.

  Here, in the second embodiment, the first opening 51 is set so that the center position 51b along the gate length direction of the first opening end 51a is located immediately above the gate electrode 27. The exposure technique is used. Since the first resist layer 49 is a positive resist, the resist is partially removed by exposure, and the formed first opening 51 extends from the first opening end 51a in the thickness direction of the first resist layer 49. It becomes what is called a taper shape which shrinks sequentially. As a result, the gate electrode 27 is exposed from the first opening 51, and the first and second base surface protection films 31 a and 31 b are covered with the first resist layer 49.

  In the second embodiment, after the first opening 51 is formed, the first resist layer 49 is preferably reflowed at a temperature of 200.degree. As a result, the inner wall surface 49b of the first opening 51 and the upper surface 49c outside the first opening 51 of the first resist layer 49 become a series of surfaces 49a, which are inclined surfaces that are concavely curved with respect to the base surface 11a. It becomes.

  As a result, the first resist layer 49 exposes the gate electrode 27 from the first opening 51 and covers the first and second main electrodes 29a and 29b and the first and second base surface protective films 31a and 31b. Furthermore, the thickness gradually decreases from the region covering the first and second main electrodes 29a and 29b toward the gate electrode 27, and the surface 49a has a shape curved concavely with respect to the base surface 11a.

  Next, in the third step, a second resist layer 53 that covers the surface 49a of the first resist layer 49 is formed to obtain a structure as shown in FIG.

  In the second embodiment, in the subsequent fourth step, from the upper surface 27a of the gate electrode 27, the side surface 27b facing the second main electrode 29b, and the surface 49a of the first resist layer 49 on the side surface 27b side. A field plate is formed over the surface. Therefore, in this third step, the second resist layer 53 used as a mask is formed when the field plate is formed.

  Therefore, in the second embodiment, the second resist layer 53 is formed as a negative resist layer using a known coating technique. Then, in this second resist layer 53, a field plate formation planned region, that is, the upper surface 27a of the gate electrode 27, the side surface 27b of the gate electrode 27 facing the second main electrode 29b, and the first resist on the side surface 27b side. A second opening 55 that exposes the surface 49a of the layer 49 is formed using a known photolithography technique and exposure technique.

  Since the second resist layer 53 is a negative resist layer, the second opening 55 has a so-called reverse taper shape by forming an opening in the second resist layer 53 using a known exposure technique. That is, the second opening 55 sequentially extends from the second opening end 55 a in the thickness direction of the second resist layer 53 and reaches the surface 49 a of the first resist layer 49.

  In the second embodiment, the end 55aa on the first main electrode 29a side along the gate length direction of the second opening end 55a is along the gate length direction of the upper surface 27a of the gate electrode 27. The second opening 55 is formed so as to be a position immediately above the end portion 27aa on the first main electrode 29a side, or a position shifted from the position just above by about 0.1 to 0.2 μm along the gate length direction. .

  As a result, the region given by the orthogonal projection of the second opening end 55a with respect to the region exposed in the second opening 55 is the side surface facing the upper surface 27a of the gate electrode 27 and the second main electrode 29b of the gate electrode 27. 27b and the field plate formation scheduled region 57 including the surface 49a of the first resist layer 49 on the side surface 27b side.

  Next, in the fourth step, from the upper surface 27b of the gate electrode 27 to the side surface 27b facing the second main electrode 29b of the gate electrode 27 and the surface 49a of the first resist layer 49 on the side surface 27b side, A field plate 59 that is integrally covered is formed to obtain a structure as shown in FIG.

  In the second embodiment, as described above, the field plate is formed by depositing, for example, Ni, Pt, and Au by using the second resist layer 53 as a mask, for example, using a known rotary evaporation method or a static evaporation method. 59 is formed. Thereby, the field plate 59 has a region given by orthogonal projection of the second opening end 55a with respect to the region exposed in the second opening 55, that is, the upper surface 27a of the gate electrode 27 and the second main electrode of the gate electrode 27. The field plate formation planned region 57 is formed so as to cover the side surface 27b facing the surface 29b and the surface 49a of the first resist layer 49 on the side surface 27b side.

  The field plate 59 formed in this way is formed such that the bottom surface 59 a, that is, the surface 59 a facing the base surface 11 a rides on the surface 49 a of the first resist layer 49. As already described, the surface 49a of the first resist layer 49 is an inclined surface curved in a concave shape with respect to the base surface 11a. Accordingly, the surface 59a of the field plate 59 facing the base surface 11a is an inclined surface curved in a concave shape with respect to the base surface 11a.

  Further, when the field plate 59 is formed, the material of the field plate 59 is deposited on the upper surface 53a of the second resist layer 53, and the metal film 61 is undesirably formed.

  In the second embodiment, after the field plate 59 is formed, the first and second resist layers 49 and 53 are removed by using an organic solvent such as acetone, for example, and a structure as shown in FIG. Get.

  As described above, since the surface 59a of the field plate 59 that faces the base surface 11a is formed on the surface 49a of the first resist layer 49, the field resist 59 is removed by removing the second resist layer 53. The surface 59a of the plate 59 facing the base surface 11a is separated from the second base surface protective film 31b.

  At this time, the metal film 61 is also removed together with the first and second resist layers 49 and 53.

  The semiconductor device manufactured through the respective steps of the second embodiment described above has first and second bases 11 formed on the base 11 and the lower ground 11a of the base 11 so as to be separated from each other and face each other. Main electrodes 29a and 29b are provided. The semiconductor device according to the second embodiment includes a gate electrode 27 formed between the first and second main electrodes 29a and 29b on the base surface 11a. Further, a first base surface protective film 31a is formed on the base surface 11a exposed between the gate electrode 27 and the first main electrode 29a. A second base surface protective film 31b is formed on the base surface 11a exposed between the gate electrode 27 and the second main electrode 29b. A field plate 59 that covers the gate electrode 27 is formed from the upper surface 27a of the gate electrode 27 to the side surface 27b of the gate electrode 27 facing the second main electrode 29b. Further, the field plate 59 is separated from the second base surface protective film 31 b as an inclined surface having a surface 59 a facing the base surface 11 that is concavely curved with respect to the base surface 11.

  In the semiconductor device according to the second embodiment, the field plate 59 is formed such that a surface 59a facing the base surface 11 is curved in a concave shape with respect to the base surface 11a. Accordingly, when the semiconductor device is driven, the electric field concentration is dispersed entirely on the surface 59a facing the base surface 11a, while the electric field concentration between the gate electrode 27 and the second main electrode 29b used as the drain electrode is dispersed.

  In the semiconductor device according to the second embodiment, the surface 59a facing the lower ground 11 of the field plate 59 is separated from the second base surface protective film 31b. That is, a space is formed between the surface 59a facing the lower ground 11a of the field plate 59 and the upper surface 31ba of the second base surface protection film 31b. Therefore, there is no insulating film between the field plate 59 and the second main electrode 29b used as the drain electrode. Therefore, the capacitance between the field plate 59 and the second main electrode 29b, which is generated due to the dielectric constant of the insulating film, can be suppressed.

  Therefore, in the semiconductor device according to the second embodiment, the electric field concentration between the gate electrode 27 and the second main electrode 29b can be relaxed efficiently, and the capacitance between the field plate 59 and the second main electrode 29b can be reduced. Can be reduced.

(A) And (B) is process drawing explaining 1st Embodiment of this invention. (A) And (B) is process drawing following FIG. 1 (B) explaining the 1st Embodiment of this invention. (A) And (B) is process drawing explaining 2nd Embodiment of this invention. (A) And (B) is process drawing following FIG. 3 (B) explaining the 2nd Embodiment of this invention. It is a figure explaining the semiconductor device by a prior art.

Explanation of symbols

11, 101: Base 13: Substrate 15: Buffer layer 17: UID-GaN layer (GaN layer)
19: UID-AlGaN layer (AlGaN layer)
21: Two-dimensional electron gas layer 23: Element region 25: Element isolation region 27, 105: Gate electrode 29a, 103a: First main electrode 29b, 103b: Second main electrode 31a, 107: First base surface protective film 31b, 109: second base surface protective film 33: peripheral region 35: groove 35a: inclined surface 37: resist layer 39: opening 41: etched region 43, 59, 111: field plate 45, 61: metal film 47, 117: Boundary surface 49: first resist layer 51: first opening 53: second resist layer 55: second opening 57: field plate formation planned region 113, 115: end 119: semiconductor device

Claims (4)

The groundwork,
First and second main electrodes formed on the lower ground of the base so as to be spaced apart from each other and facing each other;
A gate electrode formed between the first main electrode and the second main electrode on the base surface;
A first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode; and a base surface exposed between the gate electrode and the second main electrode. A formed second base surface protective film;
A field plate formed by integrally covering from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode and the second base surface protective film; With
2. A semiconductor device according to claim 1, wherein a boundary surface between the field plate and the second base surface protective film is an inclined surface that is convexly curved toward the base surface. The groundwork,
First and second main electrodes formed on the lower ground of the base so as to be spaced apart from each other and facing each other;
A gate electrode formed between the first main electrode and the second main electrode on the base surface;
A first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode; and a base surface exposed between the gate electrode and the second main electrode. A formed second base surface protective film;
A field plate formed by integrally covering from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode;
The semiconductor device according to claim 1, wherein a surface of the field plate facing the base surface is separated from the second base surface protective film as a slope that is concavely curved with respect to the base surface. A first and a second main electrode formed on the lower ground of the base so as to be spaced apart from each other; a gate electrode formed on the base surface and sandwiched between the first and second main electrodes; A first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode; and a base surface exposed between the gate electrode and the second main electrode. A first step of preparing the base comprising a second base surface protective film formed;
By partially removing the second base surface protective film in the peripheral region of the gate electrode on the side facing the second main electrode, the removed region is formed on the upper surface of the second base surface protective film. A second step of forming a groove defined by an inclined surface convexly convex toward the base surface side from the gate electrode and a side surface of the gate electrode facing the second main electrode; ,
A third step of embedding the groove and forming a field plate so as to be integrally covered from the upper surface of the gate electrode to the side surface facing the second main electrode. A method for manufacturing a semiconductor device. A first and a second main electrode formed on the lower ground of the base so as to be spaced apart from each other; a gate electrode formed on the base surface and sandwiched between the first and second main electrodes; A first base surface protective film formed on the base surface exposed between the gate electrode and the first main electrode; and a base surface exposed between the gate electrode and the second main electrode. A first step of preparing the base comprising a second base surface protective film formed;
A first resist layer that exposes the gate electrode and covers the first and second main electrodes and the first and second base surface protective films, from a region covering the first and second main electrodes A second step of forming the first resist layer, the thickness of which gradually decreases toward the gate electrode, and the surface of which is curved concavely with respect to the base surface;
A second resist layer covering the surface of the first resist layer, the gate extending from an opening extending in the thickness direction of the second resist layer sequentially from an opening end to the surface of the first resist layer; A third step of forming an upper surface of the electrode, a side surface of the gate electrode facing the second main electrode, and the second resist layer exposing the surface of the first resist layer on the side surface side;
A field plate is integrally formed from the upper surface of the gate electrode to the side surface of the gate electrode facing the second main electrode and the surface of the first resist layer on the side surface side. And a fourth step of removing the first and second resist layers.

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