JP2010251540A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a semiconductor device by a small number of processes, and to relax a field concentration in the vicinity of a gate electrode. <P>SOLUTION: First and second insulating films 13 and 15 are sequentially formed on a foundation 11, a first opening pattern and the first insulating film are exposed from a surface in the second insulating film and a second opening pattern having a length along the first direction of an opening end shorter than the first opening pattern is formed. A second opening 21 continuing from the first opening and having the length along the first direction at the opening end shorter than the first opening 19 and a foundation surface continuing from the second opening are exposed by partially removing the first insulating film from an exposed surface from the first opening 19 and the first and second opening patterns by expanding the first opening pattern along the thickness direction. A third opening 23 having the length along the first direction at the opening end shorter than the second opening is formed, and an opening 17 for forming an electrode containing the first to third openings is embedded while the electrode coating the surface of the second insulating film in the periphery of the opening for forming the electrode is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which electric field concentration near a gate electrode is mitigated during operation, and a method for manufacturing the same.

  As is well known, in recent years, a two-dimensional electron gas (hereinafter also referred to as 2DEG) layer has been used as a current path as a semiconductor device that realizes excellent electronic elements in terms of high-temperature operation, high-speed switching operation, high-power operation, and the like. HEMT (High Electron Mobility Transistor) has been attracting attention. In such a HEMT, for example, in a HEMT using a compound such as GaN (gallium nitride), a structure in which electric field concentration in the vicinity of the gate electrode can be relaxed while driving a transistor and avoiding element breakdown. is necessary.

  Thus, in order to alleviate such electric field concentration, conventionally, the electric field concentration is dispersed by increasing the number of locations where the electric field concentrates in the vicinity of the gate electrode.

  For this purpose, for example, a structure of a semiconductor device in which electric field concentration in the vicinity of a gate electrode is reduced by providing a field plate is well known (for example, see Patent Document 1).

  In the technique disclosed in Patent Document 1, an opening that exposes the substrate surface is formed in an insulating film formed on the substrate, and the gate electrode is formed by filling this opening. A field plate is formed from the surface of the gate electrode to the side surface of the gate electrode on the drain electrode side and the surface of the insulating film on the drain electrode side. As a result, in the technique disclosed in Patent Document 1, the location where the electric field concentrates is the drain electrode side end at the interface between the gate electrode and the substrate, and the drain side at the interface between the field plate and the insulating film. It is dispersed at two points at the end to ease the concentration of the electric field.

  In this way, by increasing the portion where the electric field concentrates and dispersing the concentration of the electric field in each of the portions, the electric field strength at the location where each electric field concentrates can be reduced.

  In view of this, in order to further reduce the electric field concentration near the gate electrode, the distribution of the electric field concentration location between the gate electrode and the substrate or the insulating film formed on the substrate is dispersed over a wide area. A technique for reducing the peak electric field intensity (that is, the maximum value of the electric field intensity) in this region is well known (see Non-Patent Document 1, for example).

  In the technique disclosed in Non-Patent Document 1, an opening having a plurality of steps in the inner wall surface is formed in an insulating film formed on a substrate, and the gate electrode is formed by filling the opening. As a result, a plurality of corner portions corresponding to the above-described stepped inner wall surface are formed at the boundary surface between the gate electrode and the insulating film, and each of these corner portions is a place where the electric field is concentrated. Therefore, in the structure according to Non-Patent Document 1, the portions where the electric field concentrates are dispersed, and the concentration of the electric field is alleviated.

  As described above, in the technique disclosed in Non-Patent Document 1, the electric field concentration is dispersed by increasing the corners where the electric field concentrates, and as a result, the electric field strength at each electric field concentration portion is reduced. Therefore, the concentration of the electric field is reduced as the number of steps of the stepped inner wall surface is increased, that is, as the inner wall surface is brought closer to a curved inclined surface.

JP 2004-200248 A

2008 Microwave Workshop Exhibition (MWE 2008) Microwave Workshop Digest (WS9-1 p.219-224)

  However, in order to increase the number of steps of the stepped inner wall surface described above, it is necessary to perform a plurality of photolithography processes and etching processes corresponding to the number of steps on the insulating film on the substrate when forming the opening. There is. For example, in order to make the inner wall surface of the opening formed in the insulating film into a three-step staircase shape, a photolithography process for forming a resist layer with an opening pattern and etching the insulating film using the resist layer as a mask The etching process is repeated three times.

  Therefore, a great amount of labor and time are spent to form a gate electrode in which electric field concentration is reduced by forming the boundary surface with the insulating film into a plurality of steps.

  Accordingly, an object of the present invention is to provide a semiconductor device that can be manufactured with a small number of steps, more specifically by performing a single photolithography step, and in which the electric field concentration near the gate electrode is reduced, and a method for manufacturing the same. It is to provide.

  In order to achieve the above object, a semiconductor device according to the present invention has the following characteristics.

  That is, the semiconductor device according to the present invention includes a base and first and second insulating films sequentially formed so as to cover the ground under the base. The first and second insulating films are formed with electrode forming openings that continuously pass through the first and second insulating films and expose the base surface. Furthermore, the semiconductor device according to the present invention includes an electrode that embeds the electrode forming opening and covers the surface of the second insulating film around the electrode forming opening.

  The electrode forming opening includes a first opening, a second opening, and a third opening.

  The first opening is formed so as to penetrate from the upper surface of the second insulating film to the middle in the thickness direction of the second insulating film.

  The second opening is formed continuously from the middle in the thickness direction of the second insulating film to the middle of the first insulating film continuously from the first opening. The second opening has a shorter length along the first direction of the opening end than the first opening.

  The third opening is formed continuously from the second opening and penetrating through the first insulating film in the middle of the thickness direction of the first insulating film. The third opening has a shorter length along the first direction of the opening end than the second opening.

  Further, the inner wall surface in the electrode forming opening has a three-step shape on both sides along the first direction.

  The method for manufacturing a semiconductor device according to the present invention includes the following steps from the first step to the fourth step.

  That is, first, in the first step, first and second insulating films covering the underlying ground of the base are sequentially formed on the base.

  Next, in the second step, the first opening pattern and the surface of the first insulating film are exposed to the second insulating film from the surface of the second insulating film, and the opening end of the second insulating film is closer to the opening end than the first opening pattern. A second opening pattern having a short length along one direction is simultaneously formed.

  In the second step, the first opening pattern and the second opening pattern are formed using the resist layer on which the resist opening pattern is formed as a mask.

  Next, in the third step, the first opening pattern is enlarged along the thickness direction of the second insulating film, whereby the first insulating portion is exposed from the exposed surface of the first insulating film through the first opening portion and the second opening pattern. By removing the film partially, the film continuously penetrates from the middle of the second insulating film in the thickness direction to the middle of the first insulating film in the thickness direction, and is open from the first opening. A second opening having a short length along the first direction, and a base surface exposed by penetrating through the first insulating film from the middle of the thickness direction of the first insulating film continuously from the second opening. And a third opening having a shorter length along the first direction of the opening end than the second opening is formed.

  In the third step, using the resist layer and a metal film formed on the resist layer and narrowing the opening end of the resist opening pattern from both sides along the first direction, the first opening, A second opening and a third opening are formed.

  Next, in the fourth step, the electrode forming opening including the first opening, the second opening, and the third opening is embedded, and the surface of the second insulating film around the electrode forming opening is covered. An electrode to be formed is formed.

  In the semiconductor device according to the present invention, the electrode forming opening is configured by the length along the first direction of the opening end, that is, the first opening, the second opening, and the third opening having different opening lengths. Yes. Thus, the inner wall surface in the electrode forming opening has a three-step shape on both sides along the first direction. Each of the electric field concentration portions corresponding to the three-step inner wall surface is provided by embedding the electrode forming opening and covering the surface of the second insulating film around the electrode forming opening. And an end portion at the interface between the electrode and the second insulating film.

  Therefore, in the semiconductor device according to the present invention, when the device is driven, the electric field concentration is dispersed in the electric field concentration portions and the end portions, and the electric field concentration is alleviated.

  In the semiconductor device according to the present invention, the electrode is curved in a convex shape toward the base surface at the boundary surface with the second insulating film in the first opening and the boundary surface with the first insulating film in the second opening. Including an inclined surface. Therefore, when the device is driven, the electric field concentration is alleviated at these boundary surfaces, so that the electric field concentration is alleviated.

  Thus, in the semiconductor device according to the present invention, by forming the inner wall surface of the electrode forming opening in a three-step shape, the electric field concentration is distributed to each electric field concentration portion corresponding to the step shape, and further, the bending By providing the inclined surfaces, the electric field strength is dispersed over the entire inclined surfaces, so that the electric field concentration can be efficiently reduced.

  According to the method for manufacturing a semiconductor device according to the present invention, as described above, in the second step, the first opening pattern and the second opening pattern are formed using the resist layer on which the resist opening pattern is formed as a mask. To do. Then, in the third step, the same resist layer as that used in the second step and a metal film that narrows the opening end of the resist opening pattern are used as a mask, and the opening length is determined from the first opening pattern and the second opening pattern. Different first openings, second openings, and third openings are formed.

  Therefore, according to the method for manufacturing a semiconductor device of the present invention, the first opening, the second opening, and the third opening can be formed by using only one resist layer. Therefore, the above-described first opening, second opening, and third opening can be formed by performing the photolithography process for forming the resist layer only once. Therefore, according to the method for manufacturing a semiconductor device according to the present invention, a semiconductor device with reduced electric field concentration can be manufactured with a small number of steps.

It is the schematic explaining the 1st Embodiment of this invention, and is an end view which shows the cut surface which cut the semiconductor device by 1st Embodiment in the thickness direction along the gate length direction. (A) And (B) is process drawing explaining the manufacturing method of the semiconductor device by 1st Embodiment of this invention. (A) And (B) is a flowchart explaining the manufacturing method of the semiconductor device by the 1st Embodiment of this invention, and is a flowchart following FIG. 2 (B). (A) And (B) is process drawing explaining the manufacturing method of the semiconductor device by 1st Embodiment of this invention, and is process drawing following FIG. 3 (B). FIG. 5 is a process diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention, and is a process diagram following FIG. 4 (B); It is the schematic explaining the modification of this invention, and is an end view which shows the cut surface which cut the semiconductor device by a modification along the gate length direction in the thickness direction.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Therefore, the configuration of the present invention is not limited to the illustrated configuration example.

<First Embodiment>
In the first embodiment, there are provided an electrode forming opening having three steps on both sides along the first direction of the inner wall surface, and an electrode formed by embedding the electrode forming opening. A semiconductor device and a manufacturing method thereof will be described.

  In the first embodiment, a configuration example when the electrode is a gate electrode will be described. The gate length direction of the semiconductor device according to the first embodiment is defined as the first direction. Therefore, hereinafter, the electrode is also referred to as a gate electrode, the electrode formation opening is referred to as a gate formation opening, and the first direction is also referred to as a gate length direction.

  FIG. 1 is a schematic diagram for explaining a first embodiment of the present invention, in which a semiconductor device according to the first embodiment is cut in a thickness direction along a gate length direction indicated by an arrow in the drawing. FIG.

  The semiconductor device 10 according to the first embodiment includes a base 11.

  The base 11 is a conventionally known semiconductor substrate, for example, a substrate having a hetero-connection surface, for example, a substrate in which an AlGaN layer and a GaN layer are stacked on a Si substrate, or an AlGaAs layer and a GaAs layer are stacked on a Si substrate. A substrate or the like, or a Si substrate, an SOI substrate, or another semiconductor substrate may be used depending on the design.

  In addition, the semiconductor device 10 according to the first embodiment includes a first insulating film 13 and a second insulating film 15 that are sequentially formed so as to cover the lower ground 11 a of the base 11.

The first insulating film 13 and the second insulating film 15 are provided on the base surface 11a as a protective film for protecting the base 11 from contamination or suppressing the generation of surface charges. A second insulating film 15 is laminated on the upper surface 13 a of the first insulating film 13. Therefore, the first insulating film 13 and the second insulating film 15 are formed using, for example, a SiN film, a SiO ₂ film, or a SiON film.

  Further, the first and second insulating films 13 and 15 are continuously formed through the first and second insulating films 13 and 15 to expose the base surface 11a, that is, a gate formation. Opening 17 is formed.

  The gate forming opening 17 includes a first opening 19, a second opening 21, and a third opening 23 that are continuous in the thickness direction.

  The first opening 19 is formed so as to penetrate from the upper surface 15 a of the second insulating film 15 to the middle of the second insulating film 15 in the thickness direction.

  Further, the second opening 21 is formed continuously from the first opening 19 so as to penetrate from the middle of the second insulating film 15 in the thickness direction to the middle of the first insulating film 13. The length along the gate length direction of the opening end 21a of the second opening portion 21, that is, the second opening length L2, is the length along the gate length direction of the opening end 19a of the first opening portion 19, ie, It is set shorter than the first opening length L1.

  The third opening 23 is formed continuously from the second opening 21 so as to penetrate the first insulating film 13 in the middle of the thickness direction of the first insulating film 13. The length along the gate length direction of the opening end 23a of the third opening 23, that is, the third opening length L3 is set to be shorter than the opening length L2 of the second opening 21.

  As described above, the first opening 19, the second opening 21, and the third opening 23 in which the respective opening lengths L1, L2, and L3 are set are configured. The side surface 15b of the second insulating film 15 in the first opening 19, the side surface 15c of the second insulating film 15 in the second opening 21, the side surface 13b of the first insulating film 13 in the second opening 21, and the third The gate forming inner wall surface 17a constituted by the side surface 13c of the first insulating film 13 in the opening 23 has a three-stepped shape on both sides along the gate length direction.

  The gate forming opening 17 includes an inclined surface 15ba in which the side surface 15b of the second insulating film 15 in the first opening 19 is curved convexly toward the base surface 11a.

  The gate forming opening 17 includes an inclined surface 13ba in which the side surface 13b of the first insulating film 13 in the second opening 21 is curved convexly toward the base surface 11a.

  These inclined surfaces 13b and 15b are preferably smooth surfaces, and it is better to disperse the electric field more effectively.

  An electrode 25 that fills the gate forming opening 17 and covers the upper surface 15a of the second insulating film 15 around the gate forming opening 17, that is, the gate electrode 25 is formed.

  The gate electrode 25 is in contact with the base 11 on the exposed surface 11 b of the base 11 from the gate forming opening 17. The gate electrode 25 is in Schottky junction with the base 11 at the exposed surface 11 b of the base 11, that is, at the boundary surface 11 b between the gate electrode 25 and the base 11. The gate electrode 25 is made of a metal corresponding to the material constituting the base 11 in order to form a Schottky junction with the base 11. For example, when a compound semiconductor substrate whose uppermost layer is a GaN layer is used as the base 11, it is preferable that the gate electrode 25 is formed using a metal such as Ni, Au, or Pt, for example.

  Further, as described above, the inner wall surface 17 a in the gate forming opening 17 has the first opening 19, the second opening 21, and the third opening 23 constituting the gate forming opening 17. Due to the difference between the respective opening lengths L1, L2, and L3, there are three steps on both sides along the gate length direction. Therefore, in the gate electrode 25, three electric field concentration portions are formed on the boundary surface with both inner wall surfaces 17 a corresponding to the three-step inner wall surfaces 17 a of the gate forming opening 17.

  That is, the boundary surface between the gate electrode 25 and the side surface 13 c of the first insulating film 13 in the third opening 23, that is, the boundary surface 13 c, and the boundary surface between the gate electrode 25 and the exposed surface 11 b of the base 11, that is, the boundary surface Electric field concentration portions 27a and 27b are formed at the corner formed by 11b by the intersection of both boundary surfaces.

  Further, due to the step between the second opening 21 and the third opening 23, the boundary surface 15c between the second insulating film 15 and the gate electrode 25, the first insulating film 13 and the gate electrode are formed in the second opening 21. An intersection occurs between the boundary 25 and the boundary surface 13b, and electric field concentration portions 29a and 29b are formed at the intersection.

  Further, due to the step between the first opening 19 and the second opening 21, electric field concentration portions 31 a and 31 b are formed on the boundary surface 15 b between the gate electrode 25 and the second insulating film 15 in the first opening 19. Has been.

  Further, in the semiconductor device 10 according to the first embodiment, since the gate electrode 25 is formed so as to cover the upper surface 15a of the second insulating film 15 around the gate forming opening 17, the gate electrode 25 and End portions 33a and 33b, that is, electric field concentration portions 33a and 33b are formed on both sides of the boundary surface between the upper surfaces 15a of the second insulating film 15 along the gate length direction.

  As described above, the side surface 15b of the second insulating film 15 in the first opening 19 includes the inclined surface 15ba that is curved in a convex shape toward the base surface 11a. Further, the side surface 13b of the first insulating film 13 in the second opening 21 includes an inclined surface 13ba that is curved convexly toward the base surface 11a. Therefore, the gate electrode 25 formed by embedding them has an inclined surface 15ba in which the boundary surface with the second insulating film in the first opening 19, that is, the side surface 15b is curved convexly toward the base surface 11a. Is included. Further, the gate electrode 25 includes an inclined surface 13ba in which the boundary surface with the first insulating film 13 in the second opening portion 21, that is, the side surface 13b is curved convexly toward the base surface 11a.

  As described above, in the semiconductor device 10 according to the first embodiment, the gate forming opening 17 includes the first opening 19, the second opening 21, and the third opening 23 having different opening lengths. As a result, the inner wall surface 17a in the gate forming opening 17 has a three-step shape on both sides along the gate length direction. Then, the gate electrode 25 is provided by embedding the gate forming opening 17 and covering the upper surface 15a of the second insulating film 15 around the gate forming opening 17, thereby providing a three-step staircase inner wall surface. The electric field concentration portions corresponding to 17a, that is, the electric field concentration portions 27a and 27b, the electric field concentration portions 29a and 29b, the electric field concentration portions 31a and 31b, and the end portion 33a of the boundary surface between the gate electrode 25 and the second insulating film 15 And 33b, that is, the electric field concentration portions 33a and 33b are formed as locations where the electric field is dispersed and concentrated.

  Therefore, in the semiconductor device 10 according to the first embodiment, during the driving of the device, the electric field concentration portions 27a and 27b, the electric field concentration portions 29a and 29b, the electric field concentration portions 31a and 31b, and the electric field concentration portions 33a and 33b. Of these, the electric field concentration is dispersed in four electric field concentration portions arranged on the drain electrode (not shown) side, and the electric field concentration is alleviated.

  In the semiconductor device 10 according to the first embodiment, the gate electrode 25 includes the boundary surface 15 b with the second insulating film in the first opening 19 and the first insulating film 13 in the second opening 21. The boundary surface 13b includes inclined surfaces 15ba and 13ba that are convexly curved toward the base surface 11a. For this reason, when the device is driven, the electric field concentration is alleviated on these boundary surfaces 13b and 15b, so that the electric field concentration is alleviated.

  As described above, in the semiconductor device 10 according to the first embodiment, by forming the inner wall surface 17a of the gate forming opening 17 in a three-step shape, the electric field concentration is dispersed in four places and further curved. By providing the inclined surface, the electric field intensity at the boundary surfaces 13b and 15b is dispersed over the entire boundary surfaces 13b and 15b, so that the electric field concentration can be efficiently reduced.

  Next, a method for manufacturing the semiconductor device 10 according to the first embodiment will be described. This manufacturing method includes each step from the first step to the fourth step. Hereinafter, each step will be described in order from the first step.

  2A and 2B are process diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS. 3A and 3B are process diagrams for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention, and are process charts following FIG. 2B. FIGS. 4A and 4B are process diagrams for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention, and are process charts following FIG. 3B. FIG. 5 is a process diagram for explaining the semiconductor device manufacturing method according to the first embodiment of the present invention, and is a process diagram following FIG. 4 (B). In each of these drawings, the structure obtained in each manufacturing process is shown by a cut surface cut in the thickness direction of the substrate. It is an end view which shows the cut end cut off in the thickness direction along the gate length direction of the semiconductor device manufactured.

  First, in the first step, first and second insulating films 13 and 15 covering the lower ground 11a of the base 11 are sequentially formed on the base 11 to obtain a structure as shown in FIG. .

  As described above, the base 11 is a conventionally known semiconductor substrate, for example, a substrate having a hetero-connection surface, for example, a substrate in which an AlGaN layer and a GaN layer are stacked on a Si substrate, an AlGaAs layer on a Si substrate, and the like. A substrate or the like on which a GaAs layer is laminated, a Si substrate, an SOI substrate, or another semiconductor substrate may be used according to the design.

Then, on such a base 11, first and second insulating films 13 and 15 are formed on the base surface 11a as a protective film for protecting the base 11 from contamination or suppressing the generation of surface charges. . Therefore, in the first embodiment, for example, a well-known PE-CVD method or thermal CVD method is used, and the first and second insulating films 13 and 15 are made of, for example, a SiN film, a SiO ₂ film, or a SiON film. Is preferably formed.

  By the way, in the first embodiment, in order to disperse the electric field concentration in the vicinity of the gate electrode when the manufactured semiconductor device is driven, a plurality of electric field concentration portions are provided in the first and second insulating films 13 and 15. An opening for forming a gate is formed. Therefore, in the first embodiment, the first and second insulating films 13 and 15 are individually etched in the subsequent second step and third step. Therefore, in order to selectively etch the first and second insulating films 13 and 15, respectively, in this first step, the etching rate value of the second insulating film 15 is equal to or higher than the etching rate value of the first insulating film 13. It is preferable to form such that

  More specifically, when it is assumed that the first insulating film 13 is etched by, for example, an ICP-RIE (inductively coupled plasma-reactive ion etching) method, the etching rate is, for example, 5 to 20 nm / min. It is preferable to form as follows. Further, when it is assumed that the second insulating film 15 is etched by, for example, an ICP-RIE method, the second insulating film 15 is preferably formed to have an etching rate of, for example, 30 to 60 nm / min. Note that these etching rate values are merely examples. For example, each material and each film thickness constituting the first and second insulating films 13 and 15 or each opening is formed in each subsequent process. It is preferable to adjust arbitrarily according to the etching conditions and the set opening length.

  Next, in the second step, the first opening pattern 35 and the second opening pattern 37 are formed.

  In this second step, in order to form the first opening pattern 35 and the second opening pattern 37, first, a resist layer 39 is formed on the second insulating film 15 by using, for example, a well-known coating technique and photolithography technique. (FIG. 2 (B)).

  In this first embodiment, a well-known so-called lift-off method is used to form a gate forming opening and a gate electrode that embeds the gate forming opening. Therefore, in this second step, the resist layer 39 is formed of a negative resist. .

  Then, in order to form the first opening pattern 35 and the second opening pattern 37 using such a resist layer 39 as a mask, the second insulating film is first formed on the resist layer 39 using a known exposure technique. A resist opening pattern 41 is formed to expose the upper surface 15a of 15 as the exposed surface 15d.

  Since the resist opening pattern 41 has the resist layer 39 formed of a negative resist as described above, the hollow portion gradually expands as the depth increases in the thickness direction of the resist layer 39 from the opening end 41a. The so-called reverse taper shape is obtained.

  Then, anisotropic etching is performed on the second insulating film 15 from the upper surface 15a of the second insulating film 15 using the resist layer 39 with the resist opening pattern 41 as a mask, so that the first opening pattern 35 and the first Each of the two opening patterns 37 is formed to obtain a structure as shown in FIG.

  In this second step, anisotropic etching is preferably performed using, for example, the well-known ICP-RIE method or ECR (electron cyclotron resonance) -RIE method.

  Then, by this anisotropic etching, the second insulating film 15 in the region given by the orthogonal projection of the opening end 41a with respect to the exposed surface 15d from the resist opening pattern 41, that is, the etched region 43 (see FIG. 2B). The second opening pattern 37 exposing the upper surface 13a of the first insulating film 13 is formed.

  At the same time, the second insulating film 15 exposed from the resist opening pattern 41 is slightly isotropically etched over the entire exposed surface 15d by radical ions contained in the etching gas plasma. As a result, in the second step, when the second opening pattern 37 is formed, the first opening pattern 35 is formed with an opening depth shallower than the second opening pattern 37 by this isotropic etching.

  As described above, the second opening pattern 37 formed by anisotropic etching is formed in the etched region 43 (see FIG. 2B) with respect to the opening end 41a of the resist opening pattern 41 and isotropically etched. The first opening pattern 35 is formed over the entire exposed surface 15d (see FIG. 2B) from the resist opening pattern 41. Accordingly, the length along the first direction of the opening end 37 a of the second opening pattern 37 is shorter than the length along the first direction of the opening end 35 a of the first opening pattern 35. The first direction is a direction that is a gate length direction in the semiconductor device 10 (see FIG. 1) manufactured according to the first embodiment. Therefore, hereinafter, the first direction is also referred to as a gate length direction, and is indicated by an arrow in each figure after FIG.

  By the way, the first opening pattern 35 and the second opening pattern 37 are expanded in the depth direction in the subsequent third step, and the first opening pattern 35 is the first opening portion 19 (see FIG. 1) described above. The second opening pattern 37 becomes the above-described second opening 21 (see FIG. 1).

  Therefore, in the second step, the first opening pattern 35 is formed such that the length along the first direction of the opening end 35a is the first opening length L1, and the second opening pattern 37 is formed using the opening end 37a. The length along the first direction is the second opening length L2.

  Therefore, the resist layer 39 used as a mask is exposed from the resist opening pattern 41 so that the length along the first direction of the resist opening pattern 41, that is, the fourth opening length becomes the second opening length L2. The length along the first direction of the exposed surface 15d is formed to be the first opening length L1 (see FIG. 2B).

  Next, in the third step, the first opening 19, the second opening 21, and the third opening 23 are formed.

  In the first embodiment, the first opening pattern 19 is enlarged in the depth direction by performing etching using the resist layer 39 formed in the second step described above as a mask again. The second opening pattern 37 is enlarged in the depth direction to partially remove the second opening 21 and the first insulating film 13, thereby forming the third opening 23.

  Here, in the first embodiment, the opening length L3 of the third opening 23 is set shorter than the opening length L2 of the second opening 21 (see FIG. 1). Therefore, first, the fourth opening length of the resist opening pattern 41 needs to be narrower than the second opening length L <b> 2 of the second opening pattern 37.

  Therefore, in this third step, first, a metal film 45 is formed on the resist layer 39 (see FIG. 3B).

  In order to narrow the fourth opening length, it is preferable to form the metal film 45 by so-called known oblique deposition. That is, by using a known vacuum vapor deposition machine, an evaporation metal molecular beam, such as Al, which is a material of the metal film 45 is applied to the resist layer from an oblique direction of 60 to 70 ° with respect to the normal direction of the base surface 11a. It deposits on the surface 39a of 39 (not shown).

  Then, by performing such oblique deposition from both sides along the gate length direction (left and right toward the paper surface of FIG. 3B), the metal film 45 is formed from the resist layer 39 surface 39a to the resist opening pattern 41. It can be formed by protruding to the open end 41a. As a result, the opening end 41a of the resist opening pattern 41 is narrowed by the metal film 45 from both sides along the first direction, that is, the gate length direction.

  As described above, in the second step, the second opening pattern 37 is formed in a region corresponding to the opening end 41a of the resist opening pattern 41 before forming the metal film 45 (FIG. 2B and FIG. 3 (A)). Therefore, in this third step, the new opening end of the resist opening pattern 41 narrowed by the metal film 45, that is, the orthogonal projection region along the lower ground 11a of the opening end 41b, that is, the etching target region 47 is the second opening. This is a region included in the exposed surface 13 d of the first insulating film 13 from the pattern 37.

  In the third step, the first opening 23 is formed by anisotropically etching the first insulating film 13 in the etched region 47. Therefore, the above-described metal film 45 is formed so that the length along the gate length direction of the opening end 41b of the resist opening pattern 41 becomes the third opening length L3 of the third opening 23 to be formed.

  Then, using the resist layer 39 with the metal film 45 as a mask, anisotropic etching is performed from the exposed surface 13d of the first insulating film 13 from the second opening pattern 37, whereby the first opening 19 and the second opening The part 21 and the third opening 23 are formed to obtain a structure as shown in FIG.

  In the third step, anisotropic etching is preferably performed using, for example, a well-known ICP-RIE method or ECR-RIE method.

  Then, by this anisotropic etching, the first insulating film 13 in the etched region 47 (see FIG. 3B) is removed, and the third opening 23 exposing the base surface 11a is formed.

  Since the third opening 23 is formed corresponding to the above-described etched region 47, the third opening length L3 of the opening end 23a of the third opening 23 is the opening end 21a of the second opening 21. Becomes shorter than the opening length L2.

  At the same time, the first opening pattern 35 is enlarged along the thickness direction of the second insulating film 15 by radical ions contained in the etching gas, and the first opening 19 is formed.

  At the same time, the exposed surface 13d of the first insulating film 13 exposed from the second opening pattern 37 is slightly isotropically etched over the entire surface by the radical ions described above. Therefore, when the third opening 23 is formed, the entire exposed surface 13 d is etched shallower than the third opening 23 by this isotropic etching. As a result, the second opening pattern 37 is enlarged in the thickness direction, and the second opening 21 is formed.

  Thus, by forming the first opening 19, the second opening 21, and the third opening 23, the first opening 19 extends from the upper surface 15 a of the second insulating film 15 to the second insulating film. The second opening 21 extends from the middle of the second insulating film 15 in the thickness direction to the middle of the first insulating film 13 in the thickness direction. The third opening 23 continues from the second opening 21 and penetrates the first insulating film 13 from the middle of the thickness direction of the first insulating film 13, that is, exposes the base surface 11a. Each is formed.

  As already described, the second opening length L2 of the second opening 21 is shorter than the first opening length L1 of the first opening 19, and the third opening length L3 of the third opening 23 is The second opening 21 is formed to be shorter than the second opening length L2.

  Thus, by setting the respective opening lengths L1, L2, and L3, the gate forming opening 17 constituted by the first opening 19, the second opening 21, and the third opening 23 can be The wall surface 17a has a three-step shape on both sides along the gate length direction.

  In the third step, as described above, the first opening pattern 35 and the second opening pattern 37 are expanded in the depth direction by isotropic etching, so that the first opening 19 and the second opening 21 is formed. As a result, the first opening portion 19 is exposed in the first opening portion 19 between the end portion 19aa of the first opening end 19a and the end portion 21aa of the second opening end 21a of the second opening portion 21. The side surface 15b of the second insulating film 15 is formed to include an inclined surface 15ba that is convexly curved toward the base surface 11a. The second opening 21 includes a vertical wall extending from the end 21aa of the second opening end 21a to the first insulating layer 13, that is, the side surface 15c, and the first insulating film 13 exposed in the second opening 21. The side surface 13b is formed including an inclined surface 13ba that is convexly curved toward the base surface 11a.

  Next, in the fourth step, the gate electrode 25 is formed.

  In the first embodiment, the gate electrode 25 is formed so as to embed the gate forming opening 17 and cover the upper surface 15 a of the second insulating film 15 around the gate forming opening 17.

  Therefore, in the fourth step, first, the metal film 45 is removed using, for example, a well-known wet etching, and then the resist opening pattern 41 is formed on both sides along the gate length direction by using a well-known oxygen ashing. Enlarge (see FIG. 4B). As the resist opening pattern 41 is enlarged by ashing, the thickness of the resist layer 39 is reduced (not shown).

  By enlarging the resist opening pattern 41, the upper surface 15 a of the second insulating film 15 around the gate forming opening 17 is exposed from the enlarged resist opening pattern 41, that is, the resist opening pattern 49.

  Then, using the resist layer 39 with the resist opening pattern 49 as a mask, the gate electrode 25 is formed by using a well-known vapor deposition technique such as, for example, rotary vapor deposition, thereby obtaining a structure as shown in FIG.

  As described above, in the resist opening pattern 49, the gate forming opening 17 and the upper surface 15 a of the second insulating film 15 around the gate forming opening 17 are exposed. The opening 17 for the gate is embedded and the upper surface 15 a of the second insulating film 15 around the opening 17 for the gate formation is covered.

  As already described, in the first embodiment, for example, when a compound semiconductor substrate whose uppermost layer is a GaN layer is used as the base 11, the gate electrode 25 is made of, for example, Ni, Au, or Pt. It is preferable to form such a metal as a material.

  Then, after the gate electrode 25 is formed, the resist layer 39 is removed using an organic solvent such as acetone, that is, lifted off, thereby obtaining the semiconductor device 10 shown in FIG.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, in the second step, the first opening pattern 35 and the second opening pattern 35 are formed using the resist layer 39 on which the resist opening pattern 41 is formed as a mask. An opening pattern 37 is formed. In the third step, the same resist layer 39 used in the second step and the metal film 45 that narrows the opening end 41a of the resist opening pattern 41 are used as a mask to form the first opening portions 19 having different opening lengths, A second opening 21 and a third opening 23 are formed.

  Therefore, according to the manufacturing method of the semiconductor device according to the first embodiment, the first opening 19, the second opening 21, and the third opening 23 are formed by using only one resist layer 39. Can do. Therefore, the first opening portion 19, the second opening portion 21, and the third opening portion 23 described above can be formed only by performing the photolithography step for forming the resist layer 39 once in the second step. . Therefore, in the method for manufacturing a semiconductor device according to the first embodiment, the semiconductor device 10 (see FIG. 1) in which electric field concentration is reduced can be manufactured with a small number of steps.

  Here, in the first embodiment, the configuration example in the case where the electrode 25 is a gate electrode has been described. However, in the first embodiment, the electrode 25 may be formed not only as a gate electrode but also as an independent field plate electrode.

  Therefore, hereinafter, as a modification of the first embodiment, a semiconductor device in which the electrode 25 described above is formed as a field plate electrode will be described.

  FIG. 6 is a schematic diagram for explaining a modification of the first embodiment, and is an end view showing a cut surface obtained by cutting a semiconductor device according to the modification along the gate length direction in the thickness direction.

  In the semiconductor device 50 according to the modification, the base configuration is changed from the base 11 (see FIG. 1) of the semiconductor device 10 according to the first embodiment described above.

  That is, in the semiconductor device 50 according to the modification, the base 53 formed by further forming the gate electrode 51 on the base 11 described above, that is, the base 53 with a gate electrode is used as the base.

  The base 53 is obtained by forming the gate electrode 51 on the base 11 described above by using a conventionally known method such as a lift-off method.

  The base 53 includes a first base insulating film 55 that covers the base surface 11a on the base 11 described above. The first base insulating film 55 is formed with an opening 63 that exposes the base surface 11a. The gate electrode 51 is formed so as to fill the opening 63 and cover the surface 55 a of the first base insulating film 55 around the opening 63. Further, a second base insulating film 57 is formed so as to cover the entire upper surface of the first base insulating film 55 including the gate electrode 51.

  Here, as described above, the base 53 is formed by filling the gate electrode 51 with the opening 63 and covering the upper surface 55a of the first base insulating film 55 around the opening 63, thereby forming two gate electrodes 51. It has an electrode concentration part.

  That is, the boundary surface between the gate electrode 51 and the side surface 55b of the first base insulating film 55 (that is, the boundary surface 55b) in the opening 63 and the boundary surface between the gate electrode 51 and the exposed surface 11c of the base 11 (that is, the boundary surface). 11c) is formed with electric field concentration portions 59a and 59b by the intersection of both boundary surfaces.

  Further, since the gate electrode 51 is formed so as to cover the upper surface 55a of the first base insulating film 55 around the opening 63, the boundary surface between the gate electrode 51 and the upper surface 55a of the first base insulating film 55 is formed. On both sides along the gate length direction, end portions 61a and 61b, that is, electric field concentration portions 61a and 61b are formed.

  Therefore, in this modification, when the device is driven, electric field concentration occurs in the two electric field concentration portions arranged on the drain electrode (not shown) side of the electric field concentration portions 59a and 59b and the electric field concentration portions 61a and 61b. scatter.

  In the semiconductor device 50 according to the modification, the first insulating film 13 similar to that of the first embodiment described above is formed on the lower ground 53a of the base 53, that is, the upper surface 57a of the second base insulating film 57. A second insulating film 15 and an electrode 25 (see FIG. 1) are formed.

  Thus, by forming the electrode 25, the electrode 25 functions as an independent field plate electrode. As described above, in the electrode 25, the electric field concentration portions 27a and 27b, the electric field concentration portions 29a and 29b, the electric field concentration portions 31a and 31b, and the electric field concentration portions 33a and 33b are on the drain electrode (not shown) side. The electric field concentration is dispersed in the four electric field concentrating portions arranged in FIG.

  Therefore, in the semiconductor device 50 according to the modification, when the device is driven, the electric field concentration portions 59a and 59b and the electric field concentration portions 61a and 61b in the base 53, and the electric field concentration portion 27a and the electric field concentration portions 27a and 61b as field plate electrodes 27b, electric field concentration portions 29a and 29b, electric field concentration portions 31a and 31b, and electric field concentration portions 33a and 33b, the electric field concentration is dispersed in six electric field concentration portions arranged on the drain electrode side, and the electric field concentration is alleviated. .

  Here, when the electrode 25 is formed as an independent field plate electrode, the electrode 25 is preferably disposed at a position shifted from the gate electrode 51 toward the drain electrode along the gate length direction. That is, the electrode 25 is arranged such that one of the electric field concentration portions 27a and 27b of the electrode 25 arranged on the drain electrode side is more than one of the electric field concentration portions 61a and 61b of the gate electrode 51 arranged on the drain electrode side. It is preferable to form it close to the drain electrode side along the gate length direction. As a result, of the electric field concentration portions 59a and 59b, the electric field concentration portions 61a and 61b, the electric field concentration portions 27a and 27b by the electrode 25, the electric field concentration portions 29a and 29b, the electric field concentration portions 31a and 31b, and the electric field concentration portions 33a and 33b. Since the six electric field concentration portions arranged on the drain electrode side are arranged in a step shape along the gate length direction, that is, in a curved and gently sloping surface shape, the electric field concentration is efficiently reduced.

  FIG. 6 shows a configuration example in the case where the drain electrode is formed on the right side of the drawing. Therefore, in the configuration example shown in FIG. 6, the electric field concentration portion 27b on the drain electrode side of the electrode 25 is on the right side of the electric field concentration portion 61b on the drain electrode side of the gate electrode 51, that is, on the drain electrode side along the gate length direction. It is shifted and arranged.

  In the semiconductor device 50 according to the modification, the electrode 25 formed as the field plate electrode is electrically connected to the gate electrode 51 by being electrically connected to the gate field plate electrode or to a source electrode (not shown). Can be used as source field plate electrodes, respectively (not shown).

  Thus, when the electrode 25 is formed as a field plate electrode, in addition to the electric field concentration portion of the gate electrode 51, four electric field concentration portions by the electrode 25 can be additionally provided. Compared with the semiconductor device 10 according to the embodiment, the electric field concentration can be relaxed more efficiently.

10, 50: Semiconductor device 11: Base 13: First insulating film 15: Second insulating film 17: Electrode forming opening (gate forming opening)
19: 1st opening 21: 2nd opening 23: 3rd opening 25: Electrode 35: 1st opening pattern 37: 2nd opening pattern 39: Resist layer 41, 49: Resist opening pattern 45: Metal film 51: Gate electrode 53: Base (base with gate electrode)
55: First base insulating film 57: Second base insulating film 63: Opening

Claims (6)

The groundwork,
First and second insulating films sequentially formed so as to cover the underlying ground of the base;
An electrode forming opening that continuously penetrates the first and second insulating films and exposes the base surface is embedded, and the surface of the second insulating film around the electrode forming opening is embedded. An electrode for coating,
The electrode forming opening is
A first opening formed penetrating from the upper surface of the second insulating film to the middle of the thickness direction of the second insulating film;
The first opening is formed so as to penetrate from the middle of the second insulating film in the thickness direction to the middle of the first insulating film, and the first direction of the opening end with respect to the first opening. A second opening having a short length along
It is formed continuously from the second opening through the first insulating film from the middle of the thickness direction of the first insulating film, and in the first direction at the opening end than the second opening. A third opening having a short length along the line,
2. A semiconductor device according to claim 1, wherein an inner wall surface in the electrode forming opening has a three-step shape on both sides along the first direction. The semiconductor device according to claim 1,
The electrode includes an inclined surface in which a boundary surface with the second insulating film in the first opening is curved convexly toward the base surface, and the first insulating film in the second opening A boundary surface of the semiconductor device includes an inclined surface curved convexly toward the base surface side. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the electrode is a gate electrode. A first step of sequentially forming first and second insulating films covering the lower ground on the lower ground;
The first opening pattern and the surface of the first insulating film are exposed to the second insulating film from the surface of the second insulating film, and the first opening pattern extends along the first direction of the opening end from the first opening pattern. A second step of simultaneously forming a second opening pattern having a short length;
The first insulating film is partially extended from the exposed surface of the first insulating film from the first opening and the second opening pattern by enlarging the first opening pattern along the thickness direction of the second insulating film. By removing the first insulating film continuously, it penetrates from the middle in the thickness direction of the second insulating film to the middle in the thickness direction of the first insulating film continuously from the first opening and opens more than the first opening. A second opening having a short length along the first direction of the end, and the second insulating part continuously through the first insulating film from the middle of the thickness direction of the first insulating film. A third step of exposing the lower ground and forming third openings each having a shorter length along the first direction of the opening end than the second opening;
An electrode forming opening including the first opening, the second opening, and the third opening is embedded, and an electrode that covers the surface of the second insulating film around the electrode forming opening is formed. And a fourth step to
In the second step, using the resist layer in which the resist opening pattern is formed as a mask, the first opening pattern and the second opening pattern are formed,
In the third step, the resist layer and a metal film formed on the resist layer and narrowing the opening end of the resist opening pattern from both sides along the first direction are used as the mask. A method for manufacturing a semiconductor device, comprising: forming an opening, the second opening, and the third opening. A method of manufacturing a semiconductor device according to claim 4,
In the third step, the first opening is formed so that a side surface of the second insulating film exposed in the first opening includes an inclined surface that is convexly curved toward the base surface side, The semiconductor device is characterized in that the second opening is formed so that a side surface of the first insulating film exposed in the second opening includes an inclined surface curved convexly toward the base surface. Device manufacturing method. A method of manufacturing a semiconductor device according to claim 4 or 5,
A method of manufacturing a semiconductor device, wherein the electrode is formed as a gate electrode.

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