JP2010021197A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently reduce concentrating electric field intensity so as to have a sufficient breakdown voltage even for a high-voltage operation and also suppress current collapse. <P>SOLUTION: A semiconductor device has a ground 11, and first and second insulating films 13 and 15 formed sequentially covering a ground surface 11a of the ground. The first and second insulating films has a hole portion 29 for gate formation formed penetrating the first and second insulating films continuously to expose the ground surface. Further, the semiconductor device has a gate electrode 33 which fills the hole portion for gate formation and covers a second insulating film surface at a periphery of the hole portion for gate formation. The hole portion for gate formation includes a first hole portion 21 bored in the first insulating film and a second hole portion 23 bored in the second insulating film larger so that an opening length in a gate length direction is larger than the first hole portion. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to MES type and MIS type semiconductor devices, and relates to a method for efficiently dispersing electric field concentration during operation.

  Conventionally, a so-called lift-off method is well known as a method for forming a metal electrode used in a semiconductor device (for example, Patent Document 1).

  That is, a resist layer having an opening having the same shape as the surface shape of the metal electrode to be formed is formed on the surface of the base on which the element is formed. Then, a metal is deposited on the entire surface of the resist layer including the openings using a technique such as vacuum evaporation. Thereafter, unnecessary metal portions deposited in regions other than the openings are removed together with the resist layer, that is, lifted off, so that the metal portions remaining in the openings remain as metal electrodes.

  By the way, as is well known, in a semiconductor device, an insulating film such as a SiN film is provided as a protective film on the surface of the base in order to protect elements formed on the base surface from contamination or suppress the generation of surface charges. It is often done. Therefore, when forming a metal electrode in a semiconductor device having this protective film, the protective film present in the metal electrode formation region is removed to expose the underlying surface.

  Next, referring to FIG. 6, a semiconductor device with a protective film disclosed in Patent Document 1 (hereinafter also referred to as a semiconductor device according to the prior art) in which a metal electrode is formed on a base by the lift-off method described above will be described. To do. FIG. 6 shows a cut end of a cross section obtained by cutting a conventional semiconductor device along the gate length direction.

  A semiconductor device according to the prior art includes a base 101 and a protective film 103 formed so as to cover the lower ground 101a of the base 101. A gate forming hole 105 that exposes the base surface 101 a is formed through the protective film 103. Then, the gate forming hole 105 is embedded, and the gate electrode 107 is formed by covering and covering the surface 103a of the protective film 103 around the gate forming hole 105.

  The semiconductor device according to the prior art is a so-called MES (Metal Semiconductor) type semiconductor device in which the gate electrode 107 and the base surface 101a are Schottky-bonded at the bottom surface 105a of the gate forming hole 105. During the operation of the semiconductor device, that is, when a voltage is applied to the gate electrode 107, the drain electrode (not shown) of the end portions 109a and 109b in the gate length direction of the contact surface between the gate electrode 107 and the base surface 101a. The electric field concentrates on the end portion on the side where the contact is formed. That is, in the configuration example of FIG. 6, when the drain electrode is formed on the left side of the paper surface, the electric field is concentrated on the end portion 109a, and when the drain electrode is formed on the right side of the paper surface, the electric field is concentrated on the end portion 109b.

  Further, in the semiconductor device according to the prior art, the gate electrode 107 is formed so as to cover the surface 103a of the protective film 103 around the gate forming hole 105, so that the gate electrode 107 can be formed when the voltage is applied. The electric field also concentrates on the end portions 111a and 111b on the side where the drain electrode is formed in the gate length direction of the portion covering the surface 103a of the protective film 103 around the gate forming hole 105. That is, in the configuration example of FIG. 6, when the drain electrode is formed on the left side of the paper, the electric field is concentrated on the end 111a, and when the drain electrode is formed on the right of the paper, the electric field is concentrated on the end 111b.

As described above, in the semiconductor device according to the prior art, the portion where the electric field concentrates when a voltage is applied is assigned not only to the end portion 109a or 109b but also to the end portion 111a or 111b. Therefore, the concentration of the electric field is distributed to each end 109a or 109b and 111a or 111b, so that the electric field strength at each end 109a, 109b, 111a, and 111b is reduced. As a result, in the semiconductor device according to this conventional technique, a structure having a good breakdown voltage against electric field concentration can be obtained.
JP 2007-67032 A

  However, when using the above-described conventional semiconductor device as a high-power electronic device operating at high voltage, it is difficult to say that the dispersion of the electric field strength concentrated on each end is sufficient in the structure of the semiconductor device according to this conventional technology. There is a risk that the breakdown voltage is insufficient.

  In addition, in a conventional semiconductor device, when operating at a high voltage, the phenomenon of so-called current collapse due to the above-described concentration of the electric field, that is, the influence of a depletion layer formed by trapping electrons on the underlying surface or the underlying surface. Therefore, there is a high possibility that the drain current will decrease.

  Further, in a so-called MIS (Metal Insulator Semiconductor) type semiconductor device, that is, a semiconductor device having a structure in which a gate electrode is formed on a base via a gate insulating film, a protective film is formed after the gate electrode is formed. Therefore, in the MIS type semiconductor device, the protective film is formed so as to cover the gate electrode. Therefore, unlike the MES type semiconductor device having the above-described conventional structure, the gate electrode does not have a shape that fills the gate forming hole formed in the protective film and rides on the surface of the protective film around the gate forming hole. Therefore, in the MIS type semiconductor device, the electric field concentrates only at the end portion of the contact surface between the gate electrode and the base in the gate length direction, so that the breakdown voltage is less than that of the MES type semiconductor device, and the current collapse is reduced. Is likely to occur.

  An object of the present invention is to provide a MES type semiconductor and a MIS type semiconductor that have a sufficient breakdown voltage even when operated at a high voltage and can reduce the concentration of concentrated electric field more efficiently in order to suppress current collapse. It is to propose a structure of a device and a manufacturing method thereof.

  In order to achieve the above object, according to the first aspect of the present invention, the MES type semiconductor device has the following features.

  In other words, the MES type semiconductor device according to the first aspect includes a base and first and second insulating films sequentially formed so as to cover the ground under the base. The first and second insulating films are formed with gate forming holes that continuously penetrate the first and second insulating films and expose the base surface. Further, the MES type semiconductor device includes a gate electrode that fills the hole for forming the gate and covers the surface of the second insulating film around the hole for forming the gate. The gate forming hole includes a first hole formed in the first insulating film and a second hole formed in the second insulating film and having a larger opening length in the gate length direction than the first hole. including.

  A manufacturing method of a MES type semiconductor device according to the first aspect of the present invention includes the following steps from the first step to the fourth step.

  That is, first, in the first step, first and second insulating films are sequentially formed on the base surface.

  Next, in the second step, the first insulating film is exposed so that the second insulating film has an opening pattern having a rectangular or tapered planar shape cut in the thickness direction of the base along the gate length direction. To form.

  Next, in the third step, in the region of the first insulating film exposed from the hole pattern, the first hole part that exposes the base surface is formed and the hole pattern is expanded. A second hole having a larger opening length in the gate length direction than the first hole is formed.

  Next, in the fourth step, a gate electrode that covers the surface of the second insulating film around the second hole is formed while the gate forming hole including the first and second holes is embedded.

  According to the second aspect of the present invention, the MIS type semiconductor device has the following characteristics.

  That is, the MIS type semiconductor device according to the second aspect includes a base, and first and second insulating films sequentially formed so as to cover the ground under the base. A gate forming hole is formed through the second insulating film to expose the surface of the first insulating film. Further, the MIS type semiconductor device includes a gate electrode that fills the hole for forming the gate and covers the surface of the second insulating film around the hole for forming the gate.

  A method for manufacturing an MIS type semiconductor device according to the second aspect of the present invention includes the following steps from the first step to the third step.

  That is, in the first step, the first and second insulating films are sequentially formed on the base surface.

  Next, in the second step, the first insulating film is exposed so that the second insulating film has an opening pattern having a rectangular or tapered planar shape cut in the thickness direction of the base along the gate length direction. To form.

  Next, in the third step, a gate electrode that fills the opening pattern and covers the surface of the second insulating film around the opening pattern is formed.

  In the MES type semiconductor device according to the first aspect and the MES type semiconductor device manufactured by the manufacturing method, the gate length is increased by forming continuous opening portions in the first and second insulating films in different processes. It is possible to form a gate forming hole including the first and second holes having different opening lengths in the direction. Then, when opening the first hole, the second hole is expanded so that the opening length in the gate length direction (hereinafter also simply referred to as the opening length) is larger than the first hole. A corner is formed on the inner wall surface of the two holes. As a result, in the semiconductor device according to the first aspect, during operation, each of the above-described end portions, that is, the end portion in the gate length direction of the contact surface between the gate electrode and the base surface, and the protective film around the gate forming hole portion In addition to the end portion in the gate length direction of the portion covering the surface of the insulating film (that is, the insulating film), the electric field concentrates on the corner portion formed on the inner wall surface of the second hole portion. Therefore, since the semiconductor device according to the first aspect has more places where the electric field concentrates than the semiconductor device according to the prior art, each concentrated electric field is dispersed. As a result, the electric field strength at each of these locations is further reduced. Therefore, in the semiconductor device according to the first aspect, the electric field strength is more efficiently distributed as compared with the semiconductor device according to the prior art. Therefore, it can be said that the semiconductor device according to the first aspect has a structure that exhibits a good breakdown voltage even when operated at a high voltage, suppresses the occurrence of current collapse, and further reduces the gate leakage current.

  In the semiconductor device according to the first aspect, the gate electrode is in contact with the base at the bottom surface of the first hole. Therefore, in the semiconductor device according to the first aspect, the length of the bottom surface of the first hole in the gate length direction is the gate length. In the semiconductor device and the manufacturing method according to the first aspect, when the first hole is formed in the first insulating film using the hole pattern, the second insulating film with the hole pattern functions as a mask. . Further, the opening pattern is formed so that the planar shape cut in the thickness direction of the base along the gate length direction is rectangular or tapered. Therefore, in the semiconductor device and the manufacturing method according to the first aspect, by appropriately setting the opening length of the opening pattern, the length of the bottom surface in the gate length direction is not expanded from a desired value, and the first hole portion is formed. Can be formed. Therefore, in the semiconductor device and the manufacturing method according to the first aspect, a semiconductor device in which a desired gate length value is accurately set can be manufactured.

  Further, in the MIS type semiconductor device according to the second aspect and the MIS type semiconductor device manufactured by the manufacturing method, the opening pattern formed in the second step of the first aspect is used as the gate forming hole portion. The first insulating film functions as a gate insulating film. Thus, in the semiconductor device according to the second aspect, the gate electrode that forms the MIS type semiconductor device, embeds the gate forming hole, that is, the hole pattern, and covers the surface of the second insulating film around the hole pattern. Is forming. As a result, in the semiconductor device according to the second aspect, in operation, in addition to the end in the gate length direction of the contact surface between the gate electrode and the first insulating film, The electric field also concentrates at the end in the gate length direction of the portion covering the surface of the second insulating film 15 around the opening pattern 17.

  Therefore, the semiconductor device manufactured according to the second aspect is more efficient in electric field strength than the MIS type semiconductor device having a conventional structure in which the electric field is concentrated only at the end portion of the contact surface between the gate electrode and the base. Distributed. Therefore, the semiconductor device manufactured according to the second gist exhibits a good breakdown voltage even when operated at a high voltage as compared with the MIS type semiconductor device having a conventional structure, and the occurrence of current collapse is suppressed. Further, it can be said that the gate leakage current is reduced.

  Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device according to embodiments of the present invention will be described with reference to the drawings. Each drawing merely schematically shows the shape, size, and arrangement relationship of each component to the extent that the present invention can be understood. Therefore, the configuration of the present invention is not limited to the illustrated configuration example.

<First Embodiment>
In the first embodiment, a MES type semiconductor device, that is, a semiconductor device in which a gate electrode and a base surface are Schottky bonded, and a gate formed by continuously penetrating the first and second insulating films is formed. A semiconductor device including a gate electrode that fills the hole portion and covers the surface of the second insulating film around the gate forming hole portion and a manufacturing method thereof will be described. This manufacturing method includes the first to fourth steps. Hereinafter, each step will be described in order from the first step.

  1A to 1C are process diagrams for explaining a first embodiment of the present invention. 2A to 2C are process diagrams following FIG. 1C. 3A and 3B are process diagrams following FIG. 2C. Each of these drawings shows a cut surface of a cross section obtained by cutting the structure obtained in each manufacturing stage along the gate length direction indicated by an arrow in each drawing.

  First, in the first step, first and second insulating films 13 and 15 are sequentially formed on the lower ground 11a of the base 11 to obtain a structure as shown in FIG.

  The substrate 11 is a conventionally known semiconductor substrate, for example, a compound semiconductor substrate such as a substrate having a hetero-connection surface, that is, a substrate on which an AlGaN layer and a GaN layer are deposited, a substrate on which an AlGaAs layer and a GaAs layer are deposited, and the like. Any suitable semiconductor substrate may be used according to the design. An element such as a transistor is formed on the lower ground 11a of the base 11 (not shown). In the first embodiment, an example in which a base having an AlGaN / GaN heterojunction surface (hereinafter also referred to as an AlGaN / GaN base) is used as the base 11 will be illustrated and described. .

  In the configuration example shown in FIG. 1A, first, the base 11 is formed of a substrate 12 made of, for example, Si, SiC, or sapphire, and an AlN or the like formed by a well-known MOCVD method on the substrate 12. A buffer layer 14 such as GaN is provided. Further, on the upper side of the buffer layer 14, as an electron transit layer, a UID (Un-Intentionally-Doped: impurity-free) -Gan layer 16 (hereinafter also simply referred to as “Gan layer 16”) and an electron supply layer as a UID-AlGan The layer 18 (hereinafter, also simply referred to as “AlGan layer 18”) is sequentially formed by a well-known MOCVD method or MBE method. When such a laminated structure is formed, a two-dimensional electron gas layer 20 (hereinafter referred to as a 2DEG layer 20) is formed near the boundary between the Gan layer 16 and the AlGan layer 18 due to the difference in energy band gap between the Gan layer 16 and the AlGan layer 18. (Also called).

  When an AlGaN / GaN substrate is used as the substrate 11, the oxide film attached to the substrate surface 11a is removed using, for example, hydrochloric acid.

Thereafter, first and second insulating films 13 and 15 are formed on the base surface 11a as protective films for protecting the element from contamination or suppressing the generation of surface charges. Therefore, in the first embodiment, the first and second insulating films 13 and 15 are formed using, for example, a SiN film, a SiO ₂ film, and a SiON film as materials.

  By the way, in the first embodiment, not only for the purpose of functioning the first and second insulating films 13 and 15 as a protective film, but also for dispersing the electric field strength when driving the manufactured semiconductor device, It is formed for the purpose of forming a corner where the electric field is concentrated and for the purpose of accurately setting a gate electrode to be formed in a later process to a desired gate length. Therefore, in the first embodiment, in the subsequent second step and third step, the first and second insulating films 13 and 15 are individually etched to form a gate electrode. The gate forming hole is formed. Therefore, in order to selectively etch the first and second insulating films 13 and 15, respectively, in this first step, the etching rate value of the second insulating film 15 is equal to or higher than the etching rate value of the first insulating film 13. First and second insulating films 13 and 15 are formed so that

More specifically, when the first insulating film 13 is assumed to be etched by, for example, the ICP-RIE method (inductively coupled plasma-reactive ion etching method), the etching rate is 5 to 20 nm / min. For this purpose, a well-known T-CVD method (chemical vapor deposition method) is used, for example, at a temperature of 800 ° C., 1% SiH ₄ gas is added at 0.1 to 1 l / min, A first insulating film 13 is formed by depositing a SiN film at a growth rate of 10 to 50 nm / min with NH ₃ gas at a flow rate of 1 to 5 l / min and N ₂ carrier gas at a rate of 10 to 20 l / min. .

Further, when it is assumed that the second insulating film 15 is etched by, for example, the ICP-RIE method, the second insulating film 15 is formed to have an etching rate of 30 to 60 nm / min. Therefore, using a well-known P-CVD method (plasma chemical vapor deposition method), for example, under a temperature condition of 250 to 400 ° C., the RF power of 13.56 MHz is set to 10 to 100 W, and 20% SiH ₄ gas is used. A second insulating film 15 is formed by depositing a SiN film at a flow rate of 10 to 50 sccm, NH ₃ gas of ₂ to 20 sccm, and N ₂ carrier gas of 1000 to 2000 sccm.

  In order to make the first and second insulating films 13 and 15 function as protective films, the total thickness of the first and second insulating films 13 and 15 is preferably about 50 to 300 nm and 500 nm or less. Good to do.

  Further, the film thicknesses of the first and second insulating films 13 and 15 are set in order to achieve the above-described purpose of accurately setting a gate electrode to be formed in a later step to a desired gate length. Is set to a suitable value. A suitable example of each film thickness will be described later.

  Next, in the second step, an opening pattern is formed in the second insulating film 15 so that the first insulating film 13 is exposed (FIG. 1B).

  In this second step, in order to form an opening pattern, first, for example, a resist layer is formed on the upper surface 15a of the second insulating film 15 by using a known coating technique, photolithography technique, electron beam exposure method, or the like. 19 is formed. A first resist hole 19 a that exposes the upper surface 15 a of the second insulating film 15 is formed in the resist layer 19. Then, using the resist layer 19 with the first resist hole 19a as a mask, the resist layer 19 is opened by using an anisotropic dry etching technique such as a well-known ECR (electron cyclotron resonance) -RIE method or ICP-RIE method. A hole pattern 17 is formed. Thereafter, the resist layer 19 is removed using an organic solvent to obtain a structure as shown in FIG. When the etching rate of the second insulating film 15 is set on the assumption that etching is performed by the ICP-RIE method as described above, the opening pattern 17 is naturally formed by using the ICP-RIE method. Form.

  By the way, in the first embodiment, in order to achieve the purpose of forming the corner portion where the electric field concentrates and the purpose of accurately setting the gate electrode to be formed in a subsequent process to a desired gate length, the first embodiment is not provided. The hole pattern 17 is formed so that the inclination angle 17b of the inner side surface 17a with respect to the bottom surface 15b of the second insulating film 15 is vertical or approximately perpendicular. That is, the planar shape of the opening pattern 17 cut in the thickness direction of the base 11 along the gate length direction is a rectangular shape. Alternatively, the planar shape is a so-called tapered shape in which the hollow portion 17c gradually contracts from the opening portion 17d of the hole pattern 17 in the thickness direction of the second insulating film 15. More specifically, in view of the above-described object, the inclination angle 17b is preferably 60 to 90 °, more preferably 80 to 90 °.

  Further, in order to form the opening pattern 17 so that the inclination angle 17b is vertical or approximate to the vertical, the inclination angle 19d of the inner side surface 19c with respect to the bottom surface 19b of the resist layer 19 is vertical or approximate to the vertical. It is necessary to use the resist layer 19 in which the first resist hole 19a having an angle, more preferably an inclination angle 19d of 90 ± 20 °, is formed. Therefore, for example, a positive resist layer is used as the resist layer 19 in which the first resist hole portion 19a can be formed so that the shape, that is, the inclination angle 19d is vertical or approximately perpendicular. Is preferred.

  Next, in the third step, the first hole portion 21 that exposes the base surface 11a is formed in the region of the first insulating film 13 exposed from the hole pattern 17, and the hole pattern 17 is expanded. A second hole portion 23 having an opening length in the gate length direction larger than that of the first hole portion 21 is formed from the opening pattern 17.

  In the third step, in order to form the first and second holes 21 and 23, first, the resist layer 25 is first formed on the upper surface 15a of the second insulating film 15 by using, for example, a well-known coating technique and photolithography technique. It is formed (see FIG. 2A). Since the lift-off method is used in the subsequent fourth step, the resist layer 25 is formed of a negative resist layer in this step. In order to remove the region 13 a of the first insulating film 13 exposed from the hole pattern 17 and to expand the hole pattern 17, the resist layer 25 includes the hole pattern 17 and the periphery of the hole pattern 17. A second resist hole 25a that exposes the upper surface 15a of the second insulating film 15 is formed.

  The second resist hole 25a includes an opening 25b and a hollow portion 25c communicating with the opening 25b. The opening 25b is provided on the upper surface 25d of the resist layer 25, and connects the internal space of the second resist hole 25a, that is, the hollow portion 25c and the external space. The opening length W1 of the opening 25b in the gate length direction is designed to be larger on both sides along the gate length direction than the opening length W2 of the opening pattern 17 in the gate length direction.

  Since the resist layer 25 is a negative resist layer, the second resist hole 25a is formed from the opening 25b to the resist layer 25 by forming the second resist hole 25a using a known exposure technique. As the depth increases in the thickness direction, the hollow portion 25c gradually expands so-called a reverse taper shape.

  Then, anisotropic etching is performed using, for example, a well-known ICP-RIE method using the resist layer 25 with the second resist hole 25a as a mask. As a result, the region exposed from the second resist hole 25a, that is, the region given by the orthogonal projection of the opening 25b with respect to the exposed surface 26, that is, the etched region 27 is anisotropically etched. At this time, since the opening length W1 is designed to be larger than the opening length W2 as described above, not only the region 13a of the first insulating film 13 exposed from the opening pattern 17 but also the first portion around the opening pattern 17 is formed. The 2 insulating film 15 is also partially removed. As a result, the region 13a is removed from the first insulating film 13, and the first hole portion 21 that exposes the base surface 11a is formed. At the same time, the second insulating film 15 around the opening pattern 17 is partially removed, so that the opening length of the opening pattern 17 becomes the second hole portion 23 extending in the gate length direction. Thus, the first and second insulating films 13 and 15 are continuously formed by the first hole 21 formed in the first insulating film 13 and the second hole 23 formed in the second insulating film 15. A gate forming hole 29 that penetrates and exposes the base surface 11a is formed to obtain a structure as shown in FIG.

  Here, in the anisotropic etching in the third step, the second resist hole 25a of the resist layer 25 is slightly isotropically etched by radical ions contained in the etching gas. Therefore, as the anisotropic etching proceeds, the opening length W1 of the opening 25b gradually increases. As a result, in the second hole portion 23, the opening length of the opening portion 23a is slightly longer in the gate length direction than the bottom portion 23b. Therefore, corner portions 31 a and 31 b are formed on the inner wall surface 23 c of the second hole portion 23.

  In the third step, when the first hole 21 is formed, the second insulating film 15 with the opening pattern 17 functions as a mask.

  By the way, in the subsequent fourth step, the gate electrode 29 is formed by filling the gate forming hole 29. Therefore, the gate electrode is in contact with the base 11 at the bottom surface 21 a of the first hole portion 21. Therefore, the length W3 of the bottom surface 21a of the first hole 21 in the gate length direction (hereinafter also simply referred to as the length W3) is the gate length. In the first embodiment, as described above, the first hole 21 is formed without extending the length W3 by using the second insulating film 15 with the opening pattern 17 as a mask. Can do. Therefore, it is necessary to adjust each etching rate and each film thickness of the 1st and 2nd insulating films 13 and 15 in the 1st process mentioned above. Hereinafter, preferred examples of the etching rates and film thicknesses of the first and second insulating films 13 and 15 for performing the etching in the third step satisfactorily will be described.

  In this third step, the region 13 a of the first insulating film 13 exposed from the hole pattern 17 and the second insulating film 15 around the hole pattern 17 are anisotropically etched in the region to be etched 27 described above. (See FIG. 2A). At this time, it is necessary to etch the region 13a of the first insulating film 13 until the base surface 11a is exposed. However, if the second insulating film 15 functioning as a mask at this time and the first insulating film 13 existing under the second insulating film 15 are completely etched, the length W3 of the bottom surface 21a is expanded. End up. Accordingly, the region 13a of the first insulating film 13 is completely removed by etching in the third step, and the second insulating film 15 serving as a mask and the first insulating film 13 existing below the second insulating film 15 are removed. It is necessary to perform the etching so as not to be completely removed.

Here, when the thickness of the first insulating film 13 is x (nm) and the etching rate is y (nm / min), the time t (min) required to completely remove the first insulating film 13 is It is represented by the following formula (1).
t = x / y (1)
However, x, y, and t are positive real numbers.

Further, if the film thickness of the second insulating film 15 is a (nm), the etching rate is b (nm / min), and the time t ′ (min) required to completely remove the second insulating film 15 is given, The time t ″ (min) required to completely remove the second insulating film 15 and the first insulating film 13 existing below the second insulating film 15 in the etching region 27 is expressed by the following equation ( 2).
t ″ = t + t ′ = a / b + x / y (2)
However, a, b, t ′, and t ″ are positive real numbers.

  Therefore, the region 13a of the first insulating film 13 is completely removed, and the second insulating film 15 serving as a mask and the first insulating film 13 existing below the second insulating film 15 are not completely removed. In order to perform etching, the etching time T (min) in the third step needs to satisfy the following formula (3).

x / y <T <a / b + x / y (3)
In order to satisfy this equation (3), for example, if a = 80 (nm), b = 40 (nm / min), x = 20 (nm), y = 10 (mn / min), equation (3) The range of T given by ## EQU2 ## is 2 <T <4 (min), so that a sufficient etching time can be secured, that is, etching can be performed with good controllability.

  From the above, from the viewpoint of performing the etching in the third step with good controllability, in the first embodiment, the etching rates of the etching rates of the first and second insulating films 13 and It is preferable to set the film thickness.

  When the etching rates of the first and second insulating films 13 and 15 are set on the assumption that etching is performed by the ICP-RIE method as described above, the ICP-RIE method is naturally used. First and second holes are formed.

  In this anisotropic etching, the second insulating film 15 outside the etched region 27 existing in the orthogonal projection region of the opening 25b is slightly isotropically etched by the radical ions described above. . Therefore, the second insulating film 15 existing in the region excluding the etched region 27 in the exposed surface 26 as compared with the second hole portion 23 formed by deeply removing the etched region 27 by anisotropic etching. Is removed shallowly. The shallowly removed region becomes the third hole 28. As a result, the third hole 28 penetrates the second insulating film 15 continuously with the gate forming hole 29. Further, the third hole portion 28 is shallower than the second hole portion 23 from the second insulating film surface 15a around the second hole portion 23 and has an opening length on both sides in the gate length direction than the second hole portion 23. It is formed by being largely removed. Then, corner portions 32a and 32b are formed on the inner wall surface 28a of the third hole portion 28 (see FIG. 2B).

  Next, in the fourth step, a gate electrode is formed.

  In this fourth step, a gate electrode is formed using a known lift-off method. For this purpose, first, a gate formed on the entire surface of the structure (see FIG. 2B) obtained in the third step, that is, on the upper surface 25d of the resist layer 25 and on the inner side of the second resist hole 25a. A metal film 35 serving as a material of the gate electrode 33 is deposited on the hole 29 and the third hole 28 by using, for example, a known rotary evaporation method or a static evaporation method (see FIG. 2C).

  Subsequently, the resist layer 25 is removed using an organic solvent such as acetone. At this time, the metal film formed on the upper surface 25d of the resist layer 25 is also removed together with the resist layer 25, and the portions of the metal film formed in the gate forming hole 29 and the third hole 28 remain. The remaining metal film portion becomes the gate electrode 33 to obtain a structure as shown in FIG.

  The gate electrode 33 is formed so as to embed the gate forming hole 29 and also cover a part of the third hole 28 so as to run over the upper surface 15 a of the second insulating film 15 around the second hole 23. .

  The gate electrode 33 is in contact with the base surface 11 a at the bottom surface of the gate forming hole 29, that is, the bottom surface 21 a of the first hole portion 21. By this contact, the gate electrode 33 and the base 11 are Schottky-bonded to form a so-called MES type semiconductor device.

  In order to achieve Schottky junction between the gate electrode 33 and the base 11, the gate electrode 33 is formed using a metal film corresponding to the base 11 used as a material. For example, in the case of using a base layer on which a GaN layer is deposited as an upper layer, the gate electrode 33 is formed of a metal film such as Ni, Au, or Pt.

  In the MES type semiconductor device manufactured by the manufacturing method according to the first embodiment described above, a gate is formed by forming continuous holes in the first and second insulating films 13 and 15 in different processes. A gate forming hole 29 composed of the first and second holes 21 and 23 having different opening lengths in the longitudinal direction can be formed. When the first hole 21 is opened, the second hole 23 is expanded so that the opening length is larger on both sides along the gate length direction than the first hole 21. Corner portions 31 a and 31 b are formed on the inner wall surface 23 c of the two-hole portion 23. Here, in the MES type semiconductor device manufactured by the manufacturing method according to the first embodiment, after the fourth step described above, the gate electrode 33 is placed on the upper side of the base 11 so as to be separated from each other and face each other. Then, a source electrode and a drain electrode are formed (not shown). As a result, in the semiconductor device according to the first embodiment, during operation, the end surface 37a or 37b on the drain electrode side in the gate length direction of the contact surface between the gate electrode 33 and the base surface 11a and the gate electrode 33 In addition to the end 39a or 39b on the drain electrode side in the gate length direction of the portion covering the surface 15a of the second insulating film 15 around the gate forming hole 29, the inner wall surface of the second hole 23 Of the corners 31a and 31b formed in 23c, the electric field is also concentrated on the end 37a or 37b, the end 39a or 39b, and the corner 31a or 31b on the drain electrode side. That is, when the drain electrode is formed on the left side of the paper with the gate electrode 33 as the center in the configuration example of FIG. 3A after the fourth step in the first embodiment described above, the end 37a When the drain electrode is formed on the end 39a and the corner 31a and on the right side of the page, the electric field is concentrated on the end 37b, the end 39b, and the corner 31b. Therefore, since the semiconductor device manufactured according to the first embodiment has more portions where the electric field concentrates than the semiconductor device according to the prior art, each concentrated electric field is dispersed. As a result, the electric field strength at each of these locations is further reduced. Therefore, the electric field strength of the semiconductor device manufactured according to the first embodiment is more efficiently distributed as compared with the semiconductor device according to the prior art. Therefore, it can be said that the semiconductor device manufactured according to the first embodiment exhibits a good breakdown voltage even when operated at a high voltage and has a structure in which the occurrence of current collapse is suppressed.

  Furthermore, in the semiconductor device manufactured according to the first embodiment, corners 32 a and 32 b are formed on the inner wall surface 28 a of the third hole 28. Therefore, for example, when the field plate 34 is formed in the semiconductor device according to the first embodiment for the purpose of suppressing current collapse (see FIG. 3B), the corner portions 32a are operated during the operation of the semiconductor device. Alternatively, the electric field can be concentrated on 32b.

  In the case where the field plate 34 is formed in the semiconductor device according to the first embodiment, after the above-described fourth step, the field plate 34 is formed by using the upper surface 33a of the gate electrode 33 and the gate length of the gate electrode 33. It is formed so as to cover the side surface 33b on the drain electrode side in the direction and the surface 15a of the second insulating film 15 around the gate electrode 33 on the drain electrode side. Note that FIG. 3B shows a configuration example in the case where a drain electrode (not shown) is formed on the right side of the drawing with the gate electrode 33 as the center.

  Then, by forming the field plate 34 so as to cover the corner 32b on the drain electrode side, an electric field concentrates on the corner 32b during the operation of the semiconductor device. In the MES type semiconductor device according to the first embodiment, when the drain electrode is formed on the left side of the paper surface with the gate electrode 33 as the center, the field plate 34 is connected to the upper surface 33a of the gate electrode 33 and the left side of the paper surface. The covering is formed from the side surface 33c to the corner portion 32a. In that case, the electric field concentrates on the corner 32a during the operation of the semiconductor device.

  In the case where the field plate 34 is formed in the semiconductor device according to the first embodiment, the gate electrode 33 and the field plate 34 are integrally connected, so that the side on which the field plate 34 is formed (see FIG. In the configuration example of 3 (B), the electric field does not concentrate on the drain electrode side end 39b on the side surface 33b side. Then, the electric field concentrates on the end portion 36 in the gate length direction of the portion of the field plate 34 covering the surface 15a of the second insulating film 15 instead of the end portion 39b.

  Therefore, in the semiconductor device manufactured according to the first embodiment, when the field plate 34 is formed, for example, the end of each end 37a and 37b existing on the drain side, the field plate 34, The end portion in the gate length direction of the portion covering the surface 15a of the second insulating film 15 and each corner portion existing on the drain side among the corner portions 31a, 31b, 32a, and 32b are efficiently provided. Electric field concentration can be dispersed.

  Here, FIG. 4 is a diagram showing a prototype of the semiconductor device manufactured by the inventors according to the first embodiment, and is a copy of an SEM photograph taken with the semiconductor device facing the base surface. Curve I indicates the brightness of this SEM photograph along the gate length direction indicated by the arrow. In the semiconductor device used for taking the SEM photograph, the gate electrode 33 is formed using the static vapor deposition method in the fourth step described above. At that time, in order to clearly see the corners 31a and 31b in the SEM photograph, the gate electrode 33 was formed to be smaller than that described in the first embodiment. Therefore, in the semiconductor device used for taking this SEM photograph, the end of the gate electrode 33 covering the surface 15a of the second insulating film 15 around the gate forming hole 29 in the gate length direction. The portions 39a and 39b exist inside the corner portions 31a and 31b.

  In this curve I, peaks 41a and 41b indicate corners 31a and 31b, peaks 43a and 43b indicate corners 32a and 32b, and peaks 45a and 45b indicate end portions 39a and 39b, respectively (FIG. 3A). reference). Therefore, it can be confirmed from FIG. 4 that the semiconductor device having the locations where the electric field concentrates, that is, the end portions 39a and 39b and the corner portions 31a, 31b, 32a, and 32b can be obtained by the first embodiment. It was.

  In the first embodiment, the gate electrode 33 is in contact with the base 11 on the bottom surface 21 a of the first hole 21. Therefore, in the first embodiment, the length W3 of the bottom surface 21a of the first hole 21 in the gate length direction is the gate length. In the first embodiment, when the first hole 21 is formed in the first insulating film 13 using the opening pattern 17, the second insulating film 15 with the opening pattern 17 functions as a mask. (See FIG. 2B). Further, the opening pattern 17 is formed so that the planar shape cut in the thickness direction of the base 11 along the gate length direction is rectangular or tapered (see FIG. 1C). Therefore, in the first embodiment, by appropriately setting the opening length W2 of the opening pattern 17, the length W3 in the gate length direction of the bottom surface 21a of the first hole portion 21 is expanded from a desired value. 1st hole 21 can be formed. Therefore, in the first embodiment, a semiconductor device in which a desired gate length value is accurately set can be manufactured.

<Second Embodiment>
In the second embodiment, as in the first embodiment described above, the gate forming hole formed in the insulating film as the protective film is embedded, and the insulating film surface around the gate forming hole is embedded. A semiconductor device having a gate electrode covering the substrate and a method for manufacturing the same will be described. This manufacturing method includes the first to third steps.

  The semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment described above in that the first hole is formed in the first insulating film after the second step. The gate electrode is formed without forming the gate. In the second embodiment, the first insulating film functions as a gate insulating film to constitute a so-called MIS type semiconductor device. Since other components and operational effects are the same as those of the first embodiment, the common components will be referred to by the same reference numerals and the same reference numerals will be given, and duplicate descriptions thereof will be omitted. .

  FIGS. 5A and 5B are process diagrams for explaining the second embodiment of the present invention. Each of these drawings shows a cut surface of a cross section obtained by cutting the structure obtained in each manufacturing stage along the gate length direction indicated by an arrow in each drawing.

  In the second embodiment, first, the first step and the second step similar to those in the first embodiment described above are performed (see FIGS. 1A to 1C).

  Next, as in the third step of the first embodiment described above, a negative resist layer 25 in which the second resist hole 25a is formed is deposited (see FIG. 2A).

  Next, in the third step in the second embodiment, the upper surface 15a of the second insulating film 15 around the hole pattern 17 is covered, and a gate electrode that embeds the hole pattern 17 is formed.

  In this third step, a gate electrode is formed using a known lift-off method, as in the fourth step of the first embodiment described above. For this purpose, first, the entire surface of the structure obtained by depositing the resist layer 25 on the structure obtained in the second step (see FIG. 2A), that is, the upper surface 25d of the resist layer 25 and the second resist hole 25a. A precursor gate electrode layer 51 made of, for example, Ni, Au, Pt or the like, which is a material of the gate electrode, is deposited on the opening pattern 17 formed on the inner side by using, for example, a known rotary evaporation method or a static evaporation method (FIG. 5). (See (A)).

  Subsequently, the resist layer 25 is removed using an organic solvent such as acetone. At this time, the precursor gate electrode layer formed on the upper surface 25d of the resist layer 25 is also removed together with the resist layer 25, and the portion of the precursor gate electrode layer formed in the opening pattern 17 remains. The remaining portion of the precursor gate electrode layer becomes the gate electrode 53 to obtain a structure as shown in FIG.

  In the second embodiment, the opening pattern 17 is used as the gate forming hole in the first embodiment described above. The gate electrode 53 is formed so as to embed the opening pattern 17 and to cover the upper surface 15a of the second insulating film 15 around the opening pattern 17.

  The gate electrode 53 is formed on the base 11 via the first insulating film 13 in the gate forming hole, that is, the opening pattern 17. The first insulating film 13 functions as a gate insulating film to constitute a so-called MIS type semiconductor device.

  In the MIS type semiconductor device manufactured by the manufacturing method according to the second embodiment described above, the hole pattern 17 formed in the second step of the first embodiment described above is used as a gate forming hole. The first insulating film 13 functions as a gate insulating film. Thus, in the semiconductor device according to the second embodiment, while forming the MIS type semiconductor device, the gate forming hole, that is, the opening pattern 17 is embedded, and the second insulating film 15 around the opening pattern 17 is formed. A gate electrode 53 that covers the upper surface 15a is formed. As a result, in the semiconductor device according to the second embodiment, during operation, the end of the contact surface between the gate electrode 53 and the first insulating film 13 on the side where the drain electrode (not shown) is formed in the gate length direction. In addition to the portion 55a or 55b, a drain electrode in the gate length direction is formed in the gate electrode 53 in the gate forming hole, that is, the portion covering the surface 15a of the second insulating film 15 around the opening pattern 17 The electric field is also concentrated on the end portion 57a or 57b on the side. That is, in the configuration example of FIG. 5B, when the drain electrode is formed on the left side of the paper surface, the end portions 55a and 57a are formed. When the drain electrode is formed on the right side of the paper surface, the end portion 55b and The electric field concentrates on 57b.

  Therefore, unlike the MIS type semiconductor device having the conventional structure in which the electric field is concentrated on the end portions 55a and 55b, the semiconductor device manufactured according to the second embodiment distributes the electric field strength more efficiently. Therefore, the semiconductor device manufactured according to the second embodiment exhibits a good breakdown voltage even when operated at a high voltage, and suppresses the occurrence of current collapse, as compared with the MIS type semiconductor device having the conventional structure. It can be said that it is a structured.

(A)-(C) is process drawing explaining 1st Embodiment of this invention. (A)-(C) are process drawings explaining 1st Embodiment of this invention, and are process drawings following FIG.1 (C). (A) And (B) is process drawing explaining 1st Embodiment of this invention, and is process drawing following FIG.2 (C). It is a SEM photograph explaining the semiconductor device by 1st Embodiment of this invention. (A) And (B) is process drawing explaining 2nd Embodiment of this invention. It is a figure which shows the semiconductor device by a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 101: Base 12: Substrate 13: 1st insulating film 14: Buffer layer 15: 2nd insulating film 16: UID-Gan layer 17: Opening pattern 18: UID-AlGan layer 19, 25: Resist layer 20: 2 Dimensional electron gas layer 21: first hole 23: second hole 26: exposed surface 27: etched region 28: third hole 29, 105: gate forming holes 31a, 31b, 32a, 32b: corners 33, 53, 107: gate electrode 34: field plate 35: metal films 36, 37a, 37b, 39a, 39b, 55a, 55b, 57a, 57b, 109a, 109b, 111a, 111b: end portions 41, 43, 45: Peak 51: Precursor gate electrode layer 103: Protective film

Claims (11)

The groundwork,
First and second insulating films sequentially formed so as to cover the underlying ground of the base;
A gate forming hole that is formed continuously through the first and second insulating films and exposes the base surface is embedded, and the surface of the second insulating film around the gate forming hole is covered. And a gate electrode
The gate forming hole includes a first hole formed in the first insulating film, and a second hole formed in the second insulating film having a larger opening length in the gate length direction than the first hole. A MES type semiconductor device comprising a hole. The MES type semiconductor device according to claim 1,
A third hole penetrating through the second insulating film continuously with the gate forming hole;
The third hole is removed from the surface of the second insulating film around the second hole so as to be shallower than the second hole and the opening length in the gate length direction is larger than that of the second hole. A MES type semiconductor device, characterized in that the MES type semiconductor device is formed. The groundwork,
First and second insulating films sequentially formed so as to cover the underlying ground of the base;
A gate formed through the second insulating film to bury a gate forming hole that exposes the surface of the first insulating film, and covers the surface of the second insulating film around the gate forming hole. An MIS type semiconductor device comprising an electrode. A first step of sequentially forming first and second insulating films on the lower ground;
A hole pattern having a rectangular planar shape or a tapered shape cut in the thickness direction of the base along the gate length direction is formed on the second insulating film so that the first insulating film is exposed. Process,
A first hole portion exposing the base surface is formed in a region of the first insulating film exposed from the hole pattern, and the hole pattern is extended in the gate length direction. A third step of forming a second hole having a larger opening length in the gate length direction than the first hole;
And a fourth step of forming a gate electrode that covers the surface of the second insulating film around the second hole and fills the gate forming hole formed of the first and second holes. Manufacturing method of MES type semiconductor device. It is a manufacturing method of the MES type semiconductor device according to claim 4,
A method of manufacturing a MES type semiconductor device, wherein the opening pattern is formed so that an inclination angle is 60 to 90 °. A method for manufacturing the MES type semiconductor device according to claim 4, wherein:
The MES type is characterized in that the opening pattern is formed using the resist layer as a mask in which a first resist hole portion having an inclination angle of 90 ± 20 ° with respect to the bottom surface of the resist layer is formed. A method for manufacturing a semiconductor device. A method for manufacturing a MES type semiconductor device according to any one of claims 4 to 6,
In the third step, on the upper surface of the second insulating film, a negative resist layer with a second resist hole that exposes the opening pattern and the upper surface of the second insulating film around the opening pattern. Form the
The second resist hole portion is constituted by an opening portion and a hollow portion communicating with the opening portion, and the hollow portion gradually increases as the depth increases from the opening portion in the thickness direction of the negative resist layer. With an expanding shape,
The method of manufacturing a MES type semiconductor device, wherein the first and second hole portions are formed using the negative resist layer as a mask. It is a manufacturing method of the MES type semiconductor device according to claim 7,
In the third step, the second hole is formed by deeply removing the second insulating film existing in the orthogonal projection region of the opening with respect to the exposed surface from the second resist hole,
The MES type semiconductor device is characterized in that the third hole is formed by removing the second insulating film existing in the region of the exposed surface excluding the orthogonal projection region shallower than the orthogonal projection region. Manufacturing method. A first step of sequentially forming first and second insulating films on the lower ground;
A hole pattern having a rectangular planar shape or a tapered shape cut in the thickness direction of the base along the gate length direction is formed on the second insulating film so that the first insulating film is exposed. Process,
And a third step of forming a gate electrode that embeds the opening pattern and covers the surface of the second insulating film around the opening pattern. A manufacturing method of the MIS type semiconductor device according to claim 9,
A manufacturing method of a MIS type semiconductor device, wherein the opening pattern is formed so that an inclination angle is 60 to 90 °. It is a manufacturing method of the MIS type semiconductor device according to claim 9 or 10,
The MIS type is characterized in that the opening pattern is formed using the resist layer as a mask in which a first resist hole portion having an inclination angle of 90 ± 20 ° with respect to the bottom surface of the resist layer is formed. A method for manufacturing a semiconductor device.