JP2014229667A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a semiconductor device having high reliability.SOLUTION: A semiconductor device manufacturing method comprises: a process of forming an interlayer insulation film II2 on an interlayer insulation film II1 in which a conductive film CF1 is embedded; a process of forming on the interlayer insulation film II2, a metal film MF1 having an opening OP1 which overlaps the conductive film CF1; a process of forming an interlayer insulation film II3 on the metal film MF1 and on the interlayer insulation film II2; a process of forming on the interlayer insulation film II3, a wiring trench TR1 which overlaps the metal film MF1 and the opening OP1 and forming in the interlayer insulation film II2, a via hole VH1 which overlaps the opening OP1; a process of removing a part of the conductive film CF1, which overlaps the opening OP1; and a process of embedding a conductive film CF2 in the wiring trench TR1 and in the via hole VH1.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, for example, a technique applicable to a semiconductor device having a dual damascene structure and a manufacturing method thereof.

  In a method of manufacturing a semiconductor device, a dual damascene process may be used when forming wirings and vias. Examples of the technology related to the dual damascene process include those described in Patent Documents 1 to 3.

  The technique described in Patent Document 1 uses the first and second mask films as a mask to remove the first and second films to be etched by a single etching process, thereby forming a wiring pattern and a via pattern. Is. The technique described in Patent Document 2 is to form a wiring groove using a metal hard mask. Patent Document 3 describes an interconnect structure including a gouging structure at the bottom of a via opening.

JP 2006-245236 A JP 2009-4665 A JP 2011-14904 A

In manufacturing a semiconductor device having a dual damascene structure, after forming a via hole and a wiring groove on a lower layer wiring, a process of forming a recess by etching in a region overlapping the via hole in the lower layer wiring may be performed. However, the interlayer insulating film exposed on the bottom surface of the wiring groove is etched by the processing, and there is a possibility that the bottom surface of the wiring groove is uneven. In this case, there is a concern that the embedding property of the conductive film in the wiring trench may be lowered.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, after forming a metal film having an opening on the second interlayer insulating film, a third interlayer insulating film is formed on the second interlayer insulating film and on the metal film. Then, a wiring groove overlapping the metal film is formed in the third interlayer insulating film, and a via hole overlapping the opening is formed in the second interlayer insulating film.

  According to the embodiment, a highly reliable semiconductor device can be realized.

It is sectional drawing which shows the wiring structure of the semiconductor device which concerns on 1st Embodiment. It is a top view which shows the positional relationship of a wiring groove | channel and a metal film among the wiring structures shown in FIG. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. FIG. 5 is a cross-sectional view showing a modification of the method for manufacturing the semiconductor device shown in FIG. It is sectional drawing which shows the wiring structure of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a cross-sectional view showing a wiring structure of the semiconductor device SD1 according to the first embodiment. FIG. 2 is a plan view showing the positional relationship between the wiring trench TR1 and the metal film MF1 in the wiring structure shown in FIG. FIG. 3 is a sectional view showing the semiconductor device SD1 according to this embodiment.
4 to 6 are cross-sectional views showing a method for manufacturing the semiconductor device SD1 according to this embodiment.

The manufacturing method of the semiconductor device SD1 according to the present embodiment is performed as follows.
First, the interlayer insulating film II2 is formed over the interlayer insulating film II1 in which the conductive film CF1 is embedded. Next, a metal film MF1 having an opening OP1 overlapping with the conductive film CF1 is formed over the interlayer insulating film II2. Next, an interlayer insulating film II3 is formed over the metal film MF1 and the interlayer insulating film II2. Next, a wiring trench TR1 that overlaps the metal film MF1 and the opening OP1 is formed in the interlayer insulating film II3, and a via hole VH1 that overlaps the opening OP1 is formed in the interlayer insulating film II2. Next, a part of the conductive film CF1 that overlaps with the via hole VH1 is removed. Next, the conductive film CF2 is embedded in the wiring trench TR1 and the via hole VH1. In the present embodiment, the semiconductor device SD1 is manufactured in this way.

  According to the present embodiment, the bottom surface of the wiring trench TR1 is covered with the metal film MF1 in a state where the wiring trench TR1 and the via hole VH1 are formed. In this case, the bottom surface of the wiring trench TR1 can be protected by the metal film MF1 in the step of removing a part of the conductive film CF1 overlapping the via hole VH1. For this reason, it can suppress that an unevenness | corrugation arises in the bottom face of wiring trench TR1, and can make the embedding property of conductive film CF2 in wiring trench TR1 favorable. Therefore, a highly reliable semiconductor device can be realized.

  Hereinafter, the configuration of the semiconductor device SD1 and the method for manufacturing the semiconductor device SD1 according to the present embodiment will be described in detail.

First, the configuration of the semiconductor device SD1 will be described.
The semiconductor device SD1 includes, for example, a semiconductor substrate SB1, a transistor MT1 provided on the semiconductor substrate SB1, and a multilayer wiring structure provided on the semiconductor substrate SB1.
In the semiconductor substrate SB1, an element isolation film EL1 that isolates the transistor MT1 from other elements is provided. The transistor MT1 includes, for example, a gate insulating film GI1 and a gate electrode GE1 provided on the semiconductor substrate SB1, and a source / drain region DR1 provided on the semiconductor substrate SB1 so as to sandwich the gate electrode GE1. A sidewall SW1 is provided on the side wall of the gate electrode GE1. On the semiconductor substrate SB1, an interlayer insulating film II4 is provided so as to cover the transistor MT1. A contact plug CP1 connected to the source / drain region DR1 is embedded in the interlayer insulating film II4.

  A multilayer wiring structure is formed on the interlayer insulating film II4. The multilayer wiring structure is composed of a plurality of wiring layers stacked on each other. In the present embodiment, the dual damascene wiring structure shown in FIG. 1 can be applied to each of the wirings constituting these wiring layers.

The multilayer wiring structure constituting the semiconductor device SD1 according to the present embodiment includes an interlayer insulating film II1, an interlayer insulating film II2 provided on the interlayer insulating film II1, and an interlayer insulating film II3 provided on the interlayer insulating film II2. And. The interlayer insulating film II1, the interlayer insulating film II2, and the interlayer insulating film II3 can constitute an arbitrary wiring layer in the multilayer wiring structure.
FIG. 3 illustrates a case where the interlayer insulating film II1, the interlayer insulating film II2, and the interlayer insulating film II3 are sequentially stacked on the interlayer insulating film II4. In the example shown in FIG. 3, for example, a plurality of wiring layers can be further formed on the interlayer insulating film II3.

  A conductive film CF1 is embedded in the interlayer insulating film II1. In the example shown in FIG. 1, the conductive film CF1 forms a wiring IC1. The interlayer insulating film II1 is made of, for example, a low dielectric constant material. The conductive film CF1 is made of Cu, for example. The conductive film CF1 is formed, for example, in the interlayer insulating film II1 using a damascene process. Note that the side and bottom surfaces of the conductive film CF1 may be covered with a barrier metal film.

  The interlayer insulating film II2 is provided on the interlayer insulating film II1, and has a via hole VH1 that overlaps the conductive film CF1 in plan view. The via hole VH1 is formed so as to penetrate the interlayer insulating film II2 and reach the conductive film CF1. Interlayer insulating film II2 is made of, for example, a low dielectric constant material.

  The conductive film CF1 has a recess RC1 in a region overlapping with the via hole VH1. The recess RC1 is provided on the upper surface of the conductive film CF1 so as not to penetrate the conductive film CF1. That is, the via hole VH1 passes through the interlayer insulating film II2 and reaches the inside of the conductive film CF1. In this case, the interface resistance between the wiring IC1 and the via plug VP2 can be reduced, and the resistance of the wiring can be reduced. It is also possible to improve the connection reliability between the wiring IC1 and the wiring IC2.

  On the conductive film CF1, for example, a metal film MF2 is provided. In this case, the interlayer insulating film II2 is provided on the conductive film CF1 via the metal film MF2. Thereby, it can suppress that Cu which comprises electrically conductive film CF1 diffuses into interlayer insulation film II2. Further, when the metal film MF2 is formed on the conductive film CF1, a part of the metal film MF2 etched in the step of forming the recess RC1 described later adheres to the side surface of the via hole VH1. Thereby, when forming the recess RC1, it is possible to avoid the Cu constituting the etched conductive film CF1 from coming into direct contact with the side surface of the via hole VH1.

  In the example shown in FIG. 1, a metal film MF2 is formed on the upper surface of the conductive film CF1 and the side surface of the via hole VH1. At this time, a portion of the metal film MF2 provided on the conductive film CF1 forms a barrier metal film BF1 that covers the upper surface of the wiring IC1. The portion located on the side surface of the via hole VH1 is formed, for example, when a part of the metal film MF2 etched when forming the recess RC1 adheres to the side surface of the via hole VH1. Further, the metal film MF2 has an opening in a region overlapping with the recess RC1.

  The metal film MF2 is made of, for example, TiN or TaN. Accordingly, Cu constituting the conductive film CF1 can be prevented from diffusing into the interlayer insulating film II2 while ensuring the adhesion of the metal film MF2 to the interlayer insulating film II2.

  A metal film MF4 is provided on the side surface of the via hole VH1, for example, via a metal film MF2. The metal film MF4 is formed by attaching a part of the conductive film CF1 etched when forming the recess RC1 on the side surface of the via hole VH1. The metal film MF4 is made of the same material as that of the conductive film CF1, and is made of Cu, for example.

  The interlayer insulating film II3 is provided on the interlayer insulating film II2 and has a wiring trench TR1 that overlaps the via hole VH1 in plan view. The wiring trench TR1 is formed so as to penetrate the interlayer insulating film II3 and be connected to the via hole VH1. The interlayer insulating film II3 is made of, for example, a low dielectric constant material.

A metal film MF1 is provided at least around the via hole VH1 on the interlayer insulating film II2. That is, the bottom surface of the wiring trench TR1 is covered with the metal film MF1. Thereby, in the step of forming the recess RC1, it is possible to suppress the formation of irregularities on the bottom surface of the wiring trench TR1 by etching the bottom surface of the wiring trench TR1.
In the present embodiment, for example, the entire bottom surface of the wiring trench TR1 is covered with the metal film MF1. In this case, in the step of forming the recess RC1, it is possible to reliably suppress the occurrence of unevenness on the bottom surface of the wiring trench TR1.

A part of the interlayer insulating film II3 located around the wiring trench TR1 is provided, for example, on the metal film MF1. In the present embodiment, a part of the interlayer insulating film II3 located around the wiring trench TR1 is provided, for example, on the outer edge PP1 of the metal film MF1 in plan view. In this case, the outer edge portion PP1 of the metal film MF1 in plan view is covered with the interlayer insulating film II3. Thereby, even if misalignment occurs when forming the wiring trench TR1, it is possible to suppress the exposure of the interlayer insulating film II2 on the bottom surface of the wiring trench TR1. For this reason, the bottom surface of the wiring trench TR1 can be reliably protected by the metal film MF1.
In FIG. 2, the broken line indicates the outline of the metal film MF1, and the alternate long and short dash line indicates the outline of the via hole VH1. In the example shown in FIG. 2, the width of the metal film MF1 is larger than the width of the wiring trench TR1. In this case, the outline in the plan view of the metal film MF1 is located outside the outline in the plan view of the wiring trench TR1. Further, the outline of the via hole VH1 in plan view is located on the inner side of the outline of the wiring trench TR1 in plan view.

  In the example shown in FIG. 1, the metal film MF1 is provided, for example, on the bottom surface and the side surface of the wiring trench TR1. The portion located on the side surface of wiring trench TR1 is formed, for example, when a part of metal film MF1 etched when forming recess RC1 adheres to the side surface of via hole VH1.

  The metal film MF1 is made of, for example, TiN or TaN. Accordingly, Cu constituting the conductive film CF2 can be prevented from diffusing into the interlayer insulating film II2 or the interlayer insulating film II3 while securing the adhesion of the metal film MF1 to the interlayer insulating film II2 and the interlayer insulating film II3. . Further, the thickness of the portion of the metal film MF1 located at the bottom surface of the wiring trench TR1 is smaller than the thickness of the outer edge portion PP1 covered with the interlayer insulating film II3, for example.

A metal film MF3 is provided on the bottom and side surfaces of the wiring trench TR1 and on the bottom and side surfaces of the via hole VH1. In the present embodiment, the metal film MF3 is provided, for example, on the bottom surface and the side surface of the wiring trench TR1 via the metal film MF1, and is provided on the side surface of the via hole VH1 via the metal film MF2 and the metal film MF4. The metal film MF3 is in direct contact with the conductive film CF1 at the bottom of the via hole VH1.
The metal film MF3 is made of Ti or Ta, for example. Thereby, it is possible to suppress the diffusion of Cu constituting the conductive film CF2 into the interlayer insulating film II2 or the interlayer insulating film II3 while ensuring the adhesion of the metal film MF3 to the conductive film CF2.

  A conductive film CF2 is embedded in the wiring trench TR1 and the via hole VH1. The conductive film CF2 is made of Cu, for example. In the present embodiment, the conductive film CF2 forms a wiring IC2 having a dual damascene structure and a via plug VP2.

  In the example shown in FIG. 1, a barrier metal film BF2 composed of each metal film is provided between the via hole VH1 and the wiring trench TR1 and the conductive film CF2. Portions of the barrier metal film BF2 located on the bottom and side surfaces of the wiring trench TR1 are configured by a laminated film of the metal film MF1 and the metal film MF3. In this case, the barrier metal film BF2 having high adhesion to the conductive film CF2, the interlayer insulating film II2, and the interlayer insulating film II3 can be realized. In addition, the portion of the barrier metal film BF2 located on the side surface of the via hole VH1 is configured by a stacked film in which the metal film MF2, the metal film MF4, and the metal film MF3 are stacked in order. Even in this case, the barrier metal film BF2 having high adhesion to the conductive film CF2 and the interlayer insulating film II2 can be realized.

Next, a method for manufacturing the semiconductor device SD1 according to this embodiment will be described.
First, as shown in FIG. 4A, an interlayer insulating film II1 in which a conductive film CF1 is embedded is formed on a semiconductor substrate SB1 provided with a transistor MT1. The interlayer insulating film II1 may be formed on the semiconductor substrate SB1 via another wiring layer. In FIG. 4A, the configurations of the semiconductor substrate SB1 and the transistor MT1 are omitted.

  Next, a metal film MF2 is formed over the conductive film CF1. Thereby, it can suppress that Cu which comprises electrically conductive film CF1 diffuses into interlayer insulation film II2. Further, in the step of forming the recess RC1 described later, a part of the etched metal film MF2 can be attached on the side surface of the via hole VH1. Thereby, when forming the recess RC1, it is possible to avoid the Cu constituting the etched conductive film CF1 from coming into direct contact with the side surface of the via hole VH1. The metal film MF2 is formed by sputtering, for example.

The metal film MF2 is made of, for example, TiN or TaN. Accordingly, Cu constituting the conductive film CF1 can be prevented from diffusing into the interlayer insulating film II2 while ensuring the adhesion of the metal film MF2 to the interlayer insulating film II2.
The metal film MF2 has a smaller film thickness than the metal film MF1 formed in the step of forming the metal film MF1 described later. Thereby, when removing a part of the metal film MF2 and a part of the conductive film CF1 in the step of forming the recess RC1, the bottom surface of the wiring trench TR1 can be reliably protected by the metal film MF1. The film thickness of the metal film MF2 formed in this step is not particularly limited, but is, for example, 10 to 40 mm.

  The metal film MF2 is formed as follows, for example. First, as shown in FIG. 4B, the upper portion of the conductive film CF1 is selectively etched to make the upper surface of the conductive film CF1 lower than the upper surface of the interlayer insulating film II1. Next, as shown in FIG. 4C, a metal film MF2 is formed on the conductive film CF1 and the interlayer insulating film II1. Next, as illustrated in FIG. 4D, the metal film MF2 over the interlayer insulating film II1 is removed by performing CMP (Chemical Mechanical Polishing) on the metal film MF2. In an example of the present embodiment, for example, the metal film MF2 is formed on the conductive film CF1 in this way.

FIG. 7 is a cross-sectional view showing a modification of the method for manufacturing the semiconductor device SD1 shown in FIG. 4, and shows a method for forming the metal film MF2 different from FIG.
In the example shown in FIG. 7, the metal film MF2 is formed as follows. First, as shown in FIG. 7B, a metal film MF2 is formed on the conductive film CF1 and the interlayer insulating film II1. At this time, the upper surface of the conductive film CF1 and the upper surface of the interlayer insulating film II1 constitute the same plane as shown in FIG. 7A. Next, the metal film MF2 is patterned by dry etching the metal film MF2 using a resist mask obtained by patterning the resist film by exposure and development. As a result, as shown in FIG. 7C, the metal film MF2 is left only on the conductive film CF1. In the present modification, the metal film MF2 is formed on the conductive film CF1 in this way.

  Next, an interlayer insulating film II2 is formed on the interlayer insulating film II1 in which the conductive film CF1 is embedded. In the present embodiment, for example, the interlayer insulating film II2 is formed over the conductive film CF1 via the metal film MF2.

Next, a metal film MF1 having an opening OP1 that overlaps the conductive film CF1 in plan view is formed over the interlayer insulating film II2. The metal film MF1 functions as a barrier metal film BF2 that covers at least the bottom surface of the wiring trench TR1 provided in the interlayer insulating film II2. For this reason, the metal film MF1 is patterned in accordance with the shape of the wiring trench TR1. In the present embodiment, the metal film MF1 can have, for example, a planar shape extending in the first direction.
In the present embodiment, for example, the metal film MF1 formed on the interlayer insulating film II2 by sputtering or the like is patterned by dry etching using a resist mask or the like, thereby forming the metal film MF1 having the opening OP1. The
Thereby, the structure shown in FIG. 5A is obtained.

The metal film MF1 is made of, for example, TiN or TaN. Accordingly, Cu constituting the conductive film CF2 can be prevented from diffusing into the interlayer insulating film II2 while ensuring the adhesion of the metal film MF1 to the interlayer insulating film II2. The film thickness of the metal film MF1 formed in this process is not particularly limited, but is, for example, 20 to 80 mm.
The metal film MF1 is provided so as to have a width larger than the wiring width of the wiring IC1 constituted by, for example, the conductive film CF1. This facilitates obtaining a margin for misalignment of the wiring trench TR1 formed in the interlayer insulating film II2.

  Next, as shown in FIG. 5B, an interlayer insulating film II3 is formed on the metal film MF1 and the interlayer insulating film II2.

Next, as shown in FIG. 5C, the metal film MF1 and the wiring trench TR1 overlapping the opening OP1 are formed in the interlayer insulating film II3, and the via hole VH1 overlapping the opening OP1 is formed in the interlayer insulating film II2. To do. The via hole VH1 and the wiring trench TR1 are respectively provided in the interlayer insulating film II2 and the interlayer insulating film II3 so as to be connected to each other.
The planar shapes of the wiring trench TR1 and the via hole VH1 are not particularly limited. In the present embodiment, the wiring trench TR1 can have a planar shape extending in the first direction, for example.

  In the present embodiment, for example, the wiring trench TR1 and the via hole VH1 can be formed as follows. First, a resist mask obtained by patterning a resist film by exposure and development is formed on the interlayer insulating film II3. Next, the wiring trench TR1 is formed by dry etching the interlayer insulating film II2 using the resist mask. Next, the via hole VH1 is formed by dry etching the interlayer insulating film II2 using the resist mask and the metal film MF1 as an etching mask. As a result, the wiring trench TR1 and the via hole VH1 are formed. According to the present embodiment, the wiring trench TR1 and the via hole VH1 constituting the dual damascene structure can be formed at the same time. Further, the via hole VH1 can be formed in the interlayer insulating film II2 using the metal film MF1 having the opening OP1 without newly forming a resist mask for forming the via hole VH1. The metal film MF2 can function as an etching stopper when the via hole VH1 is formed, for example.

  In the above step of forming the wiring trench TR1 and the via hole VH1, the wiring trench TR1 is formed, for example, so that the outer edge portion PP1 of the metal film MF1 is covered with the interlayer insulating film II3. That is, a part of the interlayer insulating film II3 located around the wiring trench TR1 is provided on the outer edge portion PP1 of the metal film MF1. Thereby, even if misalignment occurs when forming the wiring trench TR1, it is possible to suppress the exposure of the interlayer insulating film II2 on the bottom surface of the wiring trench TR1. For this reason, the bottom surface of the wiring trench TR1 can be reliably protected by the metal film MF1, and the occurrence of unevenness on the bottom surface of the wiring trench TR1 can be suppressed.

Next, as shown in FIG. 6A, a part of the conductive film CF1 overlapping the via hole VH1 is removed. Thereby, the recess RC1 is formed on the upper surface of the conductive film CF1. For this reason, it is possible to reduce the resistance and improve the connection reliability in the wiring.
In the present embodiment, the bottom surface of the wiring trench TR1 is covered with the metal film MF1 in a state where the wiring trench TR1 and the via hole VH1 are formed. In this case, the bottom surface of the wiring trench TR1 is protected by the metal film MF1 in the step of removing a part of the conductive film CF1 overlapping the via hole VH1. For this reason, it can suppress that an unevenness | corrugation arises in the bottom face of wiring trench TR1, and can make the embedding property of conductive film CF2 in wiring trench TR1 favorable.

In the above-described step of removing a part of the conductive film CF1, the surface portion of the metal film MF1 is removed by etching and attached on the side surface of the wiring trench TR1. For this reason, the metal film MF1 is provided on the side surface and the bottom surface of the wiring trench TR1.
When the outer edge portion PP1 of the metal film MF1 is covered with the interlayer insulating film II3, the outer edge portion PP1 is not etched in the above step of removing a part of the conductive film CF1. In this case, the film thickness of the outer edge portion PP1 in the metal film MF1 is larger than the film thickness of the portion located on the bottom surface of the wiring trench TR1 in the metal film MF1.

When the metal film MF2 is provided over the conductive film CF1, the above step of removing a part of the conductive film CF1 removes a part of the metal film MF2 that overlaps the via hole VH1 and A portion overlapping the via hole VH1 is removed. Thereby, the conductive film CF1 having the recess RC1 is realized. In this case, the portion of the metal film MF2 that overlaps the via hole VH1 is removed by etching, and is deposited on the side surface of the via hole VH1. For this reason, the metal film MF2 is provided on the side surface of the via hole VH1 and the upper surface of the conductive film CF1.
In the example shown in FIG. 6, a part of the conductive film CF1 removed by etching when the recess RC1 is formed adheres to, for example, the metal film MF2 provided on the side surface of the via hole VH1, and the metal film MF4. Configure.

  Next, as shown in FIG. 6B, a metal film MF3 that covers the inner wall of the wiring trench TR1, the inner wall of the via hole VH1, and the upper surface of the interlayer insulating film II3 is formed. Thereby, in the step of forming the conductive film CF2 to be described later, it is possible to suppress the diffusion of Cu constituting the conductive film CF2 provided on the upper surface of the interlayer insulating film II3 into the interlayer insulating film II3. The metal film MF3 is formed by sputtering, for example.

  Next, as shown in FIG. 6C, a conductive film CF2 is embedded in the wiring trench TR1 and the via hole VH1. In the present embodiment, the conductive film CF2 is formed in the wiring trench TR1, the via hole VH1, and the interlayer insulating film II3 via the metal film MF3. The conductive film CF2 is formed using, for example, a plating method using a Cu seed film after forming a Cu seed film.

Next, a portion of the conductive film CF2 located on the interlayer insulating film II3 is removed using CMP. Next, a portion of the metal film MF3 located on the interlayer insulating film II3 is removed using CMP. As a result, the wiring IC2 constituted by the conductive film CF2 embedded in the wiring trench TR1 and the via plug VP2 constituted by the conductive film CF2 embedded in the via hole VH1 are formed. In this way, a dual damascene wiring structure constituted by the wiring IC2 and the via plug VP2 is obtained.
In the present embodiment, for example, the semiconductor device SD1 is manufactured in this way.

Next, the effect of this embodiment will be described.
According to the present embodiment, the bottom surface of the wiring trench TR1 is covered with the metal film MF1 in a state where the wiring trench TR1 and the via hole VH1 are formed. In this case, the bottom surface of the wiring trench TR1 can be protected by the metal film MF1 in the step of removing a part of the conductive film CF1 overlapping the via hole VH1. For this reason, it can suppress that an unevenness | corrugation arises in the bottom face of wiring trench TR1, and can make the embedding property of conductive film CF2 in wiring trench TR1 favorable. Therefore, a highly reliable semiconductor device can be realized.

(Second Embodiment)
FIG. 8 is a cross-sectional view showing a wiring structure of the semiconductor device SD2 according to the second embodiment. 9 to 10 are cross-sectional views illustrating the method for manufacturing the semiconductor device SD2 according to this embodiment.
The semiconductor device SD2 according to this embodiment has the same configuration as that of the semiconductor device SD1 according to the first embodiment, except that the semiconductor device SD2 includes the metal film MF5. Hereinafter, the configuration and manufacturing method of the semiconductor device SD1 according to the present embodiment will be described in detail.

The semiconductor device SD2 includes a metal film MF5. The metal film MF5 is provided so as to cover the side surface of the wiring trench TR1 and the side surface of the via hole VH1. In the example shown in FIG. 8, the metal film MF1 is provided on the side surface of the wiring trench TR1 via the metal film MF5. The metal film MF2 is provided on the side surface of the via hole VH1 via the metal film MF5.
The metal film MF5 is made of, for example, TiN or TaN. Thereby, the adhesion of the metal film MF5 to the interlayer insulating film II2 and the interlayer insulating film II3 can be improved. The metal film MF5 functions as a part of the barrier metal film BF2, for example.

Next, a method for manufacturing the semiconductor device SD2 according to the present embodiment will be described.
First, after forming the interlayer insulating film II2, the metal film MF1, and the interlayer insulating film II3 on the interlayer insulating film II1 in which the conductive film CF1 is embedded, the wiring trench TR1 and the via hole VH1 are formed. In the method for manufacturing the semiconductor device SD2 according to the present embodiment, the process of forming the wiring trench TR1 in the interlayer insulating film II3 and forming the via hole VH1 in the interlayer insulating film II2 is performed in the same manner as in the first embodiment. be able to.

  Next, as shown in FIG. 9A, a metal film MF5 that covers the inner wall of the wiring trench TR1 and the inner wall of the via hole VH1 is formed. In the present embodiment, for example, the metal film MF5 is formed on the inner wall of the wiring trench TR1, the inner wall of the via hole VH1, and the upper surface of the interlayer insulating film II3.

  Next, as shown in FIG. 9B, a part of the conductive film CF1 overlapping the via hole VH1 is removed. In the present embodiment, a part of the metal film MF5 that overlaps the via hole VH1 is removed, and a part of the conductive film CF1 that overlaps the via hole VH1 is removed. Thereby, the conductive film CF1 having the concave portion RC1 on the upper surface is realized. At this time, the portion of the metal film MF5 provided on the upper surface of the interlayer insulating film II3 is also removed at the same time.

Next, as shown in FIG. 10A, a metal film MF3 is formed on the inner wall of the wiring trench TR1, the inner wall of the via hole VH1, and the upper surface of the interlayer insulating film II3. The metal film MF3 can be formed in the same manner as the method for manufacturing the semiconductor device SD1 according to the first embodiment.
Next, as shown in FIG. 10B, a conductive film CF2 is embedded in the wiring trench TR1 and the via hole VH1. The conductive film CF2 can be formed in the wiring trench TR1 and the via hole VH1 similarly to the method for manufacturing the semiconductor device SD1 according to the first embodiment.

Next, a portion of the conductive film CF2 located on the interlayer insulating film II3 is removed using CMP. Next, a portion of the metal film MF3 located on the interlayer insulating film II3 is removed using CMP. As a result, the wiring IC2 constituted by the conductive film CF2 embedded in the wiring trench TR1 and the via plug VP2 constituted by the conductive film CF2 embedded in the via hole VH1 are formed. In this way, a dual damascene wiring structure constituted by the wiring IC2 and the via plug VP2 is obtained.
In the present embodiment, for example, the semiconductor device SD2 is manufactured in this way.

  Also in this embodiment, the same effect as that of the first embodiment can be obtained.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

SD1, SD2 Semiconductor device CF1, CF2 Conductive film IC1, IC2 Wiring VP2, Via plug VH1, Via hole TR1, Wiring trench II1, II2, II3, II4 Interlayer insulating film BF1, BF2 Barrier metal film MF1, MF2, MF3, MF4, MF5 Metal film RC1 Recessed portion OP1 Opening portion PP1 Outer edge portion SB1 Semiconductor substrate MT1 Transistor EL1 Element isolation film GI1 Gate insulating film GE1 Gate electrode DR1 Source / drain region SW1 Side wall CP1 Contact plug

Claims (11)

Forming a second interlayer insulating film on the first interlayer insulating film embedded with the first conductive film;
Forming a first metal film having an opening overlapping the first conductive film on the second interlayer insulating film;
Forming a third interlayer insulating film on the first metal film and the second interlayer insulating film;
Forming a wiring groove overlapping the first metal film and the opening in the third interlayer insulating film, and forming a via hole overlapping the opening in the second interlayer insulating film;
Removing a portion of the first conductive film overlapping the via hole;
Burying a second conductive film in the wiring trench and the via hole;
A method for manufacturing a semiconductor device comprising: In the manufacturing method of the semiconductor device according to claim 1,
Before the step of forming the second interlayer insulating film, comprising a step of forming a second metal film having a thickness smaller than that of the first metal film on the first conductive film;
The step of removing a portion of the first conductive film that overlaps the via hole removes a portion of the second metal film that overlaps the via hole and at the same time removes the portion of the first conductive film. A method for manufacturing a semiconductor device, wherein a part overlapping with a via hole is removed. In the manufacturing method of the semiconductor device according to claim 2,
The method of manufacturing a semiconductor device, wherein the second metal film is made of TiN or TaN. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein in the step of forming the wiring groove and the via hole, the wiring groove is formed so that an outer edge of the first metal film is covered with the third interlayer insulating film. In the manufacturing method of the semiconductor device according to claim 1,
After the step of removing a portion of the first conductive film overlapping the via hole and before the step of filling the second conductive film in the wiring groove and in the via hole, the wiring A method of manufacturing a semiconductor device, comprising: forming a third metal film that covers an inner wall of a groove, an inner wall of the via hole, and an upper surface of the third interlayer insulating film. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the first metal film is made of TiN or TaN. In the manufacturing method of the semiconductor device according to claim 1,
After the step of forming the wiring groove and the via hole, and before the step of removing a portion of the first conductive film overlapping the via hole, the inner wall of the wiring groove and the via hole Forming a fourth metal film covering the inner wall of
The step of removing a part of the first conductive film that overlaps the via hole removes a part of the fourth metal film that overlaps the via hole, and also removes the part of the first conductive film. A method for manufacturing a semiconductor device, wherein a part overlapping with a via hole is removed. A first interlayer insulating film embedded with a first conductive film;
A second interlayer insulating film provided on the first interlayer insulating film and having a via hole overlapping the first conductive film;
A first metal film provided at least around the via hole on the second interlayer insulating film;
A third interlayer insulating film provided on the second interlayer insulating film, having a wiring groove overlapping the via hole, and a part positioned around the wiring groove being positioned on the first metal film;
A second conductive film embedded in the wiring trench and in the via hole;
A semiconductor device comprising: The semiconductor device according to claim 8,
A semiconductor device in which a second metal film is formed on the first conductive film. The semiconductor device according to claim 9.
The second metal film is a semiconductor device made of TiN or TaN. The semiconductor device according to claim 9.
A barrier film is provided between the wiring trench and the via hole, and the second conductive film,
Portions of the barrier film located on the bottom surface and the side surface of the wiring trench are configured by a laminated film of the first metal film and a third metal film made of a material different from the first metal film. Semiconductor device.

Images