CN103871855B - A kind of preparation method of integrated circuit Dual Gate Oxide - Google Patents
A kind of preparation method of integrated circuit Dual Gate Oxide Download PDFInfo
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- CN103871855B CN103871855B CN201210548973.XA CN201210548973A CN103871855B CN 103871855 B CN103871855 B CN 103871855B CN 201210548973 A CN201210548973 A CN 201210548973A CN 103871855 B CN103871855 B CN 103871855B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
Abstract
The present invention relates to semiconductor integrated circuit technical field, disclose the preparation method of a kind of integrated circuit Dual Gate Oxide, including: the substrate surface in place forms field oxide；Ground floor polysilicon is formed on the field oxide surface of place；Substrate surface at high-voltage MOS pipe active area and low pressure metal-oxide-semiconductor active area forms thick grating oxide layer；Photoresist is coated in the integrated circuit surface of semi-finished completing above-mentioned steps；The integrated circuit semi-finished product of coating photoresist being exposed development, makes the surface of described ground floor polysilicon cover one layer of place photoresist, the surface of described high-voltage MOS pipe active area thick grating oxide layer covers one layer of active area photoresist.Using technical solution of the present invention, when etching away the thick grating oxide layer of low pressure metal-oxide-semiconductor, place photoresist can effectively protect the field oxide under ground floor polysilicon not by lateral etching, it is to avoid produces cavity, substantially increases the reliability of product.
Description
Technical field
The present invention relates to semiconductor integrated circuit technical field, particularly relate to the preparation method of a kind of integrated circuit Dual Gate Oxide.
Background technology
In integrated circuits, low pressure metal-oxide-semiconductor is different due to the pressure condition of respective grid with high-voltage MOS pipe, and the thickness of the two corresponding gate oxide is the most different, and usual grid voltage is 5V, corresponding gate oxide thickness is 15 ~ 20nm, thus gate oxide thickness corresponding to high-voltage MOS pipe is bigger.If there is the gate oxide of two kinds of thickness, the most referred to as Dual Gate Oxide in integrated circuits.
Function needs according to integrated circuit, also need to design high value resistor (referred to as high resistant) and electric capacity etc. in addition to low pressure metal-oxide-semiconductor, high-voltage MOS pipe device.The upper bottom crown of the grid of metal-oxide-semiconductor, high resistant and electric capacity can make of polysilicon.
In the prior art, when making integrated circuit Dual Gate Oxide, it is initially formed thick grating oxide layer；Then the thick grating oxide layer needing to make thin oxide gate layer region is etched away；Form thin gate oxide again.As shown in Figure 1, use prior art, when etching away thick grating oxide layer, the field oxide 2 being coated with ground floor polysilicon 5 can occur lateral encroaching, then preparing thin gate oxide 4, Fig. 1 is the schematic diagram of the integrated circuit Dual Gate Oxide that prior art completes, and has been covered each by field oxide 2 on substrate 1, thick grating oxide layer 3 and thin gate oxide 4, the field oxide 2 under ground floor polysilicon 5 produces cavity 8.
The defect of prior art is, during etching away thick grating oxide layer, the field oxide below ground floor polysilicon can occur lateral etching, produces cavity, ultimately results in product defects, affect the reliability of product.
Summary of the invention
It is an object of the invention to provide the preparation method of a kind of integrated circuit Dual Gate Oxide, the problem producing cavity in order to improve present in prior art the field oxide lateral etching under ground floor polysilicon, improves the reliability of product.
The preparation method of integrated circuit Dual Gate Oxide of the present invention, including:
Substrate surface in place forms field oxide；
Ground floor polysilicon is formed on the field oxide surface of place；
Thick grating oxide layer is formed at high-voltage MOS pipe active area and low pressure metal-oxide-semiconductor active area substrate surface；
Photoresist is coated in the integrated circuit surface of semi-finished completing above-mentioned steps；
The integrated circuit semi-finished product of coating photoresist being exposed development, makes ground floor polysilicon surface be coated with one layer of place photoresist, the surface of described high-voltage MOS pipe active area thick grating oxide layer covers one layer of active area photoresist.
The preparation method of described integrated circuit Dual Gate Oxide, after the integrated circuit semi-finished product coating photoresist are exposed development, also includes:
Etch away the thick grating oxide layer of the substrate surface of low pressure metal-oxide-semiconductor active area；
Remove described place photoresist and described active area photoresist；
Substrate surface at low pressure metal-oxide-semiconductor active area forms thin gate oxide；
Second layer polysilicon is formed on the surface of described thin gate oxide and high-voltage MOS pipe active area thick grating oxide layer.
Preferably, each limit of place photoresist exceeds 0.5 ~ 2.0 micron of the limit that ground floor polysilicon is corresponding.
Preferably, described ground floor polysilicon is as high resistant and/or polysilicon capacitance bottom crown.
In the preparation method of integrated circuit Dual Gate Oxide of the present invention; owing to being coated with place photoresist on ground floor polysilicon; therefore; when etching away the thick grating oxide layer of low pressure metal-oxide-semiconductor; place photoresist can effectively protect the field oxide under ground floor polysilicon not by lateral etching; avoid producing cavity, substantially increase the reliability of product.
Accompanying drawing explanation
Fig. 1 is the integrated circuit Dual Gate Oxide structural representation of prior art；
Fig. 2 is the preparation method schematic flow sheet of integrated circuit Dual Gate Oxide of the present invention；
Fig. 3 a to Fig. 3 e is the process schematic representation of the preparation method specific embodiment of integrated circuit Dual Gate Oxide of the present invention.
Reference:
1-substrate 2-field oxide 3-thick grating oxide layer 4-thin gate oxide
5-ground floor polysilicon 6-high resistant 7-double polycrystalline electric capacity bottom crown 8-cavity
9-second layer polysilicon 10-active area photoresist 11-place photoresist
21-place 22-high-voltage MOS pipe active area 23-low pressure metal-oxide-semiconductor active area
Detailed description of the invention
In order to solve present in prior art the field oxide generation lateral etching under ground floor polysilicon, it is easily generated cavity, causes the technical problem of product defects, the invention provides the preparation method of a kind of integrated circuit Dual Gate Oxide.
As in figure 2 it is shown, the preparation method schematic flow sheet of integrated circuit Dual Gate Oxide of the present invention, including:
Step 101, substrate surface in place form field oxide；
Step 102, on the field oxide of place formed ground floor polysilicon；
Step 103, form thick grating oxide layer at high-voltage MOS pipe active area and low pressure metal-oxide-semiconductor active area substrate surface.
Step 104, complete above-mentioned steps integrated circuit surface of semi-finished coat photoresist；
Step 105, integrated circuit semi-finished product to coating photoresist are exposed development, make the surface of ground floor polysilicon cover one layer of place photoresist, and the surface of described high-voltage MOS pipe active area thick grating oxide layer covers one layer of active area photoresist.
In technical solution of the present invention, owing to being coated with one layer of place photoresist at ground floor polysilicon surface, in follow-up etch step, it is to avoid to the field oxide generation lateral etching under ground floor polysilicon, thus decrease the generation in cavity, improve the reliability of product.
The preparation method of integrated circuit Dual Gate Oxide of the present invention, after step 105, also includes:
Etch away the thick grating oxide layer of the substrate surface of low pressure metal-oxide-semiconductor active area；
Remove place photoresist and active area photoresist；
Substrate surface at low pressure metal-oxide-semiconductor active area forms thin gate oxide；
Second layer polysilicon is formed on the surface of thin gate oxide and high-voltage MOS pipe active area thick grating oxide layer.
Preferably, described ground floor polysilicon is as high resistant and/or polysilicon capacitance bottom crown, and ground floor polysilicon, according to the needs of IC design, can be used to prepare different devices.
Preferably, each limit of place photoresist exceeds 0.5 ~ 2.0 micron of the limit that ground floor polysilicon is corresponding.
In preferred embodiments of the present invention, place photoresist covers ground floor polysilicon, each limit of place photoresist exceeds 0.5 ~ 2.0 micron of the limit that ground floor polysilicon is corresponding, when etching away the thick grating oxide layer of substrate surface of low pressure metal-oxide-semiconductor active area, more effectively prevent the place oxide layer lateral etching under ground floor polysilicon, improve the reliability of product.
Show the specific embodiment of the preparation method of integrated circuit Dual Gate Oxide of the present invention such as Fig. 3 a to Fig. 3 e, its main fabrication processing is as follows:
As shown in Figure 3 a, the most artificially mark off high-voltage MOS pipe active area 22, low pressure metal-oxide-semiconductor active area 23 and place 21, form field oxide 2 on substrate 1 surface of place 21；
According to the design of integrated circuit, forming ground floor polysilicon 5 needing to make on the field oxide 2 of the place 21 of polycrystalline silicon device, ground floor polysilicon 5 can be as the bottom crown 7 of high resistant 6 and polysilicon capacitance；
Thick grating oxide layer 3 is formed at high-voltage MOS pipe active area 22 and low pressure metal-oxide-semiconductor active area 23 substrate 1 surface.
As shown in Figure 3 b, at the surface-coated photoresist of the integrated circuit semi-finished product completing above-mentioned steps；
The integrated circuit semi-finished product of coating photoresist are exposed development, the surface making ground floor polysilicon 5 covers one layer of place photoresist 11, and thick grating oxide layer 3 surface making high-voltage MOS pipe active area 22 covers one layer of active area photoresist 10, wherein, place photoresist 11 covers ground floor polysilicon 5, preferably, each limit of place photoresist 11 is beyond 0.5 ~ 2.0 micron of the limit of ground floor polysilicon 5 correspondence.
As shown in Figure 3 c, etch away the thick grating oxide layer 3 on substrate 1 surface of low pressure metal-oxide-semiconductor active area 23, and, the field oxide 2 not having place covered by photoresist is also corroded certain thickness, this thickness is generally equivalent to 1.05 ~ 1.25 times of thick grating oxide layer 3 thickness, field oxide 2 below place photoresist 11 is also fallen sub-fraction by lateral encroaching, generally less than 0.2 micron.
As shown in Figure 3 d, remove the place photoresist 11 on ground floor polysilicon 5 surface and remove the active area photoresist 10 on high-voltage MOS pipe active area thick grating oxide layer surface, after removing photoresist, ground floor polysilicon 5 and field oxide 2 will not produce cavity, field oxide surface is smooth step, it is to avoid the security risk of final products；
Thin gate oxide 4 is formed on substrate 1 surface of low pressure metal-oxide-semiconductor active area 23；
As shown in Figure 3 e, forming second layer polysilicon 9 on the surface of thin gate oxide 4 and high-voltage MOS pipe active area thick grating oxide layer 3, this layer of polysilicon may be used for forming low pressure metal-oxide-semiconductor and the grid of high-voltage MOS pipe.
In the present embodiment, ground floor polysilicon is used to make high resistant and the bottom crown of electric capacity, but the present invention is not limited to this embodiment, the device that ground floor polysilicon makes can be different according to the design of integrated circuit in the position of place with it, such as ground floor polysilicon is only used for making high resistant or being only used for making the bottom crown of electric capacity, in like manner, second layer polysilicon is also not necessarily limited to simply make the grid of MOS, it is also possible to for making the top crown of electric capacity.As long as the Dual Gate Oxide of integrated circuit is prepared after ground floor polysilicon is just applicable to the present invention.
Visible; in the inventive solutions; owing to being coated with place photoresist on ground floor polysilicon; therefore; when etching away the thick grating oxide layer of low pressure metal-oxide-semiconductor, place photoresist can effectively protect the field oxide under ground floor polysilicon not by lateral etching, it is to avoid produces cavity; decrease the defect of product, substantially increase the reliability of product.
Obviously, those skilled in the art can carry out various change and modification without departing from the spirit and scope of the present invention to the present invention.So, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (3)
1. the preparation method of an integrated circuit Dual Gate Oxide, it is characterised in that including:
Substrate surface in place forms field oxide；
Ground floor polysilicon is formed on the field oxide surface of place；
Substrate surface at high-voltage MOS pipe active area and low pressure metal-oxide-semiconductor active area forms thick grating oxide layer；
Photoresist is coated in the integrated circuit surface of semi-finished completing above-mentioned steps；
The integrated circuit semi-finished product of coating photoresist are exposed development, the surface making described ground floor polysilicon covers one layer of place photoresist, the surface of described high-voltage MOS pipe active area thick grating oxide layer covers one layer of active area photoresist, and each limit of described place photoresist is beyond limit 0.5 corresponding to ground floor polysilicon～2.0 microns.
2. the preparation method of the integrated circuit Dual Gate Oxide described in claim 1, it is characterised in that after the integrated circuit semi-finished product coating photoresist are exposed development, also include:
Etch away the thick grating oxide layer of the substrate surface of low pressure metal-oxide-semiconductor active area；
Remove described place photoresist and described active area photoresist；
Substrate surface at low pressure metal-oxide-semiconductor active area forms thin gate oxide；
Second layer polysilicon is formed on the surface of described thin gate oxide and high-voltage MOS pipe active area thick grating oxide layer.
3. the preparation method of integrated circuit Dual Gate Oxide as claimed in claim 1, it is characterised in that described ground floor polysilicon is as high resistant and/or polysilicon capacitance bottom crown.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210548973.XA CN103871855B (en) | 2012-12-17 | 2012-12-17 | A kind of preparation method of integrated circuit Dual Gate Oxide |
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| CN201210548973.XA CN103871855B (en) | 2012-12-17 | 2012-12-17 | A kind of preparation method of integrated circuit Dual Gate Oxide |
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| CN103871855A CN103871855A (en) | 2014-06-18 |
| CN103871855B true CN103871855B (en) | 2016-08-03 |
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| CN105355596A (en) * | 2014-08-20 | 2016-02-24 | 北大方正集团有限公司 | Method for manufacturing CMOS device |
| CN112397591B (en) * | 2020-11-11 | 2022-06-17 | 武汉新芯集成电路制造有限公司 | Semiconductor device comprising LDMOS transistor and manufacturing method |
Citations (5)
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| CN1225507A (en) * | 1998-02-05 | 1999-08-11 | 国际商业机器公司 | Method for dual gate oxide dual workfunction CMOS |
| US6100141A (en) * | 1998-11-04 | 2000-08-08 | United Microelectronics Corp. | Method for forming electrostatic discharge (ESD) protection circuit |
| US6573568B2 (en) * | 2001-06-01 | 2003-06-03 | Winbond Electronics Corp. | ESD protection devices and methods for reducing trigger voltage |
| CN1819198A (en) * | 2004-12-31 | 2006-08-16 | 东部亚南半导体株式会社 | Semiconductor device and fabricating method thereof |
| CN101217162A (en) * | 2008-01-04 | 2008-07-09 | 东南大学 | A high voltage N-type MOS transistor and the corresponding manufacturing method |
-
2012
- 2012-12-17 CN CN201210548973.XA patent/CN103871855B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1225507A (en) * | 1998-02-05 | 1999-08-11 | 国际商业机器公司 | Method for dual gate oxide dual workfunction CMOS |
| US6100141A (en) * | 1998-11-04 | 2000-08-08 | United Microelectronics Corp. | Method for forming electrostatic discharge (ESD) protection circuit |
| US6573568B2 (en) * | 2001-06-01 | 2003-06-03 | Winbond Electronics Corp. | ESD protection devices and methods for reducing trigger voltage |
| CN1819198A (en) * | 2004-12-31 | 2006-08-16 | 东部亚南半导体株式会社 | Semiconductor device and fabricating method thereof |
| CN101217162A (en) * | 2008-01-04 | 2008-07-09 | 东南大学 | A high voltage N-type MOS transistor and the corresponding manufacturing method |
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Effective date of registration: 20220718 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District Cheng Fu Road 298, founder building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |
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