CN102738062B - Method for manufacturing semiconductor device - Google Patents
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- CN102738062B CN102738062B CN201110081785.6A CN201110081785A CN102738062B CN 102738062 B CN102738062 B CN 102738062B CN 201110081785 A CN201110081785 A CN 201110081785A CN 102738062 B CN102738062 B CN 102738062B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, comprising the steps of: providing a semiconductor substrate and an intermediate metal layer formed on the semiconductor substrate; forming an etch stop layer of a top metal layer on the intermediate metal layer; baking the semiconductor substrate; rinsing the etch stop layer by using a cleaning agent; and forming a dielectric material layer on the etch stop layer. In the method, as baking and rinsing steps are added in the process of forming the top metal layer, the etch stop layer can be effectively prevented from releasing stress to form a peeling source in the subsequent process of forming the dielectric material layer, and peeling defect on the dielectric material layer and possible peeling phenomenon can be avoided. Moreover, the impact of peeling defect and peeling phenomenon on subsequent processes can be prevented, and yield of qualified chips can be improved.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of method of making semiconductor device.
Background technology
Current semiconductor device processing technology develop rapidly, semiconductor device has had deep-submicron structure, comprises the semiconductor element of enormous quantity in integrated circuit.In large scale integrated circuit like this, between element, high-performance, highdensity connection not only interconnect in single interconnection layer, and will between multilayer, interconnect.Therefore, conventionally adopt multilayer interconnect structure, the multilayer interconnect structure that particularly utilizes dual damascene (dual-damascene) technique to form, it forms groove (trench) and hole (via) in advance in interlayer dielectric layer, then fills above-mentioned groove and hole with for example copper of electric conducting material (Cu).Finally, on the metal level of top, form aluminium wiring layer, so that the interconnect architecture in device is all connected to the aluminium wiring layer on top layer.
Figure 1A is the sectional view of the interconnection structure of existing employing dual-damascene technics formation.As shown in Figure 1A, this interconnection structure is formed in multilayer interlayer dielectric layer 110,130 and 150, and interlayer dielectric layer 110,130 and 150 is deposited on Semiconductor substrate (not shown) successively.Substrate layer 110b, intermediate metal layer 130b and top metal level 150b are formed at respectively in interlayer dielectric layer 120,130 and 150.In interconnection structure, may comprise the interlayer dielectric layer 130 of multiple intermediate metal layer 130b and this intermediate metal layer of multiple encirclement 130b.Be formed on contact hole 110a in interlayer dielectric layer 110 for connecting substrate layer 110b and being formed on the element (not shown) of semiconductor substrate surface.Similarly, be formed on interlayer dielectric layer 130 and through hole 130a in 150 with 150a for being connected substrate layer 110b and intermediate metal layer 130b and intermediate metal layer 130b and top metal level 150b.In the time comprising multiple intermediate metal layer 130b in this interconnection structure, through hole 130a is also for connecting two adjacent intermediate metal layer 130b.On the metal level 150b of top, be formed with aluminium wiring layer 170, this aluminium wiring layer 170 comprises passivation layer 171-174 and aluminum pad (Al pad) 170a.
Figure 1B shows the sectional view of making in the top metal level 150b process shown in Figure 1A.As shown in Figure 1B, first, first form thinner etching stop layer 151 on interlayer dielectric layer 130, the material of this etching stop layer 151 is generally silicon nitride; Then on etching stop layer 151, form thicker dielectric materials layer 152, the material of this dielectric materials layer 152 is generally plain silex glass (USG); Then, form hard mask layer 153 on dielectric materials layer 152, the material of described hard mask layer 153 is generally silicon oxynitride; Finally, on hard mask layer 153, form the figuratum photoresist layer of tool, and in interlayer dielectric layer 150, form through hole and groove through steps such as exposure, developments, then in through hole and groove, fill Cu to form top metal level (not shown).
In order to reduce the parasitic capacitance between interconnecting metal, interlayer dielectric layer 130 is normally made up of the less material of dielectric constant, for example, and black diamond (black diamond, BD) etc.But, because the stress distribution between black diamond and silicon nitride is inhomogeneous, cause the adhesion between etching stop layer 151 and interlayer dielectric layer 130 poor.When form thicker dielectric materials layer 152 again on etching stop layer 151 time, in etching stop layer 151, be easy to form the source of peeling off.Forming subsequently in the process of dielectric materials layer 152; etching stop layer 151 can produce and peel off at the fringe region of whole Semiconductor substrate; peeling off particle can further be embedded in dielectric materials layer 152; peel off defect and form in dielectric materials layer 152, finally probably cause dielectric materials layer 152 also to occur peeling phenomenon.These peel off defect and peel off particle and will produce a very large impact subsequent technique, and reduce the yields of chip.
Therefore, a kind of method of making semiconductor device need to be provided, and to avoid in the process of formation top metal level, in interlayer dielectric layer, defect or contingent peeling phenomenon are peeled off in formation, prevent peeling off defect and peeling phenomenon exerts an influence to subsequent technique, and then improve the yields of chip.
Summary of the invention
For fear of in the process of formation top metal level, in interlayer dielectric layer, form and peel off defect or contingent peeling phenomenon, the present invention proposes a kind of method of making semiconductor device, comprising: Semiconductor substrate is provided and is formed on the intermediate metal layer in described Semiconductor substrate; On described intermediate metal layer, form the etching stop layer of top metal level; Described Semiconductor substrate is carried out to baking procedure; Use irrigation to carry out rinsing step to described etching stop layer; On described etching stop layer, form dielectric materials layer.
Preferably, described method is also included in the step that forms through hole and top metal level in described dielectric materials layer.
Preferably, the baking temperature of described baking procedure is identical with the temperature that forms described dielectric materials layer.
Preferably, the baking time of described baking procedure is identical with the formation time of described dielectric materials layer.
Preferably, the material of described dielectric materials layer is plasma enhanced oxidation thing.
Preferably, described gas ions enhancing oxide is plain silex glass or fluorine-containing silex glass.
Preferably, described baking temperature is 350
oc-450
oc.
Preferably, described baking temperature is 380
oc-420
oc.
Preferably, described baking time is 50-250 second.
Preferably, described baking time is 100-200 second.
Preferably, described irrigation is one or more in helium, argon gas and nitrogen.
Preferably, described irrigation is nitrogen, and the flow velocity of described nitrogen is 60-100 cc/min.
Preferably, described irrigation also comprises deionized water, and described deionized water sprays under described nitrogen punching press.
Preferably, after finishing, described rinsing step also comprises the described Semiconductor substrate of rotation, with the step that described Semiconductor substrate is dried.
Preferably, in described flushing process, make described Semiconductor substrate rotation.
Preferably, the rotary speed of described Semiconductor substrate is 400-600 rev/min.
Preferably, the time of described flushing is 20-40 second.
Preferably, the time of described flushing is 25-35 second.
Preferably, the material of described etching stop layer is the silicon nitride of silicon nitride or carbon containing.
Method of the present invention by increasing baking and rinsing step in the technique that forms top metal level, can effectively avoid in the process of follow-up formation dielectric materials layer, etching stop layer discharges stress and forms the source of peeling off, and then can avoid forming and peeling off defect and contingent peeling phenomenon in dielectric materials layer.Further, can prevent peeling off defect and peeling phenomenon exerts an influence to subsequent technique, and then improve the yields of chip.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A is the sectional view of the interconnection structure of existing employing dual-damascene technics formation;
Figure 1B shows the sectional view of making in the top metal level process shown in Figure 1A;
Fig. 2 adopts according to the flow chart of the method for the making semiconductor device of one aspect of the invention;
Fig. 3 makes the sectional view in the metal level process of top according to one aspect of the invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
Fig. 2 adopts according to the flow chart of the method for the making semiconductor device of one aspect of the invention, and Fig. 3 makes the sectional view in the metal level process of top according to one aspect of the invention.Below in conjunction with Fig. 2 and Fig. 3, the method for manufacture semiconductor device of the present invention is described.
Execution step 201, provides Semiconductor substrate and is formed on the intermediate metal layer in this Semiconductor substrate.
Below in conjunction with Fig. 3, said structure is described in detail.First Semiconductor substrate (not shown) is provided, then in this Semiconductor substrate, forms substrate layer 310b and intermediate metal layer 330b, wherein substrate layer 310b and intermediate metal layer 330b are respectively formed in interlayer dielectric layer 310 and 330.Should be understood that, although only show an intermediate metal layer 330b in Fig. 3, but those skilled in the art should be understood that, under normal circumstances, said structure can comprise the interlayer dielectric layer 330 of multiple intermediate metal layer 330b and this intermediate metal layer of multiple encirclement 330b.Multiple intermediate metal layer 330b and interlayer dielectric layer 330 are formed on substrate layer 310b and interlayer dielectric layer 310 successively.In order to reduce the parasitic capacitance between interconnecting metal layer, interlayer dielectric layer 330 is normally made up of the less material of dielectric constant, for example, and black diamond (black diamond, BD) etc.
In interlayer dielectric layer 310, substrate layer 310b below be formed with contact hole 310a, contact hole 310a is for connecting substrate layer 310b and be formed on the component structure (not shown) of semiconductor substrate surface.Described component structure comprises grid, source electrode, drain electrode, word line or resistance etc.In interlayer dielectric layer 330, intermediate metal layer 330b below be formed with through hole 330a, through hole 330a is used for connecting substrate layer 310b and intermediate metal layer 330b.In the time that said structure comprises multiple intermediate metal layer 330b, through hole 330a is also for connecting two adjacent intermediate metal layer 330b.
Perform step 202, on intermediate metal layer, form the etching stop layer of top metal level.
With reference to Fig. 3, on intermediate metal layer 330b and interlayer dielectric layer 330, form etching stop layer 351, the material of etching stop layer 351 can be the silicon nitride (NDC) of silicon nitride or carbon containing etc.This etching stop layer 351 can be used as the etching stop layer while subsequently dielectric materials layer (not shown) being carried out to etching.The formation method of etching stop layer 351 can be chemical vapour deposition technique, physical vaporous deposition or sputtering method etc.
Execution step 203, toasts Semiconductor substrate.
Preferably, the baking temperature of this baking procedure is identical with the temperature that forms subsequently dielectric materials layer, the formation technique of follow-up dielectric materials layer is exerted an influence avoiding, and guarantees the reliability of subsequent technique.According to one embodiment of the present invention, the material of dielectric materials layer is plain silex glass (USG), or fluorine-containing silex glass (FSG).Conventionally, the depositing temperature of this dielectric materials layer is 350
oc-450
oc, therefore, the baking temperature of baking procedure is 350
oc-450
oc.Preferably, this baking temperature can be 380
oc-420
oc.
Preferably, the baking time of described baking procedure is identical with the formation time of dielectric materials layer subsequently.When dielectric materials layer is that while adopting chemical vapour deposition (CVD) or physical vaporous deposition to form, described formation time refers to the effective time that deposition of dielectric materials layer uses, do not comprise and vacuumize, heat up and the additional process time such as cooling.When dielectric materials layer is that while adopting sputtering method to form, described formation time refers to the effective time that sputter dielectric materials layer uses, do not comprise and vacuumize, heat up and the additional process time such as cooling.According to one embodiment of the present invention, the material of dielectric materials layer is plain silex glass, and conventionally, the formation time of this dielectric materials layer is 50-250 second, and therefore, the baking time of baking procedure is 50-250 second.Preferably, this baking temperature can be 100-200 second.
Execution step 204, is used irrigation to rinse etching stop layer.Preferably, in flushing process, Semiconductor substrate is rotated.In flushing process, make Semiconductor substrate rotation not only can improve the uniformity of flushing, and it is long-time to avoid irrigation to stop on etching stop layer surface by rotation Semiconductor substrate, and then prevents that irrigation from exerting an influence to etching stop layer.Under normal circumstances, Semiconductor substrate is fixed on chassis, can drive Semiconductor substrate rotation by swivel base.Preferably, the rotary speed of Semiconductor substrate is 400-600 rev/min.More preferably, the rotary speed of Semiconductor substrate is 450-550 rev/min.Preferably, the time of described flushing is 20-40 second.More preferably, the time of described flushing is 25-35 second.
Described irrigation can be one or more in the inert gases such as helium, argon gas and nitrogen.Consider production cost, preferably, described irrigation is nitrogen.In flushing process, the flow velocity of nitrogen is to be 60-100 cc/min, and preferably, the flow velocity of nitrogen is 80 cc/min.
In order to improve the rinse capability to particle on etching stop layer, preferably, described irrigation also comprises deionized water, and deionized water sprays under nitrogen punching press.But it should be noted that in the time that described irrigation comprises deionized water, being conventionally applicable to etching stop layer is non-water absorption material.Be easy water absorption material for etching stop layer, for example, when the silicon nitride of carbon containing (NDC), conventionally select irrigation not comprise the scheme of deionized water.In addition,, in the time that irrigation comprises deionized water, after finishing, described rinsing step also comprises rotation Semiconductor substrate, with the step that Semiconductor substrate is dried.
By above-mentioned baking procedure, can discharge the stress producing in etching stopping layer deposition process.Take the material of etching stop layer as silicon nitride is as example, can make unnecessary nitrogen and the silicon in silicon nitride lattice, inlayed diffuse to the surface of etching stop layer by baking procedure, and form silicon nitride particle.Then by rinsing step subsequently, remove the silicon nitride particle on etching stop layer surface.Can avoid like this in the process of follow-up formation dielectric materials layer, etching stop layer discharges stress, forms and peels off source, and then avoid forming and peeling off defect or contingent peeling phenomenon in dielectric materials layer.
Execution step 205 forms dielectric materials layer on etching stop layer.
The material of this dielectric materials layer can be plasma enhanced oxidation thing (PEOX), for example, and plain silex glass (USG) or fluorine-containing silex glass (FSG) etc.The formation method of dielectric materials layer can be chemical vapour deposition technique, physical vaporous deposition or sputtering method etc.
In addition, be also included in the step that forms through hole and top metal level in dielectric materials layer according to the method for making semiconductor device of the present invention, described through hole is used for connecting intermediate metal layer and top metal level.Form through hole and top metal level and can adopt the conventional method in this area.According to one embodiment of the present invention, on dielectric materials layer, form successively hard mask layer and the figuratum photoresist layer of tool; Then take the figuratum photoresist layer of tool as mask carries out etching to hard mask layer and dielectric materials layer successively, in dielectric materials layer, form through hole and groove; Finally, in through hole and groove, fill metal.Be understandable that, the method is only an embodiment of the invention, is not construed as limiting the invention.
Method of the present invention by increasing baking and rinsing step in the technique that forms top metal level, can effectively avoid in the process of follow-up formation dielectric materials layer, etching stop layer discharges stress and forms the source of peeling off, and then can avoid forming and peeling off defect and contingent peeling phenomenon in dielectric materials layer.Further, can prevent peeling off defect and peeling phenomenon exerts an influence to subsequent technique, and then improve the yields of chip.
Have according to the semiconductor device of execution mode manufacture as mentioned above and can be applicable in multiple integrated circuit (IC).For example memory circuitry according to IC of the present invention, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcie arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-mentioned execution mode, but should be understood that, above-mentioned execution mode is the object for giving an example and illustrating just, but not is intended to the present invention to be limited within the scope of described execution mode.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-mentioned execution mode, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (19)
1. a method of making semiconductor device, comprising:
Semiconductor substrate is provided and is formed on the intermediate metal layer in described Semiconductor substrate;
On described intermediate metal layer, form the etching stop layer of top metal level;
Described Semiconductor substrate is carried out to baking procedure, to discharge the stress producing in described etching stopping layer deposition process;
Use irrigation to carry out rinsing step to described etching stop layer, implement described baking procedure and at the particle that surface was produced of described etching stop layer to remove;
On described etching stop layer, form dielectric materials layer.
2. the method for claim 1, is characterized in that, described method is also included in the step that forms through hole and top metal level in described dielectric materials layer.
3. the method for claim 1, is characterized in that, the baking temperature of described baking procedure is identical with the temperature that forms described dielectric materials layer.
4. the method for claim 1, is characterized in that, the baking time of described baking procedure is identical with the formation time of described dielectric materials layer.
5. the method for claim 1, is characterized in that, the material of described dielectric materials layer is plasma enhanced oxidation thing.
6. method as claimed in claim 5, is characterized in that, it is plain silex glass or fluorine-containing silex glass that described gas ions strengthens oxide.
7. method as claimed in claim 3, is characterized in that, described baking temperature is 350 ℃-450 ℃.
8. method as claimed in claim 7, is characterized in that, described baking temperature is 380 ℃-420 ℃.
9. method as claimed in claim 4, is characterized in that, described baking time is 50-250 second.
10. method as claimed in claim 9, is characterized in that, described baking time is 100-200 second.
11. the method for claim 1, is characterized in that, described irrigation is one or more in helium, argon gas and nitrogen.
12. the method for claim 1, is characterized in that, described irrigation is nitrogen, and the flow velocity of described nitrogen is 60-100 cc/min.
13. methods as claimed in claim 12, is characterized in that, described irrigation also comprises deionized water, and described deionized water sprays under described nitrogen punching press.
14. methods as claimed in claim 13, is characterized in that, also comprise the described Semiconductor substrate of rotation, with the step that described Semiconductor substrate is dried after described rinsing step finishes.
15. the method for claim 1, is characterized in that, in described flushing process, make described Semiconductor substrate rotation.
16. methods as claimed in claim 15, is characterized in that, the rotary speed of described Semiconductor substrate is 400-600 rev/min.
17. the method for claim 1, is characterized in that, the time of described flushing is 20-40 second.
18. methods as claimed in claim 17, is characterized in that, the time of described flushing is 25-35 second.
19. the method for claim 1, is characterized in that, the material of described etching stop layer is the silicon nitride of silicon nitride or carbon containing.
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| CN201110081785.6A CN102738062B (en) | 2011-04-01 | 2011-04-01 | Method for manufacturing semiconductor device |
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| CN102738062B true CN102738062B (en) | 2014-06-04 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767171A (en) * | 2004-10-14 | 2006-05-03 | 三星电子株式会社 | Etch stop structure and manufacture method, and semiconductor device and manufacture method |
| CN101154585A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming etch stop layer and double mosaic structure |
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| US6821571B2 (en) * | 1999-06-18 | 2004-11-23 | Applied Materials Inc. | Plasma treatment to enhance adhesion and to minimize oxidation of carbon-containing layers |
| US7187081B2 (en) * | 2003-01-29 | 2007-03-06 | International Business Machines Corporation | Polycarbosilane buried etch stops in interconnect structures |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1767171A (en) * | 2004-10-14 | 2006-05-03 | 三星电子株式会社 | Etch stop structure and manufacture method, and semiconductor device and manufacture method |
| CN101154585A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming etch stop layer and double mosaic structure |
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