CN102087998B - Dual polycrystalline structure device and manufacturing method thereof - Google Patents
Dual polycrystalline structure device and manufacturing method thereof Download PDFInfo
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- CN102087998B CN102087998B CN200910188619.9A CN200910188619A CN102087998B CN 102087998 B CN102087998 B CN 102087998B CN 200910188619 A CN200910188619 A CN 200910188619A CN 102087998 B CN102087998 B CN 102087998B
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Abstract
The invention relates to a method for manufacturing a dual polycrystalline structure device, which comprises the following steps of: forming a pit and an active area on a substrate, and thermally growing a field oxide layer; performing thermal oxide growth of a first grid oxide layer; depositing a first polycrystalline silicon layer; forming a polycrystalline silicon resistor by plasma injection; forming a bottom plate and a first grid of a polycrystalline silicon capacitor by plasma injection, and removing the redundant first polycrystalline layer by etching; performing thermal treatment on the dual polycrystalline structure device; performing thermal oxide growth of a second grid oxide layer and growing an insulation medium; performing threshold adjustment and injection; depositing a second polycrystalline silicon layer; and forming a top plate and a second grid of the polycrystalline silicon capacitor by plasma injection, and etching to remove the redundant second polycrystalline silicon layer. In the dual polycrystalline structure device manufactured by the method provided by the invention, the grids of high and low-voltage devices are manufactured by two layers of different polycrystalline silicon, the processes such as thermal treatment and grid oxide layer growth are separated, so the parameter characteristics of high and low-voltage devices can be adjusted independently without influencing one another.
Description
[technical field]
The present invention relates to integrated circuit fabrication process, relate in particular to a kind of pair of polycrystalline structure device, also relate to the manufacture method of a kind of pair of polycrystalline structure device.
[background technology]
Two polycrystalline (Double Poly) technique is widely used in integrated circuit manufacture; but the large-scale along with integrated circuit; make the integrated level of manufacture of semiconductor more and more higher; complicated one of them result of bringing of technique is that the compatibility between device requires to improve; expedited the emergence of and on same chip, made bipolar tube (Bipolar), the technique of the devices such as CMOS and DMOS (BCD technique).Because part category is various, must accomplish the compatibility of high tension apparatus and low-voltage device; The compatibility of bipolar process and CMOS technique, the DMOS of high-voltage CMOS and various puncture voltages is compatible.
In traditional two polycrystalline techniques, the gate electrode of all devices is all to adopt same layer polysilicon.The bottom crown of for example grid using the first polysilicon layer as metal-oxide-semiconductor, and electric capacity; The second polysilicon layer is used for doing resistance, and the top crown of electric capacity.Its technological process is: the first step, first with mode deposit one deck polysilicon of low-pressure chemical vapor phase deposition (LPCVD) and it is injected, follow depositing metal (titanium on polysilicon layer, cobalt, Deng) or metallide (tungsten silicon) to obtain lower resistance, then by photoetching and corrosion, remove except unnecessary polysilicon; Second step, the dielectric layer of deposit electric capacity; The 3rd step: deposit the second polysilicon layer, by injecting and form polysilicon resistance compared with low dosage, then by the top crown of Selective implantation electric capacity and the exit of polysilicon resistance, then by photoetching and the unnecessary polysilicon of erosion removal.Thereby in disk surfaces, form grid, polysilicon resistance and the polysilicon capacitance of polysilicon.
Adopt this traditional structure can cause following problem: because the gate electrode of all devices is all to adopt same layer polysilicon, in device manufacturing processes, will certainly influence each other, what especially the different heat treatment process of high-low voltage device was brought influences each other, and can cause the change of device electrical performance.In order to eliminate this impact, must adopt other means to adjust device, make process complications, the device construction cycle is elongated.
[summary of the invention]
The interactional problem of high-low pressure grid causing in order to solve traditional double polycrystalline technique, is necessary to provide the manufacture method of a kind of pair of polycrystalline structure device.
A manufacture method for pair polycrystalline structure device, comprises the following steps: on substrate, form trap and active area, and the raw long field oxide layer of heat; Thermal oxide growth the first grid oxide layer; Deposit the first polysilicon layer; Adopt plasma to inject and form polysilicon resistance; By plasma, inject and form polysilicon capacitance bottom crown and first grid, and etch away the first unnecessary polysilicon layer; Described pair of polycrystalline structure device heat-treated; Thermal oxide growth the second grid oxide layer, and the dielectric of growing; Threshold value adjustment is injected; Deposit the second polysilicon layer; By plasma, inject and form polysilicon capacitance top crown and second grid, and etch away the second unnecessary polysilicon layer.
Preferably, the thickness of described the first grid oxide layer is 6nm～200nm.
Preferably, described growth dielectric, is in thermal oxide growth the second grid oxide layer, on polysilicon capacitance bottom crown, to carry out heat growth.
Preferably, described dielectric is silicon dioxide.
Preferably, it is not need photoetching that described threshold value adjustment is injected, and directly carries out.
In order to solve the interactional problem of high-low pressure grid of traditional double polycrystalline structure device, be also necessary to provide a kind of pair of polycrystalline structure device.
A kind of pair of polycrystalline structure device, comprise substrate, the first grid oxide layer of substrate surface, the second grid oxide layer, an oxygen layer, first grid on the first grid oxide layer, second grid on the second grid oxide layer, polysilicon resistance, polysilicon capacitance bottom crown on the oxygen layer of field, the dielectric on polysilicon capacitance bottom crown surface, the polysilicon capacitance top crown on dielectric; Described polysilicon capacitance bottom crown, polysilicon resistance and first grid adopt same polysilicon layer to form, and described polysilicon capacitance top crown and second grid adopt same polysilicon layer to form.
Preferably, described the first grid oxide layer and the second grid oxide layer are to grow in different steps.
Preferably, the thickness of described the first grid oxide layer is 6nm～200nm.
The above-mentioned pair of polycrystalline structure device and manufacture method thereof, utilize two-layer different polysilicon respectively as the grid of high and low pressure device, the techniques such as the heat treatment of high-low voltage device, growth of gate oxide layer is separated, the parameter characteristic of high-low voltage device can independently be adjusted, be independent of each other.
[accompanying drawing explanation]
Fig. 1 is the schematic diagram of the two polycrystalline structure devices of the present invention.
[embodiment]
Fig. 1 is the schematic diagram of the two polycrystalline structure devices of the present invention.The manufacture method of two polycrystalline structure devices comprises the following steps:
(1) adopt the known standard technology of those skilled in the art on substrate 100, to form trap and active area (not shown), and the raw long field oxide layer 109 of heat.
(2) thermal oxide growth the first grid oxide layer 101.This layer is the oxide layer of high tension apparatus grid, and thickness is 6nm～200nm, can adjust according to the parameter request of high tension apparatus, and can not impact the oxide layer of low-voltage device grid, also just can not impact the performance of low-voltage device.The lower devices of puncture voltage such as described high tension apparatus refers to the higher devices of puncture voltage such as the known DMOS of those skilled in the art, IGBT, JFET, and low-voltage device refers to low voltage CMOS, BJT.
(3) deposit the first polysilicon layer.In a preferred embodiment, adopt the technique of low-pressure chemical vapor phase deposition (LPCVD) to carry out deposit to this polysilicon; In other embodiments, also can adopt the techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) to realize.
(4) the first polysilicon layer is carried out to plasma and inject formation polysilicon resistance 102, in a preferred embodiment, adopt phosphorus or potassium to inject, implantation dosage is adjusted according to actual resistance demand.
(5) the first polysilicon layer is carried out to plasma and inject formation polysilicon capacitance bottom crown 103 and first grid 104, and etch away resistance 102, bottom crown 103, first grid 104 the first unnecessary polysilicon layer in addition.
(6) according to the needed parameter of high tension apparatus, two polycrystalline structure devices are heat-treated.Due to now also formation of low-voltage device, therefore can not impact the characteristic of low-voltage device.
(7) thermal oxide growth low pressure grid oxide layer 105, the oxide layer of growing on bottom crown 103, forms dielectric 106 simultaneously.The second grid oxide layer 105 is oxide layers of low-voltage device grid, and thickness can be adjusted according to the parameter request of low-voltage device.The dielectric 106 of growing on polysilicon capacitance bottom crown when utilizing thermal oxide growth the second grid oxide layer, has saved the step of deposit in traditional handicraft or growth dielectric 106, has accelerated speed of production, has reduced production cost.
(8) the threshold value adjustment of area of low pressure is injected.By plasma injection technology, the voltage threshold of low-voltage device is adjusted.Because the channel surface of high-pressure area is now covered by first grid 104, therefore can directly inject, with respect to traditional handicraft, saved the step of a photoetching, accelerated speed of production, reduced production cost.
(9) deposit the second polysilicon layer.In a preferred embodiment, adopt the technique of low-pressure chemical vapor phase deposition (LPCVD) to carry out deposit to this polysilicon; In other embodiments, also can adopt the techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD) to realize.
(10) by plasma, inject the second polysilicon layer and form polysilicon capacitance top crown 108 and second grid 107, and etch away top crown 108, second grid 107 the second unnecessary polysilicon layer in addition.
Deposit separator afterwards, metal line, passivation step can be undertaken by the known standard technology of those skilled in the art, do not repeat them here.
As shown in Figure 1, adopt two polycrystalline structure devices of said method manufacture to comprise substrate 100, the first grid oxide layer 101 of substrate surface, the second grid oxide layer 105, an oxygen layer 109, first grid 104 on the first grid oxide layer 101, second grid 107 on the second grid oxide layer 105, polysilicon resistance 102, polysilicon capacitance bottom crown 103 on field oxygen layer 109, the dielectric 106 on polysilicon capacitance bottom crown 103 surfaces, the polysilicon capacitance top crown 108 on dielectric 106.
The two polycrystalline structure devices that adopt the inventive method to manufacture, utilize two-layer different polysilicon respectively as the grid of high and low pressure device, the techniques such as the heat treatment of high-low voltage device, growth of gate oxide layer is separated, the parameter characteristic of high-low voltage device can independently be adjusted, be independent of each other.The dielectric of growing on polysilicon capacitance bottom crown when utilizing thermal oxide growth low pressure grid oxide layer, has saved the step of deposit in traditional handicraft or growth dielectric; Channel surface due to higher-pressure region while carrying out the threshold value adjustment injection of area of low pressure is covered by high pressure grid, therefore can directly inject, and has saved the step of a photoetching, thereby accelerated speed of production with respect to traditional handicraft, has reduced production cost.
The above embodiment has only expressed embodiments of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (5)
1. a manufacture method for two polycrystalline structure devices, comprises the following steps:
On substrate, form trap and active area, and the raw long field oxide layer of heat;
Thermal oxide growth the first grid oxide layer;
Deposit the first polysilicon layer;
Adopt plasma to inject and form polysilicon resistance;
By plasma, inject and form polysilicon capacitance bottom crown and first grid, and etch away the first unnecessary polysilicon layer;
Described pair of polycrystalline structure device heat-treated;
Thermal oxide growth the second grid oxide layer, and the dielectric of growing;
Threshold value adjustment is injected;
Deposit the second polysilicon layer;
By plasma, inject and form polysilicon capacitance top crown and second grid, and etch away the second unnecessary polysilicon layer.
2. the manufacture method of according to claim 1 pair of polycrystalline structure device, is characterized in that: the thickness of described the first grid oxide layer is 6nm～200nm.
3. the manufacture method of according to claim 1 pair of polycrystalline structure device, is characterized in that: described growth dielectric is in thermal oxide growth the second grid oxide layer, on polysilicon capacitance bottom crown, to carry out heat growth.
4. the manufacture method of according to claim 3 pair of polycrystalline structure device, is characterized in that: described dielectric is silicon dioxide.
5. the manufacture method of according to claim 1 pair of polycrystalline structure device, is characterized in that: it is not need photoetching that described threshold value adjustment is injected, and directly carries out.
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| CN103489830B (en) * | 2012-06-08 | 2016-10-05 | 北大方正集团有限公司 | A kind of preparation method of integrated circuit |
| CN103578949B (en) * | 2012-07-30 | 2016-11-02 | 上海华虹宏力半导体制造有限公司 | Grid polycrystalline silicon and polysilicon resistance integrated manufacturing method |
| CN104347504A (en) * | 2013-08-08 | 2015-02-11 | 北大方正集团有限公司 | Manufacturing method of mixed signal integrated circuit |
| CN107785324A (en) * | 2017-09-19 | 2018-03-09 | 上海华虹宏力半导体制造有限公司 | High-pressure process integrated circuit method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
| CN101013664A (en) * | 2006-01-30 | 2007-08-08 | 三洋电机株式会社 | Method of manufacturing semiconductor device |
| CN101483153A (en) * | 2008-01-07 | 2009-07-15 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor device manufacturing process capable of being optimized |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
| CN101013664A (en) * | 2006-01-30 | 2007-08-08 | 三洋电机株式会社 | Method of manufacturing semiconductor device |
| CN101483153A (en) * | 2008-01-07 | 2009-07-15 | 中芯国际集成电路制造(上海)有限公司 | Semi-conductor device manufacturing process capable of being optimized |
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Effective date of registration: 20170926 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214000 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |