CN106158961B - Plane VDMOS device production method - Google Patents
Plane VDMOS device production method Download PDFInfo
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- CN106158961B CN106158961B CN201510184574.3A CN201510184574A CN106158961B CN 106158961 B CN106158961 B CN 106158961B CN 201510184574 A CN201510184574 A CN 201510184574A CN 106158961 B CN106158961 B CN 106158961B
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Abstract
The present invention provides a kind of plane VDMOS device production method, comprising: provides substrate, is sequentially formed with gate oxide, polysilicon layer and the first silicon nitride layer on substrate surface；The gate oxide other than preset first area, polysilicon layer and the first silicon nitride layer are removed, the gate oxide being located in first area, polysilicon layer and the first silicon nitride layer are retained；The second silicon nitride layer is formed on the surface of entire device, is returned by silicon nitride and forms grid at quarter；It is injected by autoregistration, forms body area and source region；By etching, removal is located at body area and source region outside grid, and the depth etched is greater than the depth in body area；Form the buffer area being located at below body area edge；In entire device surface dielectric layer deposited, the dielectric layer in preset third region is removed, retains the dielectric layer for surrounding part buffer area；Deposited metal.Plane VDMOS device production method provided by the invention, manufacturing process is simpler, and manufacturing cost is lower.
Description
Technical field
The present invention relates to semiconductor chip fabrication process technical fields more particularly to a kind of plane VDMOS device to make
Method.
Background technique
Longitudinal bilateral diffusion field-effect tranisistor (VDMOS) is one of most common power transistor, as a kind of
Voltage-controlled device controls channel by gate voltage signal and is formed, to control source electrode and drain current conducting.VDMOS
The advantages of having both bipolar transistor and common MOS device.Therefore, whether switch application or linear applications, VDMOS are reasons
The power device thought.
In the manufacturing process of existing VDMOS, the production of VDMOS active area is generally required by photoetching, wet etching, is done
Method etching, ion implanting and ion the methods of drive in and can just complete the production.Wherein, the photoetching treatment of VDMOS is respectively occurring at AA
Area, polycrystal layer, source region, in the manufacturing process of contact hole and metal layer, i.e. VDMOS is needed could by the step of 5 photoetching
It completes the production.
The manufacturing process of existing VDMOS production method is many and diverse, and manufacturing cost is higher.
Summary of the invention
The present invention provides a kind of plane VDMOS device production method, to solve manufacturing process in existing production method
It is many and diverse, the higher problem of manufacturing cost.
Plane VDMOS device production method provided by the invention, comprising:
Substrate is provided, is sequentially formed with gate oxide, polysilicon layer and the first silicon nitride layer on the substrate surface；
The gate oxide other than preset first area, polysilicon layer and the first silicon nitride layer are removed, with reserved bit
In the gate oxide in the first area, polysilicon layer and the first silicon nitride layer；
The second silicon nitride layer is formed on the surface of entire device, second silicon nitride layer in predeterminable area is removed, protects
It stays and is located at the gate oxide, second silicon nitride layer on polysilicon layer and the first silicon nitride layer side wall forms grid；
It is injected by autoregistration, forms body area and the source region of the plane VDMOS device；
By etching, removal is located at the body area and source region in preset second area, retains and is located under the grid
The body area of side and source region, and the depth etched is greater than the depth in the body area；
Form the buffer area being located at below the body area edge；
In entire device surface dielectric layer deposited, the dielectric layer in preset third region is removed, retains enclosure
Divide the dielectric layer of the buffer area；
Deposited metal, and the photoetching and etching of the metal layer are completed, form source metal.
Plane VDMOS device production method provided by the invention, by sequentially form on the surface of a substrate gate oxide,
Polysilicon layer and the first silicon nitride layer, and by the gate oxide, polysilicon layer and the first nitrogen other than preset first area
SiClx layer removes to form grid；Body area and source region are formed in such a way that autoregistration is injected；And by the method for etching described
The lower section of body area edge forms buffer area, completes the plane eventually by dielectric layer deposited, etching, the mode of deposited metal
The production of type VDMOS device, manufacture craft is simpler, and cost is relatively low.Also, by introducing buffer area below body area, guarantee
The conducting resistance of device is also reduced while the resistance to pressure of device, reduces the power consumption of device.
Detailed description of the invention
Fig. 1 is the flow diagram for the plane VDMOS device production method that the embodiment of the present invention one provides；
Fig. 2 is the structural schematic diagram for the substrate that the embodiment of the present invention one provides；
Fig. 3 is that the embodiment of the present invention one removes gate oxide, polysilicon layer and the first nitrogen other than preset first area
Structural schematic diagram after SiClx layer；
Fig. 4 is that the embodiment of the present invention one forms the structural schematic diagram after the second silicon nitride layer；
Fig. 5 is that the embodiment of the present invention one forms the structural schematic diagram after grid；
Fig. 6 is that the embodiment of the present invention one forms the structural schematic diagram after body area and source region；
Fig. 7 is that the embodiment of the present invention one forms the structural schematic diagram behind buffer area；
Fig. 8 is the structural schematic diagram after one dielectric layer deposited of the embodiment of the present invention；
Fig. 9 is that the embodiment of the present invention one etches the structural schematic diagram after dielectric layer；
Figure 10 is the flow diagram of plane VDMOS device production method provided by Embodiment 2 of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Following embodiment will be illustrated for the active area production method of plane VDMOS device.
Fig. 1 is the flow diagram for the plane VDMOS device production method that the embodiment of the present invention one provides, such as Fig. 1 institute
Show, plane VDMOS device production method described in the present embodiment the following steps are included:
As shown in Fig. 2, substrate provided in this embodiment is from bottom to top successively including N-type substrate 1 and N-type epitaxy layer 2, it is described
Gate oxide 3, polysilicon layer 4 and the first silicon nitride layer 5 are sequentially formed on the surface of N-type epitaxy layer 2.
The gate oxide other than step 102, the preset first area of removal, polysilicon layer and the first silicon nitride layer,
To retain the gate oxide being located in the first area, polysilicon layer and the first silicon nitride layer.
Specifically, a first area 6 is preset on the surface of first silicon nitride layer 5, in the first area 6
On first silicon nitride layer 5 on form photoresist, under the masking of the photoresist, to be located at the first area 6 with
The outer gate oxide 3, polysilicon layer 4 and the first silicon nitride layer 5 perform etching, and are exposing the substrate N-type epitaxy layer 2
Stop etching behind surface, removes the photoresist, the structure after over etching is as shown in Figure 3.
Specifically, as shown in figure 4, on the surface of entire device generate one layer of second silicon nitride layer 7, then pass through nitridation
Silicon, which returns, to be carved and will be located on 2 surface of N-type epitaxy layer, and 5 surface of the first silicon nitride layer on the first area 6
On second silicon nitride layer 7 etch away, only retain be located at the gate oxide 3, polysilicon layer 4 and the first silicon nitride layer 5
Second silicon nitride layer 7 on side wall, is formed by figure for step 102 and protects to form grid.After forming grid
Structure it is as shown in Figure 5.
Specifically, as shown in fig. 6, carry out the injection of autoregistration p type impurity to the region in the body area to be formed, and complete to drive
Enter to be formed the first p-type implanted layer, to form the body area 21；Autoregistration N+ type impurity is carried out to the region of the source region to be formed
Injection, and complete to drive in form the first N+ type implanted layer, to form the source region 22, the body area 21 surrounds the source region 22.
Specifically, as shown in fig. 6, under the masking of the first silicon nitride layer 5 and the second silicon nitride layer 7, to preset second
8 area Nei Ti 21 of region and source region 22 carry out etching groove, and the body area 21 of 8 lower section of second area and source region 22 are etched
Fall, only retain the body area 21 being located at below the grid and source region 22, and continue to etch to the lower section of the second area 8, directly
Until etch away sections N-type epitaxy layer 2, so that the depth for being formed by groove is greater than the depth in the body area 21, herein
It should be noted that it is described continue to the lower section of the second area 8 etch depth be those skilled in the art as desired from
Row setting, it is not specific herein to limit.
The etching depth of groove described herein is greater than the depth in the body area, provides space guarantor for the introducing of buffer layer
Barrier.
Specifically, as shown in fig. 7, by way of inclination injection, to by step 105, treated that device does p-type is miscellaneous
The inclination injection of matter forms the buffer area 23 being located at below 21 edge of body area and in 2 surface of substrate N-type epitaxy layer, right
The surface of the substrate N-type epitaxy layer 2 performs etching, and removes the buffer area 23 outside the body area 21, until dew
Out until 2 surface of substrate N-type epitaxy layer, only retain the buffer area 23 being located at below 21 edge of body area, finally
The buffer area 23 formed is column structure.
In the prior art, the pressure-resistant performance of plane VDMOS device is realized mainly by the extension area PXing Ti depletion layer,
Epilayer resistance rate cannot be made low while guaranteeing device resistance to pressure, and device on-resistance is higher, and device power consumption is larger,
And the present embodiment is below body area edge by introducing buffer layer, when device is reverse-biased, entire buffer layer all exhaust play it is resistance to
The effect of pressure, therefore, epilayer resistance rate can be made high, and the conducting resistance of device is lower, and then can reduce device
Power consumption.
Specifically, as shown in figure 8, first in the surface deposition dielectric layer 9 of entire device, until the dielectric layer 9 is by ditch
Until slot fills up, wherein the dielectric layer 9 can be oxide.After generating dielectric layer 9, pass through the method for wet etching, removal
The certain media layer 9 in dielectric layer 9 and the groove on first silicon nitride layer, 5 surface, wherein in the groove
The height of the dielectric layer 9 of remainder is less than the height of the buffer layer 23, and the dielectric layer 9 of the remainder surrounds part institute
State buffer area 23.The structure formed after etch media layer 9 is as shown in Figure 9.
The forming method of source metal is same as the prior art, repeats no more herein.
Plane VDMOS device production method provided in this embodiment, by sequentially forming gate oxidation on the surface of a substrate
Layer, polysilicon layer and the first silicon nitride layer, and by the gate oxide, the polysilicon layer and first other than preset first area
Silicon nitride layer removes to form grid；Body area and source region are formed in such a way that autoregistration is injected；And by the method for etching in institute
The lower section for stating body area edge forms buffer area, completes eventually by dielectric layer deposited, etching, the mode of deposited metal described flat
The production of face type VDMOS device, manufacture craft is simpler, and cost is relatively low.Also, it by introducing buffer area below body area, protects
The conducting resistance of device is also reduced while having demonstrate,proved the resistance to pressure of device, reduces the power consumption of device.
Figure 10 is the flow diagram of plane VDMOS device production method provided by Embodiment 2 of the present invention, such as Figure 10
Shown, the present embodiment further includes step 100 before above-mentioned steps 101.
Specifically, on the surface of the N-type epitaxy layer 2, gate oxide 3, more is sequentially generated by sequence from the bottom to top
Crystal silicon layer 4 and the first silicon nitride layer 5.Wherein, generating mode can be using generation methods such as deposits, herein without specifically limiting
It is fixed.
The present embodiment on the surface of N-type epitaxy layer 2 by sequentially forming the gate oxide 3,4 He of polysilicon layer first
First silicon nitride layer 5 provides structure basis for the subsequent production method of the present embodiment.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (6)
1. a kind of plane VDMOS device production method characterized by comprising
Substrate is provided, is sequentially formed with gate oxide, polysilicon layer and the first silicon nitride layer on the substrate surface；
The gate oxide other than preset first area, polysilicon layer and the first silicon nitride layer are removed, is located at institute to retain
State the gate oxide in first area, polysilicon layer and the first silicon nitride layer；
The second silicon nitride layer is formed on the surface of entire device, second silicon nitride layer in predeterminable area is removed, only retains
Positioned at the gate oxide, second silicon nitride layer on polysilicon layer and the first silicon nitride layer side wall forms grid；
It is injected by autoregistration, forms body area and the source region of the plane VDMOS device；
By etching, removal is located at the body area and source region in preset second area, only retains and is located at below the grid
The body area and source region, and etch depth be greater than the body area depth；
Form the buffer area being located at below the body area edge；
In entire device surface dielectric layer deposited, the dielectric layer in preset third region is removed, retains and surrounds part institute
State the dielectric layer of buffer area；
Deposited metal, and the photoetching and etching of the metal layer are completed, form source metal；
It is wherein, described to form the buffer area being located at below the body area edge, comprising:
It is injected by inclination, forms the buffer area being located at below the body area edge and in the substrate surface；
It is performed etching by the surface to the substrate, removes the buffer area outside the body area, only retained and be located at
The buffer area below the body area edge.
2. plane VDMOS device production method according to claim 1, which is characterized in that the removal preset the
The gate oxide other than one region, polysilicon layer and the first silicon nitride layer, comprising:
Photoresist is formed on first silicon nitride layer on the first area；
Under the masking of photoresist, to the gate oxide being located at other than the first area, polysilicon layer and the first nitridation
Silicon layer performs etching, to expose the surface of the substrate；
Remove the photoresist.
3. plane VDMOS device production method according to claim 1, which is characterized in that described to be infused by autoregistration
Enter, form body area and the source region of the plane VDMOS device, comprising:
The injection of autoregistration p type impurity is carried out to the region in the body area to be formed, and completes to drive in form the first p-type implanted layer,
To form the body area；
The injection of autoregistration N+ type impurity is carried out to the region of the source region to be formed, and completes to drive in and to form the injection of the first N+ type
Layer, to form the source region, the body area surrounds the source region.
4. plane VDMOS device production method according to claim 1, which is characterized in that the removal preset the
The dielectric layer in three regions, comprising:
Using wet etching, the dielectric layer in the third region is removed.
5. plane VDMOS device production method described in any one of -4 according to claim 1, which is characterized in that described to mention
Before substrate, further includes:
The gate oxide, polysilicon layer and the first silicon nitride layer are sequentially formed on the surface of N-type epitaxy layer.
6. plane VDMOS device production method described in any one of -4 according to claim 1, which is characterized in that described to go
Except second silicon nitride layer in predeterminable area, comprising:
It is carved by returning, removes second silicon nitride layer in predeterminable area.
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| CN201510184574.3A CN106158961B (en) | 2015-04-17 | 2015-04-17 | Plane VDMOS device production method |
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| CN113643969B (en) * | 2021-07-27 | 2024-01-19 | 上海华力集成电路制造有限公司 | Method for improving corrosion of high-K dielectric gate by optimizing polysilicon etching |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
| CN103413763A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Super junction transistor and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19922187C2 (en) * | 1999-05-12 | 2001-04-26 | Siemens Ag | Low-resistance VDMOS semiconductor component and method for its production |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5268586A (en) * | 1992-02-25 | 1993-12-07 | North American Philips Corporation | Vertical power MOS device with increased ruggedness and method of fabrication |
| CN103413763A (en) * | 2013-08-22 | 2013-11-27 | 上海宏力半导体制造有限公司 | Super junction transistor and forming method thereof |
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Effective date of registration: 20220719 Address after: 518116 founder Microelectronics Industrial Park, No. 5, Baolong seventh Road, Baolong Industrial City, Longgang District, Shenzhen, Guangdong Province Patentee after: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. Address before: 100871, Beijing, Haidian District, Cheng Fu Road, No. 298, Zhongguancun Fangzheng building, 9 floor Patentee before: PEKING UNIVERSITY FOUNDER GROUP Co.,Ltd. Patentee before: SHENZHEN FOUNDER MICROELECTRONICS Co.,Ltd. |