JP2005259779A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably manufacture a thin IGBT having good electrical characteristics. <P>SOLUTION: The IGBT has a p<SP>+</SP>-type high-concentration drain layer 12 which decides the injection volume of a hole and a p<SP>-</SP>-type low-concentration drain layer 11 which absorbs the fluctuation of the ground amount of the rear surface of a wafer under an n<SP>+</SP>-type buffer layer 13. Since ohmic junction is formed by means of a drain electrode 31 containing aluminum with the p<SP>-</SP>-type drain layer 11 after the rear surface of the wafer is ground, ion implantation and heat treatment performed for separately forming a high-concentration layer for drain contact become unnecessary. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention particularly relates to an insulated gate bipolar transistor (IGBT) and a method for manufacturing the same.

  In recent years, the trade-off relationship between on-state voltage and turn-off time has been improved by adopting a thin-type low-injection-efficiency anode (drain) structure adopted in non-punch-through IGBTs in punch-through IGBTs. It is becoming known that This is because the speed of the IGBT can be increased without performing lifetime control.

  However, in this structure, for example, in the case of an element having a withstand voltage of 600 V, the total thickness of the IGBT is as extremely thin as about 60 μm, so that a MOS gate structure or the like cannot be formed in a normal semiconductor manufacturing apparatus. In addition, a 1200 V element has a very thin structure as compared with the conventional structure, and the same problem occurs. Therefore, various methods have been proposed in which a thick structure is processed to reduce the thickness after forming a MOS gate structure or the like.

One is to use a thick epitaxial wafer consisting of a conventional n ⁻ drift layer, n ⁺ buffer layer, and p ⁺ drain substrate, form a MOS gate structure, etc., and then grind the back surface of the p ⁺ drain substrate. Forming a thin p ⁺ drain layer.

In this case, the final thickness of the p ⁺ drain layer greatly changes due to variations in the amount of back grinding. Then, since the thickness of the region with the highest impurity concentration in the drain layer changes, the hole injection amount also changes greatly. As a result, there arises a problem that even if the variation in the amount of grinding on the back surface is ± 3 μm, the electrical characteristics of the obtained device deviate from the target value.

  On the other hand, FIG. 12 shows another structure according to the prior art provided with a low-concentration layer that absorbs variations in the grinding amount of the back surface of the wafer (see Patent Document 1 as an example of this type of semiconductor device). reference).

In the structure of FIG. 12, a MOS gate structure or the like is formed before the low concentration layer 18 is ground, and then the low concentration layer 18 is ground to a predetermined thickness. Then, a p ⁺ drain layer 17 is formed on the ground surface by ion implantation and heat treatment. As a result, a device with a small change in the amount of injected holes can be obtained even when the back grinding amount varies.

However, in this case, the p ⁺ drain layer 17 is formed by ion-implanting impurities and activating the ions by heat treatment (annealing) that does not affect the device structure on the element surface side. At this time, the activation rate of the implanted impurity ions varies greatly depending on the temperature and time during annealing. Therefore, there is a problem that it is difficult to make the characteristics of the p ⁺ drain layer 17 constant.

On the other hand, FIG. 13 shows still another structure according to the prior art provided with p ⁺ layers on both sides of the low concentration layer (see Patent Document 2 as an example of this type of semiconductor device).

In the structure of FIG. 13, a p ⁺ drain layer 17 that determines the amount of holes injected is first formed on the n ⁺ buffer layer 13 side above the low concentration layer 18 by ion implantation and heat treatment. At this time, since the MOS gate structure or the like has not yet been formed, a sufficient heat treatment can be performed, and the ion activation rate is almost 100%.

Subsequently, a MOS gate structure or the like is formed, and then the low concentration layer 18 is ground until a predetermined thickness is reached. Then, a p ⁺ contact layer 19 is formed on the ground surface by ion implantation and heat treatment. This p ⁺ contact layer 19 only needs to function for making ohmic contact with the drain electrode 30. As a result, even if the characteristics of the p ⁺ contact layer 19 vary, a device with little change in the amount of injected holes can be obtained.

However, in this case, as in the structure shown in FIG. 12, the ion implantation and heat treatment must be performed after the wafer is thinned.
JP 2003-69020 A (page 5, FIG. 1) JP 2002-305305 A (page 9, FIG. 11 to FIG. 13)

  As described above, the conventional structure for absorbing the variation in the amount of wafer grinding in the IGBT requires ion implantation and heat treatment after the wafer is thinned, and requires a special manufacturing apparatus corresponding to the thin wafer, There was a problem that cracking and chipping were likely to occur.

  An object of the present invention is to provide a structure and a manufacturing method capable of stably manufacturing a thin-structure IGBT having good electrical characteristics.

  In order to achieve the above object, a semiconductor device of the present invention has a first conductivity type low concentration drain layer having a relatively low impurity concentration and a relatively low impurity concentration formed on the upper surface of the low concentration drain layer. A high first conductivity type high concentration drain layer; a second conductivity type buffer layer formed on the upper surface of the high concentration drain layer; a second conductivity type drift layer formed on the upper surface of the buffer layer; A MOS gate structure including a base region, a source region, and a gate electrode formed in a surface region of the drift layer; and a drain electrode including aluminum formed on a lower surface of the low-concentration drain layer.

  Therefore, it is not necessary to perform ion implantation and a heat treatment (annealing) accompanying it after the wafer is thinned.

  According to the present invention, there is no need for a special ion implantation apparatus capable of handling a thin wafer. Further, there is no opportunity for cracking or chipping of the wafer during the annealing process. Therefore, it is possible to stably manufacture an IGBT having good electrical characteristics.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an IGBT according to the first embodiment of the present invention. A p base region 15, an n ⁺ source region 16, a gate insulating film 21, an interlayer insulating film 22, a gate electrode 32 and a source electrode 33 are formed in the surface region of the n ⁻ drift layer 14. On the other hand, an n ⁺ buffer layer 13, a p ⁺ high concentration drain layer 12, a p ⁻ low concentration drain layer 11, and a drain electrode 31 are formed under the n ⁻ drift layer 14.

2 to 4 show a method of manufacturing the IGBT shown in FIG. First, as shown in FIG. 2, a low concentration p-type substrate 10 is prepared, and a p ⁺ high concentration drain layer 12 is formed by ion implantation and heat treatment. In this case, the p ⁺ high-concentration drain layer 12 can be formed by epitaxial growth or the like, but it is desirable to use an ion implantation method in order to form a high-concentration and thin layer with high accuracy.

Next, as shown in FIG. 3, an n ⁺ buffer layer 13 is formed on the p ⁺ high concentration drain layer 12 by epitaxial growth. In this case, it is also possible to form the n ⁺ buffer layer 13 by ion implantation and heat treatment. Further, an n ⁻ drift layer 14 is formed on the n ⁺ buffer layer 13 by epitaxial growth. At this time, the n ⁺ buffer layer 13 is controlled to have a thickness of, for example, 10 μm, and the n ⁻ drift layer 14 is controlled to have a thickness of, for example, 50 μm.

Next, as shown in FIG. 4, a MOS gate structure or the like is formed on the surface region of the n ⁻ drift layer 14 by a known process. Thereafter, the back surface of the p ⁻ low concentration substrate 10 is subjected to grinding, etching, or the like to form the p ⁻ low concentration drain layer 11 having a predetermined thickness.

At this time, the predetermined thickness is determined from the amount of variation in grinding or etching of the back surface of the substrate. For example, when the variation amount is ± 3 μm, the predetermined thickness is about 3 μm. Finally, a drain electrode 31 containing aluminum is formed on the p ⁻ low-concentration drain layer 11 to complete the IGBT.

According to the IGBT having the above configuration, even if the substrate back surface grinding amount varies, the thickness of the p ⁺ high concentration drain layer 12 does not change, and only the thickness of the p ⁻ low concentration drain layer 11 varies. Therefore, variation in the amount of injected holes is small. Further, there is no step of ion implantation after the entire wafer is thinned, and the manufacturing process becomes extremely easy.

FIG. 5 schematically shows the relationship between the film thickness and impurity concentration of each layer of the completed IGBT. In FIG. 5, for example, the p ⁻ low concentration drain layer 11 having a thickness of 3 μm exists, but due to variations in grinding and etching of the back surface of the substrate, the p ⁻ low concentration drain layer 11 hardly remains as shown in FIG. 6. There is a case. However, even in this case, since the thickness of the p ⁺ high-concentration drain layer 12 hardly changes, the change in the amount of injected holes is slight, and an IGBT having desired characteristics can be obtained.

Here, the IGBT having the above configuration can be implemented because the drain electrode 31 containing aluminum forms an ohmic junction with the p ⁻ low-concentration drain layer 11 without forming a Schottky junction.

For example, in aluminum, as disclosed in Non-Patent Document 1, for example, it is known that an ohmic junction is formed even on p-type silicon of 1.5 × 10 ¹⁶ cm ⁻³ on the low impurity concentration side. Yes. Therefore, from the viewpoint of ohmic contact, the impurity concentration of the p ⁻ low-concentration drain layer 11 is desirably 1.5 × 10 ¹⁶ cm ⁻³ or more.
Corona, Power Devices and Power IC Handbook, 24 pages, Table 2.1

On the other hand, the impurity concentration of the p ⁻ low concentration drain layer 11 is preferably low in order to prevent the hole injection amount from changing greatly even if the substrate back surface grinding amount varies, and p ⁺ high concentration. It is desirable to set it to 1/10 or less of the impurity concentration of the drain layer 12. According to the present invention, the impurity concentration of the p ⁺ high-concentration drain layer 12 can be increased to 3 × 10 ¹⁸ cm ⁻³ or more, which is the same as that of the high-concentration substrate used in the conventional structure. . Therefore, the impurity concentration of the p ⁻ low concentration drain layer 11 is desirably 3 × 10 ¹⁷ cm ⁻³ or less.

Furthermore, since the drain electrode 31 is usually formed with a multilayer structure of different metals, it is necessary that the metal layer in direct contact with the p ⁻ low-concentration drain layer 11 contains aluminum. In this case, pure aluminum or aluminum silicon alloy is desirable.

Next, a second embodiment of the present invention will be described. 7 and 8 show a method of manufacturing a semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 7, a substrate 9 is prepared, and a p ⁻ low concentration drain layer 11 is formed by epitaxial growth. In this case, the p ⁻ low concentration drain layer 11 can be formed by diffusion or the like, but in order to form the p ⁻ low concentration drain layer 11 having a constant concentration, it is desirable to use an epitaxial growth method.

Next, as shown in FIG. 8, a p ⁺ high concentration drain layer 12 is formed on the p ⁻ low concentration drain layer 11 by ion implantation and heat treatment. Thereafter, the IGBT is completed through the same processes as those in FIGS. 3 and 4 of the first embodiment. At this time, in the first embodiment, p-type substrate 10 at low concentrations is processed so as to leave only a predetermined thickness p ^- although low concentration drain layer 11 is formed, in this second embodiment, The substrate 9 is completely removed, and the exposed p ⁻ low-concentration drain layer 11 is processed to have a predetermined thickness.

  In the second embodiment, it is not necessary to specify the conductivity type and impurity concentration of the substrate 9 as compared to the first embodiment. Therefore, there is an advantage that a cheap substrate can be used.

Furthermore, a third embodiment of the present invention will be described. 9 to 11 show a method of manufacturing a semiconductor device according to the third embodiment of the present invention. First, as shown in FIG. 9, a low concentration n-type substrate 8 is prepared, and an n ⁺ buffer layer 13 is formed by epitaxial growth. Here, since the n ⁻ substrate 8 finally becomes the n ⁻ drift layer of the IGBT, it is necessary that the n ⁻ substrate 8 has a thickness and an impurity concentration corresponding to the breakdown voltage required for the IGBT.

Next, as shown in FIG. 10, the p ⁺ high concentration drain layer 12 is formed by epitaxial growth on the n ⁺ buffer layer 13, and the p ⁻ low concentration drain layer 11 is further formed by epitaxial growth thereon. .

Subsequently, as shown in FIG. 11, a MOS gate structure or the like is formed on the opposite surface of the n ⁻ substrate 8 by a known process. Thereafter, the p ⁻ low concentration drain layer 11 is ground or etched to form the p ⁻ low concentration drain layer 11 having a predetermined thickness. Finally, a drain electrode 31 containing aluminum is formed on the p ⁻ low-concentration drain layer 11 to complete the IGBT.

Example 3 is characterized in that the n ⁻ drift layer is formed of the n ⁻ substrate 8. When the breakdown voltage class of the IGBT is increased, it is necessary to increase the thickness of the n ⁻ drift layer. At this time, if the n ⁻ drift layer is formed by epitaxial growth, the cost increases as the thickness increases. Therefore, the third embodiment has an advantage that the cost is reduced in the case of an IGBT having a high breakdown voltage class.

  The planar gate type IGBT has been described above as an example. However, the present invention is not limited to the above-described embodiment, and it is apparent that the same effect can be obtained with a trench gate type IGBT.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step that follows FIG. 2. FIG. 4 is a cross-sectional view showing a manufacturing process subsequent to FIG. 3. FIG. 2 is a diagram schematically showing the relationship between the film thickness of each layer of the semiconductor device shown in FIG. 1 and the impurity concentration. FIG. 6 is another diagram schematically showing the relationship between the film thickness of each layer of the semiconductor device shown in FIG. 1 and the impurity concentration. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Example of this invention. FIG. 8 is a cross-sectional view showing a manufacturing step that follows FIG. 7. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Example of this invention. FIG. 10 is a cross-sectional view showing a manufacturing step that follows FIG. 9. It is sectional drawing which shows the manufacturing process following FIG. It is sectional drawing which shows the structure of the conventional semiconductor device. It is principal part sectional drawing which shows the other structure of the conventional semiconductor device.

Explanation of symbols

8 n ⁻ substrate 9 substrate 10 p ⁻ low concentration substrate 11 p ⁻ low concentration drain layer 12 p ⁺ high concentration drain layer 13 n ⁺ buffer layer 14 n ⁻ drift layer 15 p base region 16 n ⁺ source region 17 p ⁺ drain layer 18 Low-concentration layer 19 p ⁺ Contact layer 21 Gate insulating film 22 Interlayer insulating film 30 Drain electrode 31 Drain electrode 32 Gate electrode 33 Source electrode

Claims (7)

A low-concentration drain layer of a first conductivity type having a relatively low impurity concentration;
A first conductivity type high concentration drain layer having a relatively high impurity concentration formed on the upper surface of the low concentration drain layer;
A second conductivity type buffer layer formed on the upper surface of the high-concentration drain layer;
A second conductivity type drift layer formed on the upper surface of the buffer layer;
A MOS gate structure including a base region, a source region, and a gate electrode formed in a surface region of the drift layer;
And a drain electrode containing aluminum formed on a lower surface of the low-concentration drain layer. 2. The semiconductor device according to claim 1, wherein an impurity concentration of the low-concentration drain layer is 1.5 × 10 ¹⁶ cm ⁻³ or more and 3 × 10 ¹⁷ cm ⁻³ or less. Forming a first conductivity type high-concentration drain layer having a relatively high impurity concentration on a first surface of a first conductivity type substrate having a relatively low impurity concentration;
Forming a second conductivity type buffer layer on the high-concentration drain layer;
Forming a second conductivity type drift layer on the buffer layer by epitaxial growth;
Forming a MOS gate structure including a base region, a source region, and a gate electrode in a surface region of the drift layer;
Removing a second surface of the substrate opposite the first surface until the substrate has a predetermined thickness;
And a step of forming a drain electrode containing aluminum on the exposed surface of the substrate. Forming a first conductivity type low concentration drain layer having a relatively low impurity concentration on a first surface of a first substrate;
Forming a first conductivity type high concentration drain layer having a relatively high impurity concentration on the low concentration drain layer;
Forming a second conductivity type buffer layer on the high-concentration drain layer;
Forming a second conductivity type drift layer on the buffer layer by epitaxial growth;
Forming a MOS gate structure including a base region, a source region, and a gate electrode in a surface region of the drift layer;
Removing a second surface opposite to the first surface of the first substrate until the lightly doped drain layer is exposed;
Removing the exposed surface of the low-concentration drain layer until the low-concentration drain layer has a predetermined thickness;
Forming a drain electrode containing aluminum on a final exposed surface of the low-concentration drain layer. Forming a second conductivity type buffer layer on the first surface of the second conductivity type substrate;
Forming a first conductivity type high concentration drain layer having a relatively high impurity concentration on the buffer layer;
Forming a low-concentration drain layer of a first conductivity type having a relatively low impurity concentration on the high-concentration drain layer by epitaxial growth;
Forming a MOS gate structure including a base region, a source region, and a gate electrode on a second surface opposite to the first surface of the substrate;
Removing the low-concentration drain layer until the low-concentration drain layer has a predetermined thickness;
Forming a drain electrode containing aluminum on the exposed surface of the low-concentration drain layer.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the high concentration drain layer is formed by ion implantation and heat treatment. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the low-concentration drain layer is formed by epitaxial growth.