KR20070002515A - Fin transistor and method for fabricating the same - Google Patents

Abstract

A method for manufacturing a fin transistor is provided to prevent degradation of transistors and to restrain a parasitic transistor by implanting halogen ions into an active region. An active region(111a) is protruded from a desired portion of a substrate(111). A channel region is formed in the active region. A field oxide layer(114) is formed in the substrate to have a relatively low surface compared to the active region. A gate electrode crosses the upper surface of the active region to overlap with the channel region. A gate oxide layer(117) is formed between the gate electrode and the active region. At this time, halogen ions are implanted to improve the growing speed of the gate oxide layer, so that the thickness of the gate oxide layer on the upper surface of the active region is thicker than that of the sidewalls of the active region.

Description

Projection transistor and its manufacturing method {FIN TRANSISTOR AND METHOD FOR FABRICATING THE SAME}

1 is a perspective view showing a conventional protrusion transistor structure,

2 is a cross-sectional view taken along the line A-B of FIG.

3 is a perspective view showing the structure of the protruding transistor proposed in the present invention;

4 is a cross-sectional view taken along the line A-B of FIG.

5 through 10 are process flowcharts illustrating the method of manufacturing the protruding transistor of FIG. 4.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a projection transistor having a triple channel and a method of manufacturing the same.

As the degree of integration of semiconductor devices increases, the channel length and width of corresponding cell transistors also become very short. Also, with the short channel structure, the threshold voltage is no longer independent of the channel width. Therefore, in implementing the threshold voltage target of the cell transistor required by a specific device, it is a general opinion that the limit has been reached with a conventional two-dimensional plannar structure.

In order to overcome this problem, researches on three-dimensional transistors have been actively conducted in a logic device. In particular, the protruding transistors forming the triple channel have attracted the most attention as next generation nano scale (NANO SCALE) transistors.

1 is a perspective view illustrating a conventional protrusion transistor structure, and FIG. 2 is a cross-sectional view taken along line A-B of FIG. 1. In the figure, reference numeral 11 denotes a semiconductor substrate, reference numeral 12 denotes a field oxide film, reference numeral 13 denotes a gate oxide film, and reference numeral 14 denotes a gate electrode of a conductive film material. Reference numerals S and D denote source and drain regions, and reference numerals C1, C2, and C3 denote channel regions, respectively.

A characteristic of this structure is that the semiconductor substrate (indicated by the active region indicated by reference numeral 11a) of the portion where the channel is to be formed is vertically protruded, and the gate oxide film 13 and the gate electrode 14 are formed thereon, whereby the gate electrode ( The transistor is designed so that all three surfaces (parts indicated by reference numerals C1, C2, C3 in FIG. 2C) of the substrate 11 surrounded by 14 can be used as a channel.

In this case, the transistor is designed to have three sides as a channel, and thus has excellent ON-OFF characteristics, high current drivability, and back bias dependency of a threshold voltage. This reduction allows for desired device characteristics even at low voltages.

However, this structure has a large difference between the inversion voltages of the sidewall channels C2 and C3 and the inversion voltage at the corners of the upper channel C1, so that deterioration of the characteristics of the transistor is inevitable. That is, parasitic transistors are turned on at or below a desired threshold voltage near the top of the gate electrode. When the parasitic transistor is formed, the threshold voltage is lowered when driving the device, and the cut-off characteristic of the transistor is reduced. Increasing the ion implantation concentration of the channel to eliminate parasitic transistors increases the leakage current, resulting in a drop in the refresh characteristics of the device, which is currently difficult to apply.

The technical problem to be achieved by the present invention is to improve the gate oxide film growth rate of the gate electrode top by ion implantation of a halogen element that selectively improves the oxide film growth rate only in the portion where the upper channel is formed in the active region. The present invention provides a projection transistor that can suppress parasitic transistor generation in the vicinity and prevent deterioration of transistor characteristics.

Another object of the present invention is to provide a manufacturing method capable of effectively manufacturing the projection transistor of the above structure.

In order to achieve the above technical problem, the present invention provides a projection transistor. This transistor has an active region protruding from a predetermined region of the substrate, and a channel region is formed in the active region. A field oxide film is formed on the substrate around the active region to have a lower surface than the upper surface of the active region. The gate electrode crosses the upper surface of the active region so as to overlap the channel region. A gate oxide film is interposed between the gate electrode and the active region. In this case, the gate oxide layer on the upper surface of the active region is formed to have a thickness thicker than the gate oxide layer on the sidewalls of the active region.

In order to achieve the above technical problem, the present invention provides a method of manufacturing a projection transistor. In this method, a semiconductor substrate is etched to form an active region protruding from a predetermined region of the substrate, and a field oxide film defining the active region is formed at its periphery. Only the portion where the upper channel is formed in the active region is selectively implanted with ions to improve the oxide film growth rate, and the field oxide layer is recess-etched to have a surface lower than the upper surface of the active region. A gate oxide film is formed along the surface exposed portion of the active region. At this time, the gate oxide film is formed thicker on the upper surface of the active region than the sidewalls due to the influence of the ions which improve the oxide film growth rate.

Halogen element is used as an ion which improves the oxide film growth rate, and fluorine, iodine, xenon etc. are mentioned as a typical example. The field oxide film is recess-etched using a polysilicon hard mask as a masking layer, and after the etching process, the post-etching process using a remote plasma is preferably performed.

When the transistor is manufactured in the above structure, since the gate oxide layer on the upper surface of the active region is formed thicker than the sidewalls, the electric field near the upper channel can be relaxed. When the electric field is relaxed in this manner, inversion can be prevented from occurring at the corners of the upper channel, thereby suppressing parasitic transistor generation near the gate electrode tower.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a perspective view illustrating the structure of the protruding transistor proposed in the present invention, and FIG. 4 is a cross-sectional view taken along line A-B of FIG.

Referring to the figure, it can be seen that this transistor is constructed as follows. An active region 111a protrudes from a predetermined region of the semiconductor substrate 111, and channel regions C1, C2, and C3 are formed in the active region 111a. The field oxide film 114 is formed on the substrate 111 around the active region 111a to have a lower surface than the upper surface of the active region 111a, and overlaps the channel regions C1, C2, and C3 on the active region 111a. A gate electrode 118 is disposed across the top surface of 111a. A gate oxide film 117 is interposed between the gate electrode 118 and the active region 111a. In this case, the gate oxide film 117 on the top surface of the active region 111a is formed to have a thickness of "h + α", while the gate oxide film 117 of the sidewall of the active region 111a is formed to have a thickness of "h". Source and drain regions S and D are formed in the active region 111a at both sides of the gate electrode 118.

In this way, the thickness of the gate oxide film 117 of the upper surface of the active region 111a is formed relatively thicker than the sidewalls so that the inversion does not occur at the corner of the upper channel C1 so that the gate electrode 118 is close to the top of the gate electrode 118. This is to suppress parasitic transistor generation as much as possible. To mitigate the electric field near the upper channel to prevent reversal in the upper channel corners.

5 to 10 are process flowcharts showing a method of manufacturing the protrusion transistor of the above structure. Looking at this in detail the manufacturing method as follows.

As shown in FIG. 5, the pad oxide film 112 and the pad nitride film 113 are sequentially formed on the semiconductor substrate 111.

As shown in FIG. 6, the pad nitride film 113 and the pad oxide film 112 are sequentially etched with a mask defining a portion where the trench is to be formed, and then the patterned nitride film 113 and the oxide film 112 are used as a mask. 111 is etched to a predetermined depth to form a trench t. As a result, the active region 111a protruding perpendicularly from the substrate 111 is formed.

As shown in FIG. 7, an oxide film is formed on the substrate 111 to sufficiently fill the inside of the trench t, and then subjected to CMP treatment to form a field oxide film 114 in the trench t.

As shown in FIG. 8, a mask pattern (not shown) for blocking a peripheral circuit region is formed on the substrate 111, and a halogen element is ion implanted thereon. As a result, a halogen element is selectively implanted only into the active region 111a under the pad oxide film 112 placed in the cell region. For convenience, the region into which the halogen element is implanted is referred to as an ion implantation region at 115. Applicable halogen elements include fluorine, iodine, xenon, and the like, and ion implantation of halogen elements is performed so that the ion implantation region 115 is formed near the surface side of the active region 111a under the pad oxide film 112. It is desirable to adjust the depth Rp.

As shown in FIG. 9, the mask pattern of the peripheral circuit region is removed, and the field oxide film 114 is etched by a predetermined thickness by plasma dry etching to form an active region 111a including the pad nitride film 113 and the pad oxide film 112. Part of the In this case, the recess etching of the field oxide layer 114 is formed of a polysilicon material on the pad nitride layer 113 to prevent top notching from occurring at the upper edge portion of the active region 111a during the etching process. After the hard mask is additionally formed, the process may be performed by using the mask as a masking layer to perform etching. Subsequently, a post etch treatment (PET) process using a remote plasma is performed to remove plasma etch damage generated in the channel formation region in the exposed active region 111a.

As shown in FIG. 10, after the pad nitride film 113 and the pad oxide film 12 are sequentially removed, a screen oxide film (not shown) is formed and an ion implantation step for adjusting the threshold voltage is performed. Subsequently, the screen oxide film is removed, and the gate oxide film 116 is formed along the surface exposed portion of the active region 111a. At this time, the upper surface of the active region 111a is formed with a relatively thick oxide film compared to the side wall due to the influence of halogen ions to accelerate the oxidation injected into the ion implantation region 115. That is, the gate oxide layer 116 is formed to a thickness of "h + α" in the portion where the upper channel C1 is to be formed in the active region (for example, the upper surface of the active region), while the sidewall channels C2 and C3 are formed. The gate oxide film 116 is formed to be "h" thick in the portion to be formed (eg, sidewall of the active region). Thereafter, as shown in FIGS. 3 and 4, the gate electrode 117 is formed to overlap the upper surface of the active region 111a by overlapping with the channel regions C1, C2, and C3, and the gate is implanted by an ion implantation process. Source and drain regions S and D are formed in the active region 111a on both sides of the electrode 117.

As such, by implanting a halogen element that selectively accelerates oxidation to only the portion where the upper channel C1 is to be formed in the active region 111a, the gate oxide film 116 is formed to be relatively thicker than the sidewall. In addition, since the electric field near the upper channel C1 can be relaxed compared to the existing one, it is possible to prevent the inversion from occurring at the corner portion of the upper channel C1. As a result, parasitic transistors turned on at or below a desired threshold voltage near the top of the gate electrode 117 can be suppressed as much as possible.

Therefore, by applying the present technology it is possible to prevent the deterioration of the transistor characteristics while maintaining the advantages of the conventional projection transistor.

Although preferred embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments and can be variously modified and implemented by those skilled in the art without departing from the technical scope of the present invention. Of course.

As described above, according to the present invention, by injecting halogen ions to accelerate oxidation in the portion where the upper channel is to be formed in the active region, the thickness of the gate oxide film on the upper surface of the active region is formed to be relatively thicker than the sidewalls, thereby increasing the vicinity of the upper channel. By reducing the electric field of the transistor, it is possible to prevent reversal in the corner of the upper channel, so that parasitic transistor generation in the vicinity of the gate electrode tower can be suppressed as much as possible, and deterioration of the characteristics of the transistor can be prevented.

Claims (6)

An active region protruding from a predetermined region of the semiconductor substrate; A channel region formed in the active region; A field oxide film formed on the substrate to have a surface lower than an upper surface of the active region; A gate electrode overlapping the channel region and crossing the upper surface of the active region; And And a gate oxide layer interposed between the gate electrode and the active region. And the gate oxide layer on the upper surface of the active region is thicker than the gate oxide layer on the sidewall of the active region. Etching the semiconductor substrate to form an active region protruding from a predetermined region of the substrate; Forming a field oxide film on the substrate to define the active region; Implanting ions which selectively increase the oxide film growth rate only in the portion where the upper channel is to be formed in the active region; Recess etching the field oxide layer so that the field oxide layer has a lower surface than an upper surface of the active region; And And forming a gate oxide film along a surface exposed portion of the active region. The method of claim 2, A process for producing a projection transistor, characterized in that a halogen element is used as the ion for improving the oxide film growth rate. The method of claim 3, wherein Fluorine, iodine, xenon or the like is used as the halogen element. The method of claim 2, The field oxide film is a recessed transistor manufacturing method, characterized in that for etching the recess using a hard mask made of polysilicon as a masking layer. The method of claim 5, After the recess etching of the field oxide film, a post-etch treatment (PET) using a remote plasma is further performed.

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