KR100743637B1 - Method of manufacturing mosfet device - Google Patents

Abstract

A method for fabricating a MOSFET is provided to form a transistor having a uniform threshold voltage even if a gate and a groove are misaligned, by forming a groove having a greater width than that of the gate and a groove having a smaller width than that of the gate. A first mask pattern is formed on a semiconductor substrate(10), exposing a gate formation region. The exposed substrate is etched to form a first groove(50) by using the first mask pattern as an etch mask. Spacers are formed on both sidewalls of the first groove including the first mask pattern. A part of the substrate under the bottom of the first groove is etched to form a second groove(70) having a smaller width than that of the first groove by using the first mask pattern including the spacers as an etch mask. A first ion implantation process for controlling a threshold voltage is performed on the surface of the substrate under the second groove. The spacer and the first mask pattern are removed. A gate(110) having a smaller width than that of the first groove is formed on the resultant structure. An oxide layer is formed on the surface of the substrate including both the sidewalls of the first groove and on both sidewalls of the gate. A source/drain region(S/D) is formed in the surface of the substrate at both sides of the gate including the oxide layer.

Description

Method of manufacturing MOSFET device

1 is a view for explaining a conventional problem.

Figure 2a to 2e is a cross-sectional view for each process for explaining the manufacturing method of the MOSFET device according to the present invention.

3 is a cross-sectional view showing an alignment state between a gate and a groove.

Explanation of symbols on the main parts of the drawings

10,10 ': semiconductor substrate 20,20': isolation layer

30: buffer oxide film 40: first mask pattern

50,50 ': first groove 60: spacer

70,70 ': second groove 80,80': gate insulating film

90,90 ': conductive film 100,100': hardmask film

110,110 ': Gate 120,120': Property canvas

130: gate spacer S / D: source / drain region

The present invention relates to a method for manufacturing a MOSFET device, and more particularly, to a method for manufacturing a MOSFET device capable of improving the threshold voltage characteristics.

Currently, design rules are becoming smaller and more complicated to manufacture highly integrated memory devices. As described above, in order to achieve high integration of the device, the size of the device is being reduced, and the tendency of such reduction is increasing day by day. Such a trend is that the channel lengths of transistors of peripheral circuits as well as cell transistors serving as storage units are decreasing.

In this way, the doping concentration of the substrate is increased due to the reduction in the channel length, which results in an increase in current leakage as the electric field is increased. As a result, it becomes difficult to obtain stable device characteristics.

Meanwhile, the semiconductor substrate is recessed, that is, the substrate is etched to form a groove, and then a gate is formed on the groove as a method for preventing the above problem, that is, a short channel effect. Research on recess gates that form and increase the effective channel length has been actively conducted.

Such a method can reduce the channel doping concentration, thereby increasing the data retention time, thereby improving the device characteristics.

However, as shown in FIG. 1, however, in order to recess the substrate 1 when forming a recess gate 7 for increasing the effective channel length as described above, that is, forming the grooves 3. The exposure equipment used for the mask process for forming and the mask equipment for forming the gate 7 are different. That is, as the integration degree of the device is increased, high resolution equipment is used to form the grooves 3 having a fine width, and the gate 7 is formed on the grooves 3 due to the difference in heterogeneous exposure equipment. It is not formed in an aligned state, but is formed in a misaligned state to the left or right side of the groove 3.

As such, when misalignment occurs between the gate 7 and the groove 3, the gate material of the portion where the misalignment occurs between the gate 7 and the groove 3, that is, the polysilicon film 4 is overetched. ) The excessive etching of the polysilicon film 4 causes a problem that the threshold voltage Vt fluctuates due to the thickness change of the reoxidation film 8 during the gate reoxidation process, thereby deteriorating the refresh characteristics of the device. Let's do it.

In addition, when misalignment occurs between the gate 7 and the groove 3, the source / drain region S / D also has a problem of having an asymmetric profile.

As a result, due to the above-described problems, it is difficult to secure uniformity between the devices in the above-described prior art, and the reliability and yield of the devices are lowered.

In FIG. 1, reference numeral 2 denotes an isolation layer, 5 denotes a metal layer, and 6 denotes a hard mask layer.

Accordingly, an object of the present invention is to provide a method for manufacturing a MOSFET device that can solve the problems caused by misalignment between a gate and a groove.

In order to achieve the above object, the present invention, forming a first mask pattern for exposing the gate formation region on the semiconductor substrate; Etching the exposed portion of the substrate using the first mask pattern as an etching mask to form a first groove; Forming a spacer on both sidewalls of the first groove including the first mask pattern; Etching the substrate portion below the bottom of the first groove by using the first mask pattern including the spacer as an etching mask to form a second groove having a width smaller than that of the first groove; Removing the spacers and the first mask pattern; Forming a gate having a width smaller than the width of the first groove on the front surface of the substrate including the second groove and the first groove; Forming an oxide film on the surface of the substrate and on both side walls of the gate, including both side walls of the first groove; And forming a source / drain region in the surface of the substrate on both sides of the gate including the oxide film.

In this case, the first groove is formed to a depth of 50 ~ 2000Å.

The first groove may be formed to have a width of 1.1 to 1.5 with respect to the width of the gate.

And performing a first threshold voltage control ion implantation into the substrate surface below the second groove after the forming of the second groove and before removing the spacer and the first mask pattern. It features.

The second groove is formed to a depth of 50 ~ 2000Å.

The second groove may be formed to have a width of 0.5 to 0.9 with respect to the width of the gate.

The oxide film may be a reoxidation film formed during a gate reoxidation process to compensate for etch damage generated during gate formation.

After the step of forming oxide films on both side walls of the gate, and before forming the source / drain regions in the substrate surfaces on both sides of the gate including the oxide film, the secondary threshold voltage is adjusted in the substrate surfaces on both sides of the gate including the oxide film. Performing ion implantation; And forming spacers on both sidewalls of the gate including the oxide film.

(Example)

First, the technical principle of the present invention will be described. In the present invention, when the recess gate is formed, the semiconductor substrate is etched to form a first groove having a width larger than the width of the gate, and then under the bottom of the first groove. The substrate portion of the substrate is etched to form a second groove having a width smaller than that of the first groove. Then, a gate is formed on the second groove and the first groove.

In this case, by forming a first groove having a width larger than the width of the gate and a second groove having a width smaller than the width of the gate, even if misalignment occurs between the gate and the groove during formation of the gate, the second groove is formed in a subsequent process. The gate material formed at is not subjected to an attack, thereby preventing an increase in the variation of the threshold voltage Vt.

In addition, due to the formation of the first groove having a width larger than the width of the gate, it is possible to prevent asymmetry between the source and drain regions.

In addition, in the alignment state between the gate and the groove, an oxide film is formed on both sidewalls of the first groove in a subsequent process, thereby lowering an electric field (E-field) between the gate and the junction.

2A to 2E are cross-sectional views illustrating processes for manufacturing a MOSFET device according to the present invention, which will be described below.

Here, in the exemplary embodiment of the present invention, a case in which misalignment between a gate and a groove occurs is illustrated.

Referring to FIG. 2A, a device isolation film 20 defining an active region in the semiconductor substrate 10 is formed by a known shallow trench isolation (STI) process. Then, a buffer oxide film 30 is deposited on the substrate 10 on which the device isolation film 20 is formed. Next, after the first mask pattern 40 is formed on the substrate 10 to expose the gate formation region, the first mask pattern 40 is used as an etching mask to expose the buffer oxide layer 30. A portion of the substrate 10 is etched to form the first groove 50 to have a width of 1.1 to 1.5 with respect to the width of the gate, and to have a depth of 50 to 2000 microns.

Here, the present invention forms a first groove 50 having a width greater than that of the subsequent gate, so that when a misalignment occurs between the subsequent gate and the groove, the profile of the subsequent source / drain region is symmetry. )

In addition, when alignment is performed between the subsequent gate and the groove, an oxide film is formed on both sidewalls of the first groove 50 during the subsequent process, so that an electric field (E-field) between the gate and the source / drain region is formed. You can see the effect to lower.

Referring to FIG. 2B, after depositing a spacer insulating film on the entire surface of the substrate including the first groove 50, the spacer insulating layer is etched and formed on both sidewalls of the first groove 50 including the first mask pattern 40. A spacer 60 is formed. Then, by using the first mask pattern 40 including the spacer 60 as an etch mask, the substrate portion under the bottom of the first groove 50 is etched to have a width smaller than that of the first groove 50. The second groove 70 is formed to have a width of 0.5 to 0.9 with respect to the width of the subsequent gate, and is formed to a depth of 50 to 2000 microns.

Here, the present invention forms a second groove 70 having a width smaller than the width of the gate, so that when a misalignment occurs between a subsequent gate and the groove (the first groove and the second groove), the second groove 70 The gate material formed on the N-A is not subjected to an attack, thereby minimizing the variation of the threshold voltage Vt.

In other words, in general, when misalignment occurs between the gate and the groove, overetch of the gate material is unavoidable. In the present invention, the second groove 70 having a width smaller than the width of the gate is formed. The gate material formed in the second groove 70 can avoid excessive etching. Therefore, it is possible to have uniformity threshold voltage.

Next, a first threshold voltage control ion implantation is performed in the substrate surface below the second groove 70.

Referring to FIG. 2C, a gate material is deposited on the entire surface of the substrate including the second groove 70 and the first groove 50 in a state where the spacer, the first mask pattern and the buffer oxide film are removed. Here, the gate material may include a gate insulating film 80, a conductive film 90, and a hard mask film 100. Next, after forming a second mask pattern (not shown) covering the gate formation region on the hard mask layer 100, the second mask pattern is used as an etch mask and the hard mask layer 100 is electrically conductive. By etching the film 90 and the gate insulating film 80, the recess gate 110 having a width smaller than the width of the first groove 50 and larger than the width of the second groove 70 is formed. Form.

In general, when misalignment occurs between the gate and the groove, the conductive film is etched up to the portion formed in the groove by over-etching the conductive film 90. As in the present invention, the first groove 50 and the second groove 70 Due to the formation, the excessive etching of the conductive film 90 is not attacked by the second groove 70.

As such, the excessive etching of the conductive layer 90 may attack only the portion of the first groove 50, thereby minimizing the increase in the variation of the threshold voltage even when the reoxidation layer generated during the subsequent gate reoxidation process increases.

Referring to FIG. 2D, a gate reoxidation process is performed on a substrate resultant to compensate for etch damage caused by etching the gate material, including the sidewall of the first groove 50. An oxide-based reoxidation film 120 is formed on the surface of the substrate 10 and both side walls of the gate 110.

Meanwhile, as shown in FIG. 3, when an alignment occurs between the gate 110 ′ and the grooves 50 ′ and 70 ′, the first groove 50 ′ during the gate reoxidation process. An oxide-based reoxidation film 120 'is formed on the surface of the substrate and both side walls of the gate 110', including both sidewalls. As such, the reoxidized film 120 'is formed on both side walls of the gate 110', thereby reducing the E-field between the gate 110 'and the subsequent source / drain regions. You can get it.

In FIG. 3, reference numeral 10 'denotes a semiconductor substrate, 20' denotes an isolation layer, 80 'denotes a gate insulating layer, 90' denotes a conductive layer, and 100 'denotes a hard mask layer.

Referring to 2e, the secondary threshold voltage control ion implantation is performed in the substrate surface on both sides of the gate 110 including the reoxidation film 120. Thereafter, an insulating film for a gate spacer is deposited on the entire surface of the substrate including the reoxidation film 120, and then etched to form gate spacers 130 on both sidewalls of the gate 110 including the reoxidation film 120. do.

Next, a high concentration of impurity ions are implanted into the surface of the substrate on both sides of the gate 110 including the reoxidation film 120, so that the source / drain regions S are formed on the surface of the substrate on both sides of the gate 110 including the reoxidation film 120. / D) to form a MOSFET device according to the present invention.

As described above, even if misalignment occurs between the gate and the groove, the transient etching of the conductive film is attacked only to the portion formed in the first groove, so that a uniform threshold voltage of the device can be expected, and the width of the gate is greater than the width of the gate. Due to the width of the first groove formation, the source / drain regions may have a symmetrical profile.

In addition, when the gate and the groove are aligned, a reoxidation film is formed on both sidewalls of the first groove, thereby lowering the electric field between the gate and the source / drain region, thereby preventing leakage current of the device.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention forms a groove having a width greater than the width of the gate and a groove having a width smaller than the width of the gate, so that even if misalignment occurs between the gate and the groove, a uniform threshold voltage of the transistor can be expected. In addition, the source / drain region may have a profile of symmetry.

In addition, when the gate and the groove are aligned, an oxide film is formed on both sidewalls of the groove having a width larger than the width of the gate, so that an electric field (E-Field) between the gate and the source / drain region can be lowered, and thus a leakage current. (current leakage) can be reduced, and as a result, it is possible to improve the refresh characteristics of the device.

Claims (8)

Forming a first mask pattern exposing the gate formation region on the semiconductor substrate; Etching the exposed portion of the substrate using the first mask pattern as an etching mask to form a first groove; Forming spacers on both sidewalls of the first groove including the first mask pattern; Etching the substrate portion below the bottom of the first groove by using the first mask pattern including the spacers as an etching mask to form a second groove having a width smaller than that of the first groove;  Removing the spacers and the first mask pattern; Forming a gate having a width smaller than a width of the first groove on a front surface of the substrate including the second groove and the first groove; Forming an oxide film on the surface of the substrate and on both side walls of the gate, including both side walls of the first groove; And Forming a source / drain region in the substrate surface on both sides of the gate including the oxide film; Method for producing a MOSFET device comprising a. The method of claim 1, And the first groove is formed to a depth of 50 to 2000 microns. The method of claim 1, The first groove is formed to have a width of 1.1 to 1.5 compared to the width of the gate of the MOSFET device manufacturing method. The method of claim 1, And performing a first threshold voltage control ion implantation into the substrate surface below the second groove after the forming of the second groove and before removing the spacer and the first mask pattern. A method for manufacturing a MOSFET device. The method of claim 1, And the second groove is formed to a depth of 50 to 2000 microns. The method of claim 1, And the second groove is formed to have a width of 0.5 to 0.9 with respect to the width of the gate. The method of claim 1, And the oxide film is a reoxidation film formed during a gate reoxidation process to compensate for etch damage generated during gate formation. The method of claim 1, After forming an oxide film on both side walls of the gate, and before forming a source / drain region in the substrate surface on both sides of the gate including the oxide film, Performing secondary threshold voltage control ion implantation into the substrate surfaces on both sides of the gate including the oxide film; And forming spacers on both sidewalls of the gate including the oxide layer.

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