KR20050028514A - Semiconductor device having gates of mos transistors and method of the same - Google Patents

Abstract

A semiconductor device having a gate of a MOS(metal oxide semiconductor) transistor is provided to prevent the sidewall of a lower gate electrode from being damaged by an etch process by forming the lower gate electrode in a trench having an active region. A gate insulation layer(114) is conformally formed in a trench(112) formed in a predetermined region of a substrate(100). A lower gate electrode(116a) is disposed on the gate insulation layer to fill the trench. At least a part of the lower gate electrode is made of metal silicide(120). An upper gate electrode(130) is formed on the lower gate electrode. A pair of impurity diffusion layers are formed in the substrate at both sides of the upper gate electrode.

Description

Semiconductor device having gates of MOS transistors and method for forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor device having a gate of a MOS transistor and a method of forming the same.

In general, the MOS transistor of the semiconductor device may include source / drain regions spaced apart from each other in the semiconductor substrate, and a gate electrode disposed over a channel region between the source / drain regions.

At present, while semiconductor devices have been highly integrated, high operating speeds are required. In other words, while the line width of the gate electrode is gradually reduced, a decrease in the resistance of the gate electrode is required. Accordingly, as a method of reducing the resistance of the gate electrode, a gate electrode having a multiple layered structure has been proposed. A method of forming a MOS transistor having a gate of a conventional multilayer structure will be described with reference to FIGS. 1 and 2.

1 and 2 are cross-sectional views illustrating a method of forming a conventional MOS transistor.

1 and 2, a gate oxide film 2, a doped polysilicon film 3, a tungsten silicide film 4, and a hard mask film 5 are formed on a semiconductor substrate 1 (hereinafter referred to as a substrate). Form in turn. The gate oxide film 2 is formed of a thermal oxide film, and the hard mask film 5 is formed of a silicon nitride film.

The hard oxide film 5, the tungsten silicide film 4, the doped polysilicon film 3, and the gate oxide film 2 are successively patterned and stacked to sequentially form a gate oxide film pattern 2a, a gate electrode 7, and The gate pattern 10 formed of the hard mask pattern 5a is formed. The gate electrode 7 is a multi-layer structure composed of a doped polysilicon pattern 3a and a tungsten silicide pattern 4a that are sequentially stacked. The tungsten silicide pattern 4a is a conductive material having a lower resistance than the doped polysilicon pattern 3a. Accordingly, the tungsten silicide pattern 4a may reduce the resistance of the gate electrode 7 even if the line width of the gate electrode 7 is reduced.

Meanwhile, due to an etching process of the patterning process for forming the gate pattern 10, the sidewalls of the gate pattern 10 or the substrate 1 on both sides of the gate pattern 10 may be damaged. In order to cure this, after the gate pattern 10 is formed, a gate oxidation process is performed. When the gate oxidation process is performed, an oxide layer 8 may be formed on sidewalls of the gate electrode 7. When the substrate 1 on both sides of the gate pattern 10 is exposed, the oxide layer 8 may also be formed on the exposed surface of the substrate 1. Subsequently, source / drain regions 9 are formed by selectively implanting impurity ions into the substrate 1 on both sides of the gate pattern 10.

In the above-described method of forming a MOS transistor, in order to form the gate pattern 10, a multilayer film made of various films 2, 3, 4, and 5 is patterned. Accordingly, the profile of the gate pattern 10 (particularly, the sidewall profile) may be very degraded. As a result, the characteristics of the gate electrode 7 may be degraded.

In addition, the gate oxidation process can cause various problems. That is, since the oxide film 8 is formed on both sidewalls of the gate electrode 7, the substantial line width of the gate electrode 7 may be reduced, thereby reducing the resistance of the gate electrode 7. In addition, when the gate electrode 7 includes a metal film such as tungsten, by-products having strange shapes may be formed in the metal film due to the gate oxidation process. The byproducts may be separated from the gate pattern 10 to cause various problems in the semiconductor device in the form of particles. For example, it may cause electrical short between the elements or failure of the subsequently formed patterns.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a semiconductor device capable of preventing deterioration of a gate constituting a MOS transistor and a method of forming the same.

Another object of the present invention is to provide a semiconductor device and a method of forming the same that can prevent deterioration of the semiconductor device that may be caused by a gate oxidation process.

Another object of the present invention is to provide a semiconductor device and a method of forming the same that can simultaneously improve the characteristics of NMOS and PMOS transistors.

Provided is a semiconductor device having a gate of a MOS transistor for solving the above technical problems. The device includes a gate insulating film conformally formed in a trench formed in a predetermined region of a substrate, and a lower gate electrode disposed to fill the trench on the gate insulating film. The lower gate electrode is formed of at least a portion of the metal silicide. An upper gate electrode is formed on the lower gate electrode. A pair of impurity diffusion layers are disposed on the substrate on both sides of the upper gate electrode.

In detail, the lower gate electrode may be formed of metal silicide in all portions thereof. The upper gate electrode may be made of a metal different from the metal included in the metal silicide. Alternatively, the upper gate electrode and the metal silicide may include the same metals as each other.

To provide a method of forming a semiconductor device having a gate of a MOS transistor for solving the above technical problems. The method includes successively patterning an insulating film formed on a substrate and the substrate to form a trench in the substrate. A gate insulating layer is formed on inner walls and bottom surfaces of the trench, and a lower gate electrode filling the trench is formed on the gate insulating layer. At least a portion of the lower gate electrode is formed of metal silicide, and an upper gate electrode is formed on the lower gate electrode. A pair of impurity diffusion layers are formed on the substrate on both sides of the upper gate electrode.

In detail, the forming of the trench and the lower gate electrode may include sequentially forming an insulating film and a hard mask film on a substrate. The hard mask layer and the insulating layer are successively patterned to form grooves to expose a predetermined region of the substrate, and the exposed substrate is selectively etched to form the trenches. The hard mask film is removed from the substrate having the trench to expose the insulating film. A lower gate conductive layer is formed on the entire surface of the substrate having the gate insulating layer, and the lower gate conductive layer is planarized until the insulating layer is exposed to form the lower gate electrode.

In example embodiments, the forming of the trench and the lower gate electrode may include sequentially forming an insulating film and a hard mask film on a substrate, and subsequently patterning the hard mask film and the insulating film to expose a predetermined region of the substrate. Forming a groove, selectively etching the exposed substrate to form the trench, forming a lower gate conductive film filling the trench on the entire surface of the substrate having the gate insulating film, and forming the trench; And continuously planarizing the hard mask layer until the insulating layer is exposed to form the lower gate electrode.

In example embodiments, the forming of the metal silicide and the upper gate electrode may include depositing a metal film on an entire surface of the substrate having the lower gate electrode. A silicidation process is performed to form at least a portion of the lower gate electrode with metal silicide, and to remove the unreacted portion of the metal film to expose the lower gate electrode. An upper gate conductive layer is formed on the entire surface of the substrate, and the upper gate conductive layer is patterned to form the upper gate electrode.

In example embodiments, the forming of the metal silicide and the upper gate electrode may include depositing a metal film on an entire surface of the substrate having the lower gate electrode and performing a silicide process to at least partially deposit the metal silicide. And forming an upper gate electrode by patterning an unreacted portion of the metal film.

In an embodiment, the lower gate electrode may be formed of metal silicide in all portions thereof.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

3A is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention, and FIG. 3B is a cross-sectional view showing another shape of a lower gate electrode in a semiconductor device in accordance with a preferred embodiment of the present invention.

3A and 3B, a semiconductor device according to a preferred embodiment of the present invention includes a device isolation film 102 disposed in a predetermined region of a semiconductor substrate (hereinafter, referred to as a substrate) to define an active region. The device isolation layer 102 may be a trench type device isolation layer.

A trench 112 crossing the active region is disposed, and a conformal gate insulating layer 114 is disposed on the inner walls and the bottom surface of the trench 112. The lower gate electrode 116a filling the trench 112 is disposed on the gate insulating layer 114. At least a portion of the lower gate electrode 116a is formed of the metal silicide 120. For example, a lower portion of the lower gate electrode 116a may be formed of doped polysilicon, and an upper portion thereof may be formed of metal silicide 120. The gate insulating layer 114 may be formed of a silicon oxide layer, in particular, a thermal oxide layer. The metal silicide 120 may be made of nickel silicide, cobalt silicide, titanium silicide, tantalum silicide or nickel-tantalum silicide.

Alternatively, to further reduce the resistance of the gate, as shown in FIG. 3B, the lower gate electrode 216 may be formed of metal silicide in all portions thereof. When the lower gate electrode 216 is applied to the NMOS and PMOS transistors simultaneously, the characteristics of the NMOS and PMOS transistors may be improved at the same time. That is, due to the lower gate electrode 216, the threshold voltage required by the NMOS transistor and the threshold voltage required by the PMOS transistor may be simultaneously implemented. In addition, since the lower gate electrode 216 is applied to the PMOS transistor, it is possible to prevent a phenomenon in which boron penetrates into the gate oxide film from a gate doped with conventional borons. The lower gate electrode 216 may be made of nickel silicide, cobalt silicide, titanium silicide, tantalum silicide or nickel-tantalum silicide.

An upper gate electrode 130 is disposed on the lower gate electrode 116a. The lower and upper gate electrodes 116a and 130 are electrically connected to each other. The upper gate electrode 130 may have a wider width than the lower gate electrode 116a. The upper gate electrode 130 may be formed of a metal film having a lower resistance than the lower gate electrode 116a. The upper gate electrode 130 may be made of tungsten, copper, or aluminum. Alternatively, the upper gate electrode 130 may be made of the same metals as the metals included in the metal silicide 120. For example, the upper gate electrode 130 may be made of nickel, cobalt, titanium, tantalum, or nickel-tantalum. The lower gate electrode 116a and the upper gate electrode 130 constitute a gate of a MOS transistor.

A gate hard mask pattern 124a may be disposed on the upper gate electrode 130. Spacers 127 may be disposed on both sidewalls of the upper gate electrode 130 and the gate hard mask pattern 124a. The gate hard mask pattern 124a and the spacer 127 may be formed of a silicon nitride layer.

A buffer insulating layer 104 ′ may be disposed on the substrate 100 at both sides of the upper gate electrode 130. When the upper gate electrode 130 has a wider width than the lower gate electrode 116a, the buffer insulating layer may be formed between both edges of the upper gate electrode 130 and the substrate 100. A portion of 104 ') is interposed.

A pair of impurity diffusion layers 129 are disposed in the active region on both sides of the upper gate electrode 130. The impurity diffusion layers 129 are positioned at both sides of the lower gate electrode 116a and correspond to source / drain regions of the MOS transistor. In particular, the impurity diffusion layers 129 are formed of elevated source / drain regions. The impurity diffusion layer 129 may have an LED structure including a low concentration diffusion layer 126 and a high concentration diffusion layer 128. 3A or 3B, the impurity diffusion layer 129 completely covers the sidewalls of the lower gate electrode 116a, but the impurity diffusion layer 129 is formed on the lower sidewall of the lower gate electrode 116a. It may not be covered. In other words, the channel region of the MOS transistor may be located under the bottom surface of the lower gate electrode 116a. In addition, an edge of the channel region may extend to the lower sidewall of the lower gate electrode 116a.

In the above-described semiconductor device, the gate of the MOS transistor has a lower gate electrode 116a formed of metal silicide or a portion thereof, and the upper gate electrode having a lower resistance than the lower gate electrode 116a. 130. Accordingly, the resistance of the gate can be reduced to improve the operating speed of the semiconductor device. In addition, the lower gate electrode 116a fills the trench 112. Accordingly, both side walls of the lower gate electrode 116a are not damaged by etching. As a result, the semiconductor device according to the present invention does not require a conventional gate oxidation process.

4 to 9 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with a preferred embodiment of the present invention, and FIGS. 10 and 11 illustrate forming an upper gate electrode of a semiconductor device in accordance with a preferred embodiment of the present invention. Process sectional drawing for demonstrating another method.

Referring to FIG. 4, an isolation region 102 is formed in a predetermined region of the substrate 100 to define an active region. A buffer insulating film 104 and a first hard mask film 106 are sequentially formed on the entire surface of the substrate 100 having the device isolation film 102. The buffer insulating layer 104 may be formed as an insulating layer that buffers stress between the hard mask layer 106 and the substrate 100. For example, the buffer insulating film 104 may be formed of a silicon oxide film such as a thermal oxide film or a CVD silicon oxide film. The first hard mask layer 106 may have an etching selectivity with respect to the substrate 100, and may be formed of an insulating layer, for example, a silicon nitride layer having a dense structure.

The first hard mask layer 106 and the buffer insulating layer 104 are successively patterned to form a groove 110 exposing a predetermined region of the active region. The groove 110 may be formed to cross the active region.

5, 6, and 7, the trench 112 may be formed by selectively etching the active region exposed to the groove 110. The first hard mask layer 106 is removed from the substrate 100 having the trench 112 to expose the buffer insulating layer 104. A conformal gate insulating layer 114 is formed on the sidewalls and the bottom surface of the trench 112. The gate insulating film 114 is preferably formed of a thermal oxide film. Thus, when the gate insulating layer 114 is formed, sidewalls and bottom surfaces of the trench 112, which may be etched, may be cured. The forming of the gate insulating layer 114 may be performed before or after removing the first hard mask layer 106.

A lower gate conductive layer 116 is formed on the entire surface of the substrate 100 having the gate insulating layer 114 to fill the trench 112. The lower gate conductive layer 116 may be formed of a doped polysilicon layer. The lower gate conductive layer 116 is planarized until the buffer insulating layer 104 is exposed to form the lower gate electrode 116a in the trench 112.

Alternatively, the first hard mask layer 106 may be removed together in the process of planarizing the lower gate conductive layer 116. In other words, after the trench 112 is formed, the gate insulating layer 114 is formed, and the lower gate conductive layer 116 filling the trench 112 on the first hard mask layer 106 is formed. Form. Subsequently, the lower gate conductive layer 116 and the first hard mask layer 106 may be planarized until the buffer insulating layer 104 is exposed to form the lower gate electrode 116a.

The metal layer 118 is deposited on the entire surface of the substrate 100 having the lower gate electrode 116a and a silicide process is performed to form at least a portion of the lower gate electrode 116a as the metal silicide 120. The silicided process may be a thermal process. The process of depositing the metal film 118 and the silicideation process may be performed in-situ in one process chamber. That is, by maintaining the internal temperature of the process chamber in which the metal film 118 is deposited at the process temperature required by the silicidation process, the metal film 118 is deposited and the upper portion of the lower gate electrode 116a. The metal silicide 120 is formed from a surface. The metal layer 118 may be formed of nickel, cobalt, titanium, tantalum, or nickel-tantalum. Accordingly, the metal silicide 120 may be formed of nickel silicide, cobalt silicide, titanium silicide, tantalum silicide or nickel-tantalum silicide.

In addition, in order to further lower the resistance of the lower gate electrode 116a and simultaneously improve the characteristics of the NMOS and PMOS transistors, the thickness of the metal film 118 or the process time of the silicideization process may be adjusted. All portions of the lower gate electrode 116a may be metal silicided. As a result, the lower gate electrode 216 of FIG. 3B may be implemented.

8 and 9, the unreacted portion of the metal layer 118 that is not silicided is removed to expose the buffer insulating layer 104 and the lower gate electrode 116a. The upper gate conductive layer 122 and the second hard mask layer 124 are sequentially formed on the entire surface of the substrate 100 having the exposed lower gate electrode 116a. The upper gate conductive layer 122 may be formed of a conductive layer having a lower resistance than the lower gate electrode 116a, for example, tungsten, copper, or aluminum, which is a metal layer.

The second hard mask layer 124 and the upper gate conductive layer 122 are successively patterned to form the upper gate electrode 130 and the gate hard mask pattern 124a sequentially stacked on the lower gate electrode 116a. Form. In this case, since the buffer insulating layer 104 is not a gate insulating layer, the buffer insulating layer 104 is formed to a sufficient thickness to protect the active regions on both sides of the upper gate electrode 130. That is, a portion of the buffer insulating layer 104 may be recessed by the overetching of the patterning process, but the surface of the substrate 100 may be sufficiently protected. After the upper gate electrode 130 is formed, the recessed buffer insulating layer 104 ′ on both sides of the upper gate electrode 130 may be removed by an etching process that does not cause etching damage, for example, wet etching. have. Alternatively, the recessed buffer insulating film 104 ′ may be used as a buffer film in a process of implanting impurity ions which are subsequently remaining. The upper gate electrode 130 may be formed to have a wider line width than the lower gate electrode 116a. In this case, an edge of the upper gate electrode 130 is electrically insulated from the active region by the recessed buffer insulating layer 104 ′. When the upper gate electrode 130 is formed of copper, the upper gate electrode 130 may be formed by a damascene technique using a mold layer (not shown). The lower and upper gate electrodes 116a and 130 form a gate of a MOS transistor.

Alternatively, the upper gate electrode 130 may be formed in another way. This method will be described with reference to FIGS. 10 and 11.

10 and 11, a metal film 118 ′ is deposited on the entire surface of the substrate 100 having the lower gate electrode 116a. At this time, the metal film 118 'is deposited to a sufficient thickness. A silicidation process is performed to form at least a portion of the lower gate electrode 116a as the metal silicide 120. Even in this case, the process of depositing the metal film 118 'and the silicidation process may be performed in-situ. The metal layer 118 ′ may be formed of nickel, cobalt, titanium, tantalum, or nickel-tantalum. Therefore, the metal silicide 120 may be formed of nickel silicide, cobalt silicide, titanium silicide, tantalum silicide or nickel-tantalum silicide.

Also in this method, all parts of the lower gate electrode 116a may be metal silicided by adjusting a process time of the silicidation process to implement the lower gate electrode 216 of FIG. 3B.

Next, a second hard mask layer 124 ′ is formed on the unreacted portion of the metal layer 118 ′. The second hard mask layer 124 ′ may be formed of a silicon nitride layer.

An upper gate electrode 130 'and a gate hard mask sequentially stacked on the lower gate electrode 116a by successively patterning unreacted portions of the second hard mask layer 124' and the metal layer 118 '. The pattern 124a 'is formed. That is, in this method, during the metal silicide formation process, the unreacted portion of the unreacted metal film 118 'is patterned to form the upper gate electrode 130'. Thus, the metal silicide 120 and the upper gate electrode 130 ′ include the same metals. According to this method, processes for forming the upper gate electrode 130 'can be simplified.

9, a pair of low concentration diffusion layers 126 are formed by selectively implanting low dose impurity ions using the upper gate electrode 130 as a mask. Subsequently, a spacer 127 shown in FIG. 3A or 3B is formed, and a high dose of impurity ions are selectively implanted to form a pair of high concentration diffusion layers 128 shown in FIG. 3. The low concentration and high concentration diffusion layers 126 and 128 constitute the impurity diffusion layer 129 of FIG. 3A or 3B. Forming the high concentration diffusion layer 128 may be omitted.

In the above-described method for forming a semiconductor device, the lower gate electrode 116a is formed by planarizing the lower gate conductive layer 116 filling the trench 112. That is, sidewalls of the lower gate electrode 116a are not etched. Accordingly, the profile and characteristics of the lower gate electrode 116a may be improved. In addition, a part or all of the lower gate electrode 116a may be formed of metal silicide, and the lower gate electrode 116a may be formed on the lower gate electrode 116a to reduce the resistance of the gate. Can improve speed.

In addition, the sidewalls of the lower gate electrode 116a are not etched, and in the patterning process for forming the upper gate electrode 130, the substrate 100 is formed by the buffer insulating layer 104 formed to a sufficient thickness. Protected. Thus, no conventional gate oxidation process is required. As a result, it is possible to prevent deterioration of the semiconductor device, which may be caused by the conventional gate oxidation process.

Further, by the impurity diffusion layer 129, source / drain regions of the MOS transistor have an elevated shape. As a result, it is possible to prevent the short channel effect of the MOS transistor, which may be caused by high integration of the semiconductor device.

As described above, according to the present invention, by forming the lower gate electrode in the trench formed in the active region, sidewalls of the lower gate electrode are protected from etching damage. In addition, by forming a part or all of the lower gate electrode of metal silicide and forming a lower resistance upper gate electrode on the lower gate electrode, the resistance of the gate may be reduced to improve the operation speed of the semiconductor device.

In addition, since the lower gate electrode is formed in the trench and the upper gate electrode is formed, a conventional gate oxidation process is not required because a buffer insulating film protects active regions on both sides of the upper gate electrode. As a result, it is possible to prevent deterioration of the semiconductor device, which may be caused by the conventional gate oxidation process.

1 and 2 are cross-sectional views illustrating a method of forming a conventional MOS transistor.

3A is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention.

3B is a cross-sectional view illustrating another form of the lower gate electrode of the semiconductor device according to the exemplary embodiment of the present invention.

4 through 9 are cross-sectional views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention.

10 and 11 are cross-sectional views illustrating another method of forming an upper gate electrode among semiconductor devices according to an exemplary embodiment of the present invention.

Claims (11)

A gate insulating film conformally formed in the trench formed in the predetermined region of the substrate; A lower gate electrode disposed to fill the trench on the gate insulating layer, at least a portion of which is formed of metal silicide; An upper gate electrode formed on the lower gate electrode; And And a pair of impurity diffusion layers formed on the substrate on both sides of the upper gate electrode. The method of claim 1, And all portions of the lower gate electrode are formed of metal silicide. The method of claim 1, And the upper gate electrode is formed of a metal different from the metal included in the metal silicide. The method of claim 1, And the upper gate electrode and the metal silicide include the same metals as each other. Successively patterning an insulating film formed on a substrate and the substrate to form a trench in the substrate; Forming a gate insulating film on inner walls and bottom surfaces of the trench; Forming a lower gate electrode filling the trench on the gate insulating layer; Forming at least a portion of the lower gate electrode with metal silicide; Forming an upper gate electrode on the lower gate electrode; And Forming a pair of impurity diffusion layers on the substrate on both sides of the upper gate electrode. The method of claim 5, wherein Forming the trench and the lower gate electrode, Sequentially forming an insulating film and a hard mask film on the substrate; Successively patterning the hard mask film and the insulating film to form a groove exposing a predetermined region of the substrate; Selectively etching the exposed substrate to form the trench; Removing the hard mask film from the substrate having the trench to expose the insulating film; Forming a lower gate conductive layer filling the trench on an entire surface of the substrate having the gate insulating layer; And Forming the lower gate electrode by planarizing the lower gate conductive layer until the insulating layer is exposed. The method of claim 5, wherein Forming the trench and the lower gate electrode, Sequentially forming an insulating film and a hard mask film on the substrate; Successively patterning the hard mask film and the insulating film to form a groove exposing a predetermined region of the substrate; Selectively etching the exposed substrate to form the trench; Forming a lower gate conductive layer filling the trench on an entire surface of the substrate having the gate insulating layer; And And planarizing the lower gate conductive layer and the hard mask layer continuously until the insulating layer is exposed to form the lower gate electrode. The method of claim 5, wherein Forming the metal silicide and the upper gate electrode, Depositing a metal film on an entire surface of the substrate having the lower gate electrode; Performing a silicidation process to form at least a portion of the lower gate electrode with metal silicide; Removing the unreacted portion of the metal film to expose the lower gate electrode; Forming an upper gate conductive layer on an entire surface of the substrate; And And patterning the upper gate conductive layer to form the upper gate electrode. The method of claim 5, wherein Forming the metal silicide and the upper gate electrode, Depositing a metal film on an entire surface of the substrate having the lower gate electrode; Performing a silicidation process to form at least a portion of the lower gate electrode with metal silicide; And Patterning the unreacted portion of the metal film to form the upper gate electrode. The method according to claim 8 or 9, And depositing the metal film and performing the silicided process are performed in situ. The method of claim 1, And wherein all of its lower gate electrodes are formed of metal silicide.