KR20010083626A - Transistor forming method - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor is provided to decrease junction capacitance of a source/drain region and to prevent hot carriers, by adding a reoxidation process of a gate oxide layer and a process for forming a source/drain. CONSTITUTION: A gate oxide layer and a material layer for a dummy gate are formed on a semiconductor substrate(21). The material layer and the gate oxide layer are etched to form the dummy gate. An oxide layer(25) is formed in an active region. The first insulation layer is formed on the entire structure, and etched back to form the first insulation layer sidewall(26) on a side surface of the dummy gate. Ions are implanted to the substrate to form a low density source/drain region(27) by using the first insulation layer sidewall as a mask. The second insulation layer is formed on the entire surface, and etched back to form the second insulation layer sidewall(28) on a side surface of the first insulation layer sidewall. Ions are implanted into the substrate to form a high density source/drain region(29) by using the second insulation layer sidewall as a mask. An interlayer dielectric(30) is formed. A part of the upper portion of the material layer is eliminated, and the material layer is removed. Ions are implanted into the substrate to control a threshold voltage through the exposed gate oxide layer. A channel(31) and a metal layer(32) are formed on the entire surface, and a planarization process is performed to expose the interlayer dielectric.

Description

Transistor Formation Method {TRANSISTOR FORMING METHOD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a transistor, and in particular, a source / drain region is first formed using a dummy gate and then a replacement gate process for forming a channel, a gate oxide film, and a gate is used. The present invention relates to a method for forming a transistor in which the electric field value is lowered and a thick gate oxide film is formed in the active region so as to be suitable for increasing the reliability of the hot carrier.

Currently, polysilicon is mainly used as a gate material for MOS transistors in semiconductor chips, but the use of metal gates is increasing due to the high integration and high speed of devices (IEDM98 p.777).

In order to improve the characteristics of the transistor and increase the reliability, a replacement gate process has been proposed in which a source / drain region is formed using a dummy gate, followed by implanting channel ions, and forming a gate oxide film and a metal gate. ED-42 (1) p.94, EDL-17 (4) 0.157, IEDM97 p.821, IEDM98 p.785)

An embodiment of the conventional transistor forming method is described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.

The sacrificial oxide film 3 and the polysilicon 4 are formed on the semiconductor substrate 1 on which the trench 2 is formed, and the polysilicon 4 and the sacrificial oxide film 3 are etched in accordance with the region where the gate is to be formed. Forming a source / drain region (5) by forming a dummy gate and implanting ions into the active region of the semiconductor substrate (1) using the formed dummy gate as a hard mask; A second step of forming an interlayer insulating film (6) on the upper surface of the formed structure, and planarizing it so that an upper portion of the dummy gate is exposed; After removing the polysilicon 4 and the sacrificial oxide layer 3 forming the dummy gate, and implanting ions on the exposed semiconductor substrate 1 as necessary, the channel is formed while adjusting the threshold voltage, and then the semiconductor substrate. A third step of forming a gate oxide film 7 on (1); In a fourth process, a metal film 8 is formed on the upper surface of the structure, and the metal film 8 is flattened to expose the interlayer insulating film 6 to form a metal gate.

First, as shown in FIG. 1A, a sacrificial oxide film 3 and a polysilicon 4 are formed on an upper portion of the semiconductor substrate 1 on which the trench 2 is formed, and the polysilicon 4 is aligned with a region where a gate is to be formed. And the sacrificial oxide layer 3 is etched to form a dummy gate.

In addition, the formed dummy gate is implanted with ions into the active region of the semiconductor substrate 1 using a hard mask to form a source / drain region 5.

At this time, by forming the source / drain regions 5 as described above, sufficient heat treatment is possible while proceeding with subsequent processes after ion implantation, thereby reducing the resistance of the source / drain regions 5.

Next, as shown in FIG. 1B, an interlayer insulating film 6 is formed on the upper surface of the formed structure, and planarized so that the upper portion of the dummy gate is exposed.

Next, as shown in FIG. 1C, the polysilicon 4 and the sacrificial oxide film 3 forming the dummy gate are removed, and if necessary, the threshold voltage is obtained by implanting ions onto the exposed semiconductor substrate 1. After the channel is formed with adjustment, a gate oxide film 7 is formed on the semiconductor substrate 1.

In this case, the characteristics of the transistor can be improved by injecting the channel ions and forming the gate oxide layer 7 and thus eliminating the need for a high temperature process. However, the formed source / drain regions 5 and the channel implantation regions Overlap occurs, resulting in increased junction capacitance and some loss of reliability for hot carriers.

Next, as shown in FIG. 1D, a metal film 8 is formed on the entire upper surface of the formed structure, and planarized so that the interlayer insulating film 6 is exposed to form a metal gate.

In the case of forming the metal gate as described above, since the gate is not required to be patterned, plasma damage of the gate oxide film 7 is prevented by the etching process, thereby improving reliability of the gate oxide film 7.

In the conventional transistor formation method as described above, a portion where the ion implantation region for threshold voltage regulation and channel formation overlaps with the source / drain region occurs, resulting in a large junction capacitance, and reliability of the hot carrier is not guaranteed. There was a problem that the gate property is impossible to improve the reliability.

The present invention has been devised to solve the above-mentioned conventional problems, and an object of the present invention is to reduce the junction capacitance of the source / drain region while preventing all the hot carriers while including all the advantages of the conventional replacement gate process. The present invention provides a method of forming a transistor that can improve reliability while improving device characteristics.

1 is a cross-sectional view showing a conventional transistor forming method.

Figure 2 is a cross-sectional view of the procedure of an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

21: semiconductor substrate 22: trench

23: sacrificial oxide film 24: polysilicon

25 oxide film 26 first insulating film side wall

27 low concentration source / drain region 28 second insulating film side wall

29 high concentration source / drain region 30 interlayer insulating film

31 channel 32 metal film

In the transistor forming method for achieving the object of the present invention as described above, a gate oxide film and a dummy gate material film are formed on a semiconductor substrate on which a trench is formed, and the dummy gate material film and the gate oxide film are matched to a region where a gate is to be formed. Etching to form a dummy gate and forming an oxide film in the active region on the exposed semiconductor substrate; After forming the first insulating film on the upper surface of the formed structure, it is etched back to form the first insulating film side wall on the side of the dummy gate, and ion is implanted on the semiconductor substrate using the mask to form a low concentration source / drain region. After that, a second insulating film is formed on the entire upper surface of the wafer and etched back to form a second insulating film side wall on the side of the first insulating film side wall, and then ions are implanted onto the semiconductor substrate using a mask to form a high concentration source / drain. A second step of forming an area; A third step of forming an interlayer insulating film on the upper surface of the formed structure, and planarizing the upper portion of the dummy gate material film to remove the dummy gate material film; A fourth step of adjusting a threshold voltage by injecting ions onto the semiconductor substrate through the gate oxide film revealed in the above step, forming a channel, and then forming a metal film on the upper surface of the structure and flattening the interlayer insulating film to be exposed. It features.

The method of forming a transistor according to the present invention as described above will be described in detail with reference to a procedure cross-sectional view shown in FIGS. 2A to 2D as an embodiment.

First, as shown in FIG. 2A, the gate oxide layer 23 and the polysilicon 24 are formed on the semiconductor substrate 21 on which the trench 22 is formed, and the polysilicon 24 corresponds to the region where the gate is to be formed. After the gate oxide layer 23 is etched to form a dummy gate, the oxide layer 25 is formed thicker than the gate oxide layer 23 in the active region on the exposed semiconductor substrate 21.

By oxidizing the active region to form the oxide film 25 as described above, the outer portion of the gate oxide film 23 positioned below the dummy gate is oxidized and thickened.

Next, as shown in FIG. 2B, a first insulating film is formed on the upper surface of the formed structure and then etched back to form a first insulating film side wall 26 on the side of the dummy gate. Ions are implanted onto 21 to form a low concentration source / drain region 27.

As described above, since the first insulating film side wall 26 is formed on the side of the gate and ions are implanted to form the low concentration source / drain region 27, the ions forming the low concentration source / drain region 27 are formed in a subsequent process. The diffusion does not invade the channel formation region under the gate, and the hot carrier characteristic of the current flowing from the source / drain region to the gate is also improved by the thick gate oxide film 23.

A second insulating film is formed on the upper surface of the wafer and etched back to form a second insulating film side wall 28 on the side of the first insulating film side wall 26, and then, as a mask, on the semiconductor substrate 21. Ions are implanted to form a high concentration source / drain region 29.

In this case, in the ion implantation process for forming the low concentration source / drain region 27 and the high concentration source / drain region 29, the oxide layer 25 serves as a buffer layer to protect the semiconductor substrate 21.

Next, as shown in FIG. 2C, the interlayer insulating film 30 is formed on the upper surface of the formed structure, and the polysilicon 24 is removed after planarization so that a part of the upper portion of the polysilicon 24 is removed.

Next, as shown in FIG. 2D, ions are implanted on the semiconductor substrate 21 through the gate oxide film 23 exposed in the process to adjust the threshold voltage Vth, and then the channel 31 is formed. A metal film 32 is formed on the upper surface of the structure and planarized so that the interlayer insulating film 30 is exposed.

In this case, the gate oxide layer 23 may be damaged during the removal of the polysilicon 24 and the ion implantation for controlling the channel 31 and the threshold voltage. It can later be removed and formed again.

In the ion implantation process for forming the channel 31, the outer surface of the gate oxide layer 23 is thick, and thus, ion implantation is masked in the portion thereof, so that no ion is implanted in the previously formed source / drain regions 27 and 29. The junction capacitance of the drain regions 27 and 29 can be kept low.

The transistor forming method of the present invention as described above obtains low resistance of the source / drain by first forming the source / drain by applying the conventional replacement gate process, and the device characteristics due to the unnecessary high temperature process after the channel and gate formation. Taking all the advantages of the improvement, the gate oxide film reoxidation process and the source / drain formation process using the double sidewall of the dummy gate are added to lower the junction capacitance of the source / drain region and to prevent hot carriers. There is an effect that can increase the reliability while further improving the characteristics of the device.

Claims (2)

A gate oxide film and a dummy gate material film are formed on the trench-formed semiconductor substrate, and the dummy gate material film and the gate oxide film are etched according to the region where the gate is to be formed to form a dummy gate, and then the active region on the exposed semiconductor substrate. Forming a oxide film on the substrate; After forming the first insulating film on the upper surface of the formed structure, it is etched back to form the first insulating film side wall on the side of the dummy gate, and ion is implanted on the semiconductor substrate using the mask to form a low concentration source / drain region. After that, a second insulating film is formed on the entire upper surface of the wafer and etched back to form a second insulating film side wall on the side of the first insulating film side wall, and then ions are implanted onto the semiconductor substrate using a mask to form a high concentration source / drain. A second step of forming an area; A third step of forming an interlayer insulating film on the upper surface of the formed structure, and planarizing the upper portion of the dummy gate material film to remove the dummy gate material film; A fourth step of adjusting a threshold voltage by injecting ions onto the semiconductor substrate through the gate oxide film revealed in the above step, forming a channel, and then forming a metal film on the upper surface of the structure and flattening the interlayer insulating film to be exposed. Transistor formation method characterized by the above-mentioned. The method of claim 1, wherein the gate oxide layer is removed after the channel forming process is finished in the fourth process, and a new gate oxide layer is formed on the semiconductor substrate. The metal layer is formed on the wafer, and the interlayer dielectric layer is exposed. And planarizing the transistor to form a transistor.