JPH11186543A - High voltage resistant mosfet and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor structure and a method of manufacturing of the same which is capable of improving a drain voltage resistance of high voltage metal oxide semiconductor field-effect transistor(MOSFT) without lowering its drain current. SOLUTION: A 5 nm thickness gate insulation film 2 is formed on a silicon substrate 1. A 200 nm thickness and 0.18 μm-long gate electrode 3 is formed on the gate insulation film 2. Arsenic of 5×10<12> cm<-2> in dose is injected in an offset region 5, which is formed on the silicon substrate 1 in 0.4 μm length in a plane direction from the gate electrode 3. An intermediate layer 4 is formed in the length of 10 μm between the gate insulation film 2 and an offset region 5 on the silicon substrate 1 by arsenic injection of 2×10<14> cm<-2> in dose. A drain region 6 is formed on the silicon substrate 1 adjacently to the offset region 5. A source region 7 is formed on the silicon substrate 1, adjacent to the gate insulation film 2. A well, a device separation film, and a channel are formed as required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high voltage MOSFE.
The present invention relates to a method for manufacturing a T (metal-oxide-semiconductor field effect transistor) and a high breakdown voltage MOSFET.

[0002]

2. Description of the Related Art In mobile communication devices such as mobile phones,
A transistor that supplies transmission power to an antenna is used in a portion that transmits radio waves. Since this transistor is used at a high voltage in order to convert transmission power into radio waves efficiently and efficiently, this transistor is required to have characteristics with a large drain withstand voltage. When such a transistor having a large drain withstand voltage is realized by a MOSFET, the drain structure is devised to increase the withstand voltage.

In a MOSFET, when a voltage higher than a certain level is applied to a drain, a large electric field is generated at a boundary between a drain region and a channel portion, and breakdown occurs at this boundary portion. Therefore, how to reduce the electric field generated at the boundary between the drain region and the channel portion when the same drain voltage is applied is an issue of increasing the withstand voltage.

FIGS. 8 and 9 show the structure of a conventional high breakdown voltage MOSFET. In each of the high breakdown voltage MOSFETs shown in FIGS. 8 and 9, the impurity concentration in the portion near the drain gate is lowered to deplete this portion during operation, and a part of the voltage is absorbed here to increase the breakdown voltage. ing.

In FIG. 8, a drain region 6 and a gate electrode 3 are shown.
The offset region 5 which is a low-concentration layer having an impurity concentration of 10 ¹⁸ cm ⁻³ is provided between the electrodes to reduce the electric field (Shigeru Atsumi et al., JP-A-62-200757). Here, n ^{− of the} offset region 5 forms a pn junction with the p-type region of the silicon substrate 1, and the vicinity of the pn junction interface is depleted by applying a somewhat large voltage to the drain region 6. .

Therefore, a part of the electric field is absorbed by the depletion layer portion, and the electric field formed at the boundary between the drain region 6 and the channel immediately below the gate electrode 3 is reduced. In FIG. 9, a region having a low impurity concentration (here, an extremely low concentration region 8) is formed between the offset region 5 and the gate electrode 3 in the structure of the high breakdown voltage MOSFET of FIG. By forming the eight extremely low concentration regions, the high breakdown voltage M shown in FIG.
A higher breakdown voltage is achieved than in the case of OSFET.

[0007]

However, in the above-described structure of the high breakdown voltage MOSFET, since the impurity concentration of the offset region 5 is reduced in order to increase the breakdown voltage, the drain is depleted as the voltage is increased. The thickness of the layer region gradually increases from the channel end immediately below the gate electrode.

For this reason, even when the drain voltage is low at which there is no fear of the breakdown at the pn junction, the portion where the depletion layer is formed partially absorbs the electric field. As a result,
When the drain voltage is low, the electric field applied to the channel is reduced, the drain current is reduced, and the high voltage MOSFE
There is a disadvantage that the T switching speed is slow. The present invention has been made under such a background, and an object of the present invention is to provide a transistor structure that improves the drain breakdown voltage of a high breakdown voltage MOSFET without reducing the drain current amount.

[0009]

According to the first aspect of the present invention,
In a high withstand voltage MOFET, a gate electrode provided on a substrate via a gate insulating film, a source region provided at one end of the gate insulating film, and a first electrode provided at the other end of the gate oxide film. A drain region formed of the same conductivity type impurity as the first diffusion layer at an interval in the planar direction of the substrate between the diffusion layer and the first diffusion layer; and A first diffusion layer interposed between the drain region and a second diffusion layer formed of the same conductivity type impurity, and an impurity concentration of the second diffusion layer is equal to that of the drain region. The impurity concentration is set lower than the impurity concentration, and the impurity concentration of the first diffusion layer is a value between the impurity concentration of the second diffusion layer and the impurity concentration of the drain region.

According to a second aspect of the present invention, in the high-breakdown-voltage MOSFET of the first aspect, the source region is formed so as to be separated from the gate oxide film and the gate oxide film on a plane of the substrate. It is characterized by being formed from a second source diffusion layer having a depth smaller than the first source diffusion layer interposed between the source diffusion layer and the first source diffusion layer.

According to a third aspect of the present invention, there is provided a high voltage MOSFE.
In the method of manufacturing T, a gate electrode forming step of forming a gate electrode on the upper surface of the substrate; and a first step of introducing a first conductive impurity into the upper portion of the substrate using the gate electrode as a mask.
A conductive impurity introducing step, an insulating film forming step of forming a side insulating film on a side surface of the gate electrode, and using the gate electrode and the side insulating film as a mask, the first conductive impurity and A second conductive impurity introducing step of introducing a second conductive impurity of an opposite conductive type, and forming a resist between the upper surface of the gate electrode and a position for forming a drain region in the substrate plane direction. And a re-introduction step of re-introducing the first conductivity type impurity using the resist as a mask.

According to a fourth aspect of the present invention, in the method of manufacturing a MOSFET, a gate electrode forming step of forming a gate electrode on the upper surface of the substrate; And a first resist forming step of forming a first resist in a region between a predetermined distance from the gate electrode and a position where a drain region is formed in the plane direction of the substrate. A second introduction step of introducing the first conductive impurity using the first resist as a mask, and a second introduction step in a region from the upper surface of the gate electrode to a position where the drain region is formed in the plane direction of the substrate. A second resist forming step of forming a second resist, and a third step of introducing the first conductive impurity using the second resist as a mask.
And an introduction step.

According to a fifth aspect of the present invention, in the method for manufacturing a MOSFET, a gate electrode forming step of forming a gate electrode on an upper surface of the substrate; A first introduction step of introducing the first region into the region from the upper surface of the gate electrode to a position including the drain region formation portion in the substrate plane direction.
A first resist forming step of forming a first resist, a second introducing step of introducing the first conductive impurity using the first resist as a mask, and a first insulating film on a side surface of the gate electrode. Forming a first insulating film; forming a second insulating film on a side surface of the first insulating film; forming a second insulating film on the side surface of the first insulating film; A second resist forming step of forming a second resist up to the position of
A third introducing step of introducing the first conductive type impurity using the resist as a mask, a removing step of removing the first insulating film by etching, and a step of removing the first conductive film on the drain region forming side in the substrate plane direction. A third resist forming step of forming a third resist between the upper surface of the second insulating film and the position where the drain region is formed; and a third step of introducing the first conductive impurity using the third resist as a mask. And 4 introduction steps.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a longitudinal sectional view showing the structure of a high breakdown voltage MOSFET according to one embodiment of the present invention.
In this figure, 1 is a silicon substrate, and 5n
The gate insulating film 2 having a thickness of m is formed. On the upper surface of the gate insulating film 2, a thickness of 200 nm and a length of 0.18
A μm gate electrode is formed.

Reference numeral 5 denotes an offset region having an arsenic dose of 5 × 10 ¹² cm ⁻² , and is formed on the upper surface of the silicon substrate 1 so as to have a length of 0.4 μm in a plane direction from the gate electrode 3.
Reference numeral 4 denotes a medium-concentration region of an arsenic dose of 2 × 10 ¹⁴ cm ⁻² , which is formed on the upper surface of the silicon substrate 1 with a length of 10 nm interposed between the gate insulating film 2 and the offset region 5. . Reference numeral 6 denotes a drain region, which is formed adjacent to the offset region 5 on the upper surface of the silicon substrate 1. 7
Denotes a source region, which is formed adjacent to the gate insulating film 2 on the upper surface of the silicon substrate 1.

Although not shown in the figure, wells, element isolation films, and channels are formed as needed.

Next, a manufacturing method of an application example of the high breakdown voltage MOSFET according to the embodiment described above will be described with reference to FIG. FIG. 2 shows a high breakdown voltage MOSF in each part of the manufacturing process.
2 shows a cross-sectional structure of ET. As shown in FIG. 2A, the impurity concentration of p is about 1 × 10 ¹⁴ cm ^−3.
An element isolation film (not shown) is formed on the mold silicon substrate 11, and a well 12 is formed. Then, channel ions are implanted into the upper surface of the p-type silicon substrate 11.

Next, a gate insulating film 13 having a thickness of 5 nm is formed on the upper surface of the silicon substrate 11 by an oxidation process. Then, on the upper surface of the gate insulating film 13, a polysilicon film is formed with a thickness of 200 nm. Next, a resist is applied to the upper surface of the polysilicon film, and the polysilicon film is etched based on the pattern of the resist remaining after the exposure step and the development step, thereby forming the gate electrode 14.

Then, using this gate electrode 14 as a mask, a dose of 2 × 10 ¹⁴ at an acceleration energy of 20 keV.
Arsenic ions of cm ⁻² are implanted into the upper surface of the p-type silicon substrate 11. Thus, a medium concentration layer 15 and a medium concentration region 16 are formed on the upper surface of the p-type silicon substrate 11.

Next, as shown in FIG. 2B, a gate sidewall 17 having a thickness of 10 nm is formed on the sidewall of the gate electrode 14 using an insulating film. The gate side wall 17
Using the gate and the gate electrode 14 as a mask, boron ions are implanted into the upper surface of the p-type silicon substrate 11 with an acceleration energy of 5 keV and a dose of 1 × 10 ¹⁴ cm ⁻² . As a result, the medium concentration region 16 into which the ion implantation has been performed becomes the drain offset region 18.

Next, as shown in FIG. 2C, the resist 20 is placed on the drain formation region D side at a position 0.4 μm from the end of the gate electrode 14 to the drain offset region 18 starting from the top of the gate electrode 14. Formed until Using the resist 20 as a mask, the drain region 22 and the source region 2 which are high-concentration impurity layers are formed.
1 is formed by implanting arsenic ions with an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁵ cm ⁻² .

In the method described above, the depth of the source region 21 is about 100 nm. Here, in order to suppress the short channel effect, the gate electrode 14 of the source region 21 is formed.
In order to reduce the depth of the diffusion layer in the vicinity, before forming the resist 20 of FIG. 3C, a second gate side wall of several tens of nm is formed on the outer surface of the gate side wall 17 and the above-described FIG. The processing of (c) is performed.

In this manufacturing method, it is necessary to introduce impurities three times in fabricating the high breakdown voltage MOSTFT of the first embodiment. First, the middle concentration layer 19 is formed by implanting a first conductivity type impurity using the gate electrode 14 as a mask. Then, when forming the drain offset region 18 which is a low concentration layer, it is necessary to leave the middle concentration layer 19 adjacent to the gate electrode 14. For this reason, a gate sidewall 17 is formed on the side surface of the gate electrode 14 to introduce impurities of a second conductivity type having a polarity different from that of the first conductivity type.
8 is created.

The drain region 22 and the source region 21, which are high-concentration layers, are necessary for making contact with the wiring. However, it cannot be formed in the drain offset region 18 and the middle concentration layer 19. For this reason, the portions that cannot be formed are masked with the resist 20 and the impurity is introduced at a high concentration to form the drain region 22 and the source region 21 which are high concentration layers.

In the present method, the introduction of impurities
The method of forming the resist mask may be modified. That is, in order to introduce an impurity only into a necessary portion of the drain offset region 18 of the low concentration layer, a part of the other source region 21 and the drain region 22 is formed by using a resist, a gate electrode, and a gate side wall. Conductive impurities can also be implanted.

Next, another manufacturing method of the first embodiment will be described with reference to FIG. FIG. 2 shows a cross-sectional structure of the high breakdown voltage MOSFET in each part of the manufacturing process. As shown in FIG. 3A, the impurity concentration is 1
An element isolation film (not shown) is formed on a p-type silicon substrate 11 of about × 10 ¹⁴ cm ⁻³ , and a well 12 is formed. Then, channel ions are implanted into the upper surface of the p-type silicon substrate 11.

Next, a gate insulating film 13 having a thickness of 5 nm is formed on the upper surface of the silicon substrate 11 by an oxidation process. Then, on the upper surface of the gate insulating film 13, a polysilicon film is formed with a thickness of 200 nm. Next, a resist is applied to the upper surface of the polysilicon film, and the polysilicon film is etched based on the pattern of the resist remaining after the exposure step and the development step, thereby forming the gate electrode 14.

Then, using this gate electrode 14 as a mask, a dose of 5 × 10 ¹² at an acceleration energy of 20 keV.
Arsenic ions of cm ⁻² are implanted into the upper surface of the p-type silicon substrate 11. Thereby, the low concentration layer 32 is formed on the upper surface of the p-type silicon substrate 11.

Next, as shown in FIG. 3 (b), 0.4 mm from the end of the gate electrode 14 to the drain formation region D side.
A resist 33 is formed between a position separated in the plane direction of μm and a position separated in the plane direction by 10 nm from the end of the gate electrode 14. Then, the resist 33 and the gate electrode 14
Is used as a mask, arsenic ions are deposited on the upper surface of the p-type silicon substrate 11 at an acceleration energy of 20 keV to 2 × 10 ¹⁴ cm
It is implanted with a dose of ^-2 . As a result, the low-concentration layer 32 in the portion where the ion implantation has been performed becomes a medium-concentration layer 34 and a medium-concentration layer 35.

Next, as shown in FIG. 3C, a resist 36 is formed on the low concentration layer 32 from the upper part of the gate electrode 14 to the drain formation region D starting from the upper part of the gate electrode 14.
Is formed up to the position of 0.4 μm. Using the resist 36 as a mask, the drain region 38 and the source region 37, which are high-concentration impurity layers, are formed by implanting arsenic ions with an acceleration energy of 50 keV and a dose of 5 × 10 ¹⁵ cm ⁻² .

In the method described above, the depth of the source region 21 is about 100 nm and is deep. Here, in order to suppress the short channel effect, the source region 37 is formed.
If it is desired to reduce the depth of the diffusion layer in the vicinity of the gate electrode 14 of FIG.
After forming the second gate side wall of m on the outer surface of the gate side wall 17, the above-described processing of FIG.

As described above, in the structure of the high-breakdown-voltage MOSFET according to the first embodiment, a medium-concentration impurity layer is formed between the drain offset region and the gate electrode. Thus, when the drain voltage is low, the amount of depletion at the interface between the drain offset region and the gate electrode is small. FIG. 4 compares the potential applied to the drain offset region from the end of the gate electrode on the drain region side to the drain region between the present invention and the conventional example.

As shown in FIG. 4A, when the drain voltage is low, the drain voltage is applied to the boundary between the gate electrode and the drain offset region because the depletion amount of the middle concentration layer is small in the present invention. On the other hand, in the conventional example, since the depletion of the low-concentration offset region progresses, the drain voltage is applied only to a position slightly away from the boundary between the gate electrode and the drain offset region. For this reason,
The voltage on the channel is higher in the present invention and therefore the amount of current also increases.

Next, as shown in FIG. 4B, when the drain voltage is high, by setting the length of the impurity layer of the middle concentration layer to an appropriate value, the middle concentration layer is depleted. . Therefore, in the case of the present invention and the conventional example as well, the offset region (drain offset region) is almost completely depleted, so that the values of the potential distribution between the drain and the offset region have similar values.

As a result, as shown in FIG. 5, it is understood that the drain current / drain voltage characteristic of the high breakdown voltage MOSFET according to the present invention is improved in the low drain voltage region as compared with the conventional example. Also, the drain current in the high drain voltage region is determined by the high breakdown voltage MOSFET of the present invention.
And the conventional high breakdown voltage MOSFET are almost equal. Furthermore, since the potential distribution in the drain offset region in the high voltage region where the breakdown occurs is equal, the drain breakdown voltage of the high breakdown voltage MOSFET of the present invention is almost equal to that of the conventional high breakdown voltage MOSFET.

As described above, one embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and a design change or the like may be made without departing from the gist of the present invention. The present invention is also included in the present invention. For example, FIG. 6 shows a high breakdown voltage MOSFET according to a second embodiment of the present invention. FIG. 6 is a vertical cross-sectional view showing the structure of a high breakdown voltage MOSFET in which a middle concentration layer is provided not only on the drain region side but also on the source region side.

In this figure, reference numeral 1 denotes a silicon substrate on which a gate insulating film 2 having a thickness of 5 nm is formed. On the upper surface of the gate insulating film 2, a thickness of 200 n
A gate electrode having a length of 0.18 μm and a length of 0.18 μm is formed.

Reference numeral 5 denotes an offset region having an arsenic dose of 5 × 10 ¹² cm ⁻² , and is formed on the upper surface of the silicon substrate 1 so as to have a length of 0.4 μm in a plane direction from the gate electrode 3.
Reference numeral 4 denotes a medium-concentration region of an arsenic dose of 2 × 10 ¹⁴ cm ⁻² , which is formed on the upper surface of the silicon substrate 1 with a length of 10 nm interposed between the gate insulating film 2 and the offset region 5. . Reference numeral 6 denotes a drain region, which is formed adjacent to the offset region 5 on the upper surface of the silicon substrate 1. 7
Is a source region, which is formed near the gate insulating film 2 on the upper surface of the silicon substrate 1. Reference numeral 9 denotes a middle concentration region, which is formed between the source region 7 and the other end of the gate electrode 14.

Although not shown, wells, element isolation films, and channels are formed as needed.

Next, a manufacturing method of an application example of the high breakdown voltage MOSFET according to the above-described embodiment will be described with reference to FIG. FIG. 7 shows a high breakdown voltage MOSF in each part of the manufacturing process.
2 shows a cross-sectional structure of ET. As shown in FIG. 7A, the impurity concentration is about 1 × 10 ¹⁴ cm ^−3.
An element isolation film (not shown) is formed on the mold silicon substrate 11, and a well 12 is formed. Then, channel ions are implanted into the upper surface of the p-type silicon substrate 11.

Next, a gate insulating film 13 having a thickness of 5 nm is formed on the upper surface of the silicon substrate 11 by an oxidation process. Then, on the upper surface of the gate insulating film 13, a polysilicon film is formed with a thickness of 200 nm. Next, a resist is applied to the upper surface of the polysilicon film, and the polysilicon film is etched based on the pattern of the resist remaining after the exposure step and the development step, thereby forming the gate electrode 14.

Then, using this gate electrode 14 as a mask, a dose of 5 × 10 ¹² at an acceleration energy of 20 keV.
Arsenic ions of cm ⁻² are implanted into the upper surface of the p-type silicon substrate 11. Thus, a low concentration layer 31 and a low concentration layer 32 are formed on the upper surface of the p-type silicon substrate 11.

Next, as shown in FIG. 7B, a pattern of a resist 33 is formed on the entire drain formation region D from above the gate electrode 14. And the gate electrode 14
Using resist 33 as a mask, arsenic ions are implanted into the upper surface of p-type silicon substrate 11 with an acceleration energy of 20 keV and a dose of 2 × 10 ¹⁴ cm ⁻² . As a result, the low-concentration region 31 into which the ion implantation has been performed becomes a medium-concentration region 34.

Next, as shown in FIG.
A first side wall 40 having a thickness of 10 nm is formed on the side surface of the gate electrode 14.
Is done. The outer surface of the first side wall 40 has 100
A second sidewall 41 having a thickness of nm is formed. In addition,
Starting from the gate electrode 14 on the side of the rain formation region D,
The position in the plane direction of 0.4 μm from the end of the gate electrode 14
The resist 42 is formed up to this point. And this resist
42, gate electrode 14, first side wall 40 and second side
Using the wall 41 as a mask, a drain which is a high-concentration impurity layer
The region 44 and the source region 43 have an acceleration energy of 50 keV.
5 × 10 with lugi ^Fifteencm^-2Dose of arsenic ion implantation
Formed by Thereby, the remaining of the low concentration layer 32
The portion becomes the drain offset region 45.

Next, as shown in FIG. 7D, the first side wall 40 is etched to form a cavity 46.
Then, a resist 47 is formed from above the second side wall 41 on the drain formation region D side to the drain region 44. Then, using the gate electrode 14, the second side wall 41, and the resist 47 as a mask, 2 × 1 at an acceleration energy of 20 keV.
Arsenic ions at a dose of 0 ¹⁴ cm ^-2 are implanted, and a middle concentration layer 48 and a middle concentration layer 49 are formed.

In this manufacturing method, it is necessary to introduce impurities three times in fabricating the high breakdown voltage MOSTFT of the first embodiment. First, the middle concentration layer 19 is formed by implanting a first conductivity type impurity using the gate electrode 14 as a mask. Then, when forming the drain offset region 18 which is a low concentration layer, it is necessary to leave the middle concentration layer 19 adjacent to the gate electrode 14. For this reason, a gate sidewall 17 is formed on the side surface of the gate electrode 14 to introduce impurities of a second conductivity type having a polarity different from that of the first conductivity type.
8 is created.

The drain region 22 and the source region 21, which are high-concentration layers, are necessary for making contact with the wiring. However, it cannot be formed in the drain offset region 18 and the middle concentration layer 19. For this reason, the portions that cannot be formed are masked with the resist 20 and the impurity is introduced at a high concentration to form the drain region 22 and the source region 21 which are high concentration layers.

In this method, the impurity introduction is
The method of forming the resist mask may be modified. That is, in order to introduce an impurity only into a necessary portion of the drain offset region 18 of the low concentration layer, a part of the other source region 21 and the drain region 22 is formed by using a resist, a gate electrode, and a gate side wall. Conductive impurities can also be implanted.

In this manufacturing method, the cavities 46 are used for impurity introduction in order to form the middle concentration layers 48 and 49. The cavity 46 is formed by continuously forming the first side wall 40 and the second side wall 41 and removing the first side wall by etching. Therefore, the first side wall 4
By controlling the thickness of 0, the widths of the middle concentration layers 48 and 49 are controlled.

As described above, in the second embodiment, the intermediate concentration layer 49 is also interposed between the source region 43 and the end of the gate electrode 14. This is MOSF
In order to control the short channel effect of ET (the effect of lowering the threshold voltage of the transistor as the gate length is reduced and the controllability of the threshold voltage becomes unstable), the source region 4
3 and the depth of the diffusion layer of the drain region 44 must be reduced.

Therefore, a part of the source region adjacent to the gate electrode 14 where the channel is to be formed is formed as the middle concentration layer 49. For this reason, the high-breakdown-voltage MOSFET according to the second embodiment has a structure in which the short-channel effect is further suppressed in addition to the structure on the drain formation region D side where the withstand voltage is increased.

[0052]

According to the structure of the high-breakdown-voltage MOSFET of the present invention, the low-concentration layer has a low breakdown voltage, the drain breakdown voltage is kept high, the middle-concentration layer has a small depletion amount. Since the drain voltage is applied to the boundary between the gate electrode and the drain offset region, a sufficient current flows through the channel, and the amount of drain current at a low drain voltage is increased to a value equivalent to that of a normal MOSFET.

[Brief description of the drawings]

FIG. 1 is a high breakdown voltage MOSFE according to an embodiment of the present invention;
It is sectional drawing which shows the structure of T.

FIG. 2 is a high breakdown voltage MOSFE according to an embodiment of the present invention;
It is a figure explaining the manufacturing process of T.

FIG. 3 is a high voltage MOSFE according to an embodiment of the present invention;
It is a figure explaining other manufacturing processes of T.

FIG. 4 is a diagram illustrating a relationship between a potential and a distance applied to a drain offset region from an end of the gate electrode on the drain region side to a drain region.

FIG. 5 is a diagram showing drain current / drain voltage characteristics of a MOSFET.

FIG. 6 shows a high voltage MOS transistor according to a second embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a structure of an FET.

FIG. 7 shows a high breakdown voltage MOS according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a manufacturing process of the FET.

FIG. 8 is a cross-sectional view showing a structure of a conventional high-breakdown-voltage MOSFET.

FIG. 9 is a cross-sectional view showing the structure of another conventional high-breakdown-voltage MOSFET.

[Explanation of symbols]

 1, 11 p-type silicon substrate (silicon substrate) 2, 13 gate insulating film 3, 14 gate electrode 4, 9, 19, 34, 35 medium concentration region (medium concentration layer) 5 offset region 6, 22, 38, 44 drain Region (drain) 7, 21, 37, 43 Source region 8 Very low concentration region 12 Well 18, 39, 45 Drain offset region 20, 33, 36, 42, 47 Resist 31, 32 Low concentration layer 40 First side wall 41 Second sidewall D Drain formation region

Claims (5)

[Claims] A gate electrode provided on the substrate via a gate insulating film; a source region provided at one end of the gate insulating film; and a first electrode provided at the other end of the gate oxide film. A drain region formed of the same conductivity type impurity as the first diffusion layer at an interval in the planar direction of the substrate between the diffusion layer and the first diffusion layer; and A second diffusion layer formed of the same conductivity type impurity as the first diffusion layer interposed between the first diffusion layer and the drain region, wherein the impurity concentration of the second diffusion layer is the drain region. Wherein the impurity concentration of the first diffusion layer is a value between the impurity concentration of the second diffusion layer and the impurity concentration of the drain region.
ET. 2. The high breakdown voltage MOSFET according to claim 1, wherein said source region is between said gate oxide film and a first source diffusion layer formed apart from said gate oxide film on a plane of said substrate. And a second source diffusion layer whose depth is smaller than that of the first source diffusion layer interposed therebetween. 3. A gate electrode forming step of forming a gate electrode on the upper surface of the substrate, and a first conductive impurity introducing step of introducing a first conductive impurity into the upper portion of the substrate using the gate electrode as a mask. An insulating film forming step of forming a side surface insulating film on a side surface of the gate electrode; and using the gate electrode and the side surface insulating film as a mask, a conductive type opposite to the first conductive type impurity. A second conductive impurity introducing step of introducing a second conductive impurity, and a resist forming step of forming a resist from a top surface of the gate electrode to a position where a drain region is formed in the substrate plane direction. Re-introducing the first conductive impurity again using the resist as a mask. 4. A gate electrode forming step of forming a gate electrode on the upper surface of the substrate; a first introducing step of introducing a first conductive impurity into the upper portion of the substrate using the gate electrode as a mask; A first resist forming step of forming a first resist in a region between a position distant from the gate electrode by a predetermined distance and a position where a drain region is formed in a plane direction; A second introduction step of introducing the first conductive impurity, and a second resist formation step of forming a second resist in a region from the upper surface of the gate electrode to a position where the drain region is formed in the substrate plane direction. And a third introducing step of introducing the first conductive impurity using the second resist as a mask. 5. A gate electrode forming step of forming a gate electrode on an upper surface of a substrate; a first introducing step of introducing a first conductive impurity into an upper portion of the substrate using the gate electrode as a mask; A first resist forming step of forming a first resist in a region from a top surface of the gate electrode to a position including a drain region forming portion in a plane direction, and using the first resist as a mask, A second introduction step of introducing an impurity, a first insulation film formation step of forming a first insulation film on the side surface of the gate electrode, and a second insulation film is formed on the side surface of the first insulation film. Second
Forming a second resist between the upper surface of the gate electrode and the position of forming the drain region in the plane direction of the substrate; and forming the second resist as a mask using the second resist as a mask. A third introduction step of introducing a first conductive impurity, a removal step of removing the first insulation film by etching, and a step of removing the first insulation film from the upper surface of the second insulation film on the drain region formation side in the substrate plane direction. A third resist forming step of forming a third resist before the position where the drain region is formed; and a fourth introducing step of introducing the first conductive impurity using the third resist as a mask. A method for manufacturing a MOSFET, comprising: