JPH0290567A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a fine MIS transistor which is high in breakdown strength, Gm characteristic, and punch-through resistance by a method wherein the base of a gate electrode is provided inside a substrate, a low concentration source.drain is provided so as to prevent a gate electrode from overlapping directly with a high concentrated source.drain. CONSTITUTION:A gate electrode 5 is formed inside the groove provided to a Si substrate 1 doped with P-type or n-type impurity. A low concentration source.drain 2 is provided to the sides of the groove sandwiching the groove in between them, a high concentration source.drain 7 is formed on both the sides of the low concentration source.drain 2s being in contact with them, and a source.drain region is doped with impurity whose conductivity type is opposite to that of the substrate 1. And, the gate electrode 5 and the substrate 1 are isolated from each other by a gate insulating layer 3. A channel injecting layer 4 controlling Vth (threshold voltage) is formed on the base of the groove in which the gate electrode has been formed. An insulating film 6 is formed on the side wall of the gate electrode 5 to enable an ion-implanting end at the formation of the high concentration source.drain 7 to be separate from the gate electrode 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is an MIS (Metal Insulator Semiconductor) in which the gate length is miniaturized to 0.5 μm.
Sea + 1 conductor)
The present invention relates to suppression of punch-through in transistors, a highly reliable semiconductor device, and a method for lateral advancement.

[Conventional technology]

Conventional techniques for realizing punch-through resistance in micro-engineered S transistors include a method of increasing the substrate concentration at the punch-through current path inside the substrate, a technique of increasing the substrate concentration at each source/drain end, or a technique of increasing the substrate concentration at the source/drain end. A technique of forming a shallow drain diffusion layer has been mainly used. Groove MIS structure DSC (Drain Separated) ROM Channel Implanted Region: Dra
inSeparated from Channel
Implanted region) is also punch-through resistant and high voltage resistant as a device.
6 pages (IEEE TranS, Elactron Dev
ices, vol HD-30, pp.

681-686.1983).

In addition, GOLD (gate/
Drain overlap structure Gate-drainO
Verlapped Device) was published in IE DM Technical Digest, (1987)
Pages 38 to 41 (IDEM Technical
Digest.

1987, p. 38-41).

[Problem to be solved by the invention]

Among the above conventional techniques, the method of increasing the substrate concentration is
The extension of the depletion layer from the drain side was not completely suppressed, and the limit for suppressing punch-through was approximately 0.3 μm in channel length.

Furthermore, when the substrate concentration is increased to enhance the punch-through suppressing effect, the electric field at the junction between the source/drain and the substrate becomes stronger, resulting in a problem of lower reliability.

The method of reducing the junction depth has a problem in that the sheet resistance of the source/drain increases and the transfer conductance Gm decreases.

Therefore, there is a trench gate transistor DSG that effectively reduces the depth of opposing source/drain portions without reducing the junction depth of the source/drain. However, in conventional DSCs, band-to-band tunnel leakage current occurs due to the gate electric field at a portion where the highly doped drain and gate electrode overlap.

It is an object of the present invention to suppress punch-through without lowering the junction breakdown voltage between the source/drain and the substrate and without reducing the diffusion depth of the source/drain, and in addition, - The object is to realize the GOLD structure in which the low concentration drain and source overlap without overlapping the drain region.

[Means to solve the problem]

In order to achieve the above purpose, a groove-shaped gate electrode is provided between the ordinary low concentration source and drain with a diffusion depth of about 0.2 μm, and the bottom surface of the groove of the gate electrode is deeper than the depth of the low concentration source/drain diffusion layer. I tried to get it to a deep position. Furthermore, a GOLD structure is adopted in which lightly doped source/drain regions are provided so that the gate electrode and the highly doped source/drain regions do not directly overlap.

[Effect]

The groove-shaped gate electrode provided at a position deeper than the depth of the low concentration source/drain diffusion layer has the function of suppressing punch-through, which is a problem in fine M I S +- transistors. Moreover, bunch-through can be prevented without scaling down the depth of the low-concentration source/drain diffusion layer, so the low-1 degree source/drain depth can be kept constant, thereby suppressing the increase in resistance due to shallower junctions. .

Further, since the trench type goo 1 to electrode overlaps the low concentration source/train without directly overlapping the high concentration source/drain, there is also an effect of suppressing drain leakage development induced by the gate electric field. Note that the high breakdown voltage and high Gm characteristics, which are the characteristics of the GOLD structure, can also be achieved.

〔Example〕

Example 1 An embodiment of the present invention will be described below with reference to FIG.

FIG. 1 shows the active area of a MIS transistor.

The device isolation regions that separate the active regions are omitted from FIG.

The electrode 5 to gate 1 of the MIS transistor is P type or n
It is formed in a groove of a Si substrate 1 doped with type impurities. There are low concentration sources and drains 2 on both sides of the groove, and high concentration sources and drains 7 on both sides in contact with the low concentration sources and drains 2.

The source/drain regions are doped with impurities of a conductivity type opposite to that of the Si substrate 1. Gate electrode 5 and Si substrate 1 are separated by gate insulating film 3. A channel implantation layer 4 for Vth (threshold voltage) control is provided at the bottom of the groove of the gate electrode 5.
form. An insulator I (I6) is formed on the sidewalls of the electrodes 1 to 5 so that the end of the implanted indium ion implant in the highly doped source/drain diffusion layer is separated from the end of the gate electrode 5.

In this embodiment, the gate electrode 5 is formed in the groove of the Si substrate 1, and the low concentration source/drain 2 is provided shallower than the bottom of the groove, thereby suppressing bunch-through between the source and drain.

Furthermore, since the gate electrode 5 does not directly overlap the highly doped source/drain 7, the interband tunnel leaf phenomenon at the drain junction in the gate overlap region can be suppressed.

On the other hand, since the gate electrode 5 overlaps the low concentration source/drain 2, the resistance of the region 2 can be reduced, and the drain electric field can be relaxed due to the gate/drain overlap effect (GOL D effect).

A channel due to the gate electric field is formed in the Si substrate 1 on the side of the trench, and current flows along the channel from the train to the source. In this embodiment, the threshold voltage of the MIS transistor is controlled by the frequency of the channel implantation layer 4.

According to this example, the gate length is 0.3 μm or less and the voltage is high.
A miniature MIS transistor with high Gm characteristics and punch-through resistance can be realized.

Example 2 FIG. 2 shows a method of manufacturing the device of the embodiment shown in FIG.

First, as shown in Figure (a), an oxide film 21 is formed on a Si substrate 1. The film thickness was 200 nm. On the upper surface of the oxide film 21, a polycrystalline silicon film 22 with a thickness of 1100 nm was deposited, and an oxide film 23 was deposited thereon with a thickness of 1100 nm. Furthermore, patterning is performed using the photoresist film 24, and the films 23, 22, 21 are processed using an anisotropic dry etching technique.

As shown in FIG. 2B, an oxide film 25 was then deposited on the entire surface, and a diffusion layer 2 used as a low concentration source/drain was formed in the opening.

In FIG. 4(Q), after depositing the oxide film 26 on the entire surface, the oxide film 26 is etched back by an anisotropic dry etching technique so that the oxide film 26 remains only on the side walls of the opening. Next, using the sidewall oxide film 26 as a mask, the Si substrate 1 is anisotropically etched to form a groove. After forming the trench, the trench sidewalls are oxidized to form an oxide film 27. In this state, channel ion implantation layer 4 is formed.

FIG. 3(d) shows a state in which after the sidewall oxide film 26 has been removed by isotropic etching, the trench sidewall is oxidized again to form the oxide film 3. Incidentally, when removing the sidewall oxide [26], the oxide films 23, 25, and 27 are also etched at the same time. When forming the oxide 1113 for this purpose, the oxide film 28 can also be formed at the same time.

FIG. 5(e) shows a state in which the opening formed in FIG. 4(d) is filled with a polycrystalline silicon film 29. First, after the formation shown in FIG. 3(d), a polycrystalline silicon film 29 is deposited thickly and etched back to fill only the opening portion with the polycrystalline silicon film.

After that, the oxide film 28 is removed and the polycrystalline silicon film 2 is removed again.
9. Perform etchback of 22. As the oxide film 21 appears on the surface by etching back the film 22, the film 2
By removing the polycrystalline silicon film 29 by isotropic etching, only the polycrystalline silicon film 29 is left, and the gate electrode 5 is formed. At this stage, an oxide film 6 is formed on the side walls of the gate electrode 5.
Using the mask as a mask, a highly doped source/drain 7 is formed to obtain the result shown in FIG.

According to the manufacturing method of this embodiment, it is possible to independently control the groove width and the length of the overhanging eaves of the single-shaped gate electrode.

Embodiment 3 FIG. 3 shows an embodiment in which the channel ion implantation layer 4 is localized in the central portion 40 of the gate electrode groove in the embodiment of FIG.

According to this embodiment, the threshold voltage can be set in the region that is most sensitive to threshold voltage control, and since no channel ion implantation layer is formed in other channel parts, there is an effect of preventing current drop due to impurity scattering. .

Embodiment 4 FIG. 4 shows an intermediate stage of the manufacturing process for realizing the embodiment of FIG. 3. At the stage shown in FIG. 2(Q), an insulating film 41 is formed, and channel ion implantation is performed using the film 41 as a mask to form an implantation layer 40.

Embodiment 5 FIG. 5 shows an embodiment in which the depth of the gate electrode groove is made shallower in the embodiment of FIG. 1.

According to this embodiment, the effect of suppressing the short channel effect of the embodiment of FIG. 1 can be realized, and the effective channel length can be shortened.

Embodiment 6 FIG. 6 is an embodiment in which the depth of the gate electrode groove is made shallower in the embodiment of FIG. 3. This embodiment can also achieve the effects of the embodiments shown in FIGS. 3 and 5.

Embodiment 7 FIG. 7 shows an embodiment in which an oxide film 70 is provided above the gate electrode 5 in the embodiment shown in FIG. This example is shown in Figure 2 (
It can be formed by oxidizing the upper surface of the polycrystalline silicon film 29 in step e).

According to this embodiment, insulation between the gate electrode 5 and the source/drain electrode 71 can be realized in a self-aligned manner.

Embodiment 8 In FIG. 8, a low concentration source/drain 2 is provided between a high concentration source/drain 7 and a goo 1-electrode 5, so that the gate electrode 5 can directly overlap the high concentration source/drain 7. This is an example in which there is no such problem.

According to this embodiment, the electric field concentration between the gate electrode 5 and the highly doped source/drain 7 can be alleviated.

The drain leak phenomenon at the end portions of the highly doped source/drain 7 and the overlap portion with the gate electrode 5 can be suppressed.

Embodiment 9 FIG. 9 shows a cross-sectional view in the channel width direction at the center of the gate. Areas 90 and 91 are isolation areas. Isolation regions 90 and 91 have a U-shaped groove isolation structure, and are composed of an oxide film 90 and a buried film 91. As shown in FIG. 9, the sidewall oxide film in the channel width direction of the gate electrode 5 formed in the substrate groove is in contact with the isolation oxide film 90. Therefore, leakage current flowing between the source and drain via the trench sidewall of the gate electrode 5 without passing through the channel implantation layer 4 can be removed.

Embodiment 10 FIG. 10 shows an embodiment in which the gate electrode is formed of conductive films 100 and 101 instead of the polycrystalline silicon film 5.

According to this embodiment, the resistance of the gate electrode can be reduced. Further, since the work function of the electrode 100 that overlaps the low concentration source/drain 2 can be changed, the degree of freedom in designing the overlap effect increases.

Embodiment 11 FIG. 11 shows the embodiment of FIG. 7 with low concentration source/drain 2.
This is an example in which a thick oxide film 110 is formed as the gate oxide film only on the upper part.

According to this embodiment, the overlap capacitance between the gate electrode 5 and the source/drain can be reduced, and the breakdown voltage of the gate insulating film can be improved even at the end of the electrode.

Embodiment 12 FIG. 12 shows the embodiment of FIG. 7 with low concentration source/drain 2.
This is an example in which the gate groove is also formed on the side wall of the gate groove. The formation of the low concentration source/drain 2 on the side wall of the gate trench is achieved by obliquely performing ion implantation after the trench is formed.

According to this embodiment, the effect of shortening the channel length is produced.

Embodiment 13 FIG. 13 shows the channel ion implantation layer 4 in the embodiment of FIG.
Instead of forming only 0, new channel ion implantation M
This is an example in which 1ll is provided. The channel ion implantation layer 111 is formed by performing oblique ion implantation on the groove side surface after forming the layer 4o.

In this embodiment, a layer 4o formed to act as a punch-through stopper and a layer M formed for threshold voltage control.
It is possible to separate functions from llll.

Embodiment 14 FIG. 14 shows an embodiment in which the gate electrode 5o is formed in the embodiment shown in FIG. 7 except for the part of the gate electrode 5 that extends in a square shape. This example is formed by the manufacturing process shown in Example 15.

Example J5 FIGS. 15(a) and 15(b) show intermediate stages of the manufacturing process. First, Figure (a) shows the steps up to forming the gate electrode 50 in a buried manner. Note that the element isolation region is omitted in FIG. 15. After forming low concentration source/drain diffusions M2 on the entire surface of the active core formation region of the Si substrate 1, a polycrystalline silicon film 150 and an oxide film 151 are subsequently deposited. Next, although not shown in the figure, the resist film is patterned, and the oxide film 151 is patterned using the resist film as a mask. Polycrystalline silicon film 150 and Si substrate 1 are processed using anisotropic etching technology. After removing the resist film, the inner wall of the Si trench is oxidized to form an oxide film 3, and then a channel ion implantation layer 4 is formed. Thereafter, polycrystalline silicon is deposited on the entire surface and filled into the Si trenches. After polycrystalline silicon other than the Si trench is removed by an etch-back technique, the top surface of the trench is oxidized to form an oxide film 70. In this way, the gate electrode 50 is formed so as to fill the Si trench.

After that, as shown in FIG. 2(b), the oxide film 151 is removed,
Subsequently, polycrystalline silicon film 150 is removed. A spacer oxide film 6 is formed on the sidewall of the gate salt t450 protruding from the silicon substrate. The oxide film 6 is formed by etching back an oxide film over the entire surface using an anisotropic etching technique using a deposition machine.

High concentration source/drain 7 is formed in a self-aligned manner using oxide film 6 as a mask.

Note that the step of forming source/drain electrodes is omitted.

Embodiment 16 FIG. 16 shows an embodiment in which the gate electrode is formed in the groove and overlaps the low concentration source/drain 2. In FIG.

This embodiment also provides the same effects as the other embodiments.

FIG. 17 is a plan layout diagram of the embodiment shown in FIG. 171 shows a U-groove isolation pattern.

The area inside 171 becomes the active area. 172 indicates a groove-type gate electrode pattern.

Reference numeral 173 denotes a wiring connection pattern provided in the electrode wiring portion of the trench gate pattern shown by 172. 174 is a pattern of holes for electrode wiring contacts, and 6175 is a metal electrode wiring pattern.

It is clear that this embodiment can be applied to embodiments other than those shown in FIG.

The above-mentioned embodiments have been explained using a Si semiconductor as an example, but semiconductors other than Si, such as GaA
It is obvious that this method may be implemented in the case of s-based semiconductors.

〔Effect of the invention〕

According to the present invention, since the gate electrode can be provided at a position deeper than the depth of the low concentration source/drain diffusion layer, the punch-through phenomenon caused by the expansion of the drain depletion layer can be suppressed. Therefore, according to the present invention, an extremely fine MOS transistor with a gate length of up to 0.1 μm can be realized.

Furthermore, since the gate electrode does not directly overlap the highly doped source/drain, it is possible to suppress the band-to-band tunnel league phenomenon caused by the gate in the train portion. Therefore, the restriction on reducing the gate oxide film thickness due to the band-to-band tunnel leak phenomenon can be removed, and an oxide film with a thickness of 10 nm or more can be applied.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and FIG.
15 are cross-sectional views showing the manufacturing process of a semiconductor device according to one embodiment of the present invention, and FIGS. 3 to 14 and FIG. FIG. 17 is a plan view of the semiconductor element of FIG. 1. 2...Low concentration source/drain, 3...Gate oxide film, 4.40,111...Channel ion implantation layer, 5.50.100.101...Gate electrode, 7...
・High concentration source/drain No. 1I21 No. 2 Mouth Chrysalis 2 (2) (OL) No. 2 Σ (〒) No. 1 Sword No. 1 Chiku No.

Claims (1)

[Claims] 1. In an MIS semiconductor device consisting of a gate electrode, a gate insulating film, and a source/drain, the bottom of the gate electrode is provided inside the substrate, and the gate electrode and the highly doped source/drain are directly connected to each other. A semiconductor device characterized in that a low concentration source and drain are provided so that they do not overlap. 2. In the semiconductor device according to claim 1,
A semiconductor device characterized in that a gate electrode is provided in a T-shape so that the gate electrode overlaps a low concentration source/drain. 3. A semiconductor device according to claims 1 and 2, characterized in that a channel ion implantation layer is provided only at the bottom of the gate electrode located inside the substrate. 4. A semiconductor device according to claim 2, characterized in that the highly doped source/drain is provided in a T-shape deeper than the lower surface of the gate electrode extending in the direction of the source/drain. 5. A semiconductor device according to claims 1 and 2, characterized in that the bottom surface of the gate electrode is provided deeper than the depth of the source/drain junction. 6. In the semiconductor device according to claim 3,
A semiconductor device characterized in that a channel ion implantation layer is provided only in the center of a channel. 7. A semiconductor device according to claims 1 and 2, characterized in that an insulating film is provided on the upper surface of the gate electrode and self-aligned source/drain electrodes are provided. 8. A semiconductor device according to claims 1 and 2, characterized in that the gate electrode is formed of a composite film of two or more different conductive films. 9. In the semiconductor device according to claim 2,
A semiconductor device characterized in that a gate oxide film under a T-shaped gate electrode extending in a source/drain direction is thicker than other parts of the gate oxide film. 10. A semiconductor device according to claims 1 and 2, characterized in that a U-groove element isolation structure is formed deeper than the gate. 11. The bottom of the gate electrode is provided inside the substrate, and a low concentration source/drain is provided so that the gate electrode and the high concentration source/drain do not overlap directly, and if necessary, the gate electrode is connected to the low concentration source/drain. - A method for manufacturing a semiconductor device in which a gate electrode is provided in a T-shape so as to overlap a drain, comprising the step of forming a gate electrode and a substrate groove in which the gate electrode is embedded in a self-aligned manner. Method of manufacturing the device.