KR20010009679A - Fabricating method of semiconductor device - Google Patents
Fabricating method of semiconductor device Download PDFInfo
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- KR20010009679A KR20010009679A KR1019990028185A KR19990028185A KR20010009679A KR 20010009679 A KR20010009679 A KR 20010009679A KR 1019990028185 A KR1019990028185 A KR 1019990028185A KR 19990028185 A KR19990028185 A KR 19990028185A KR 20010009679 A KR20010009679 A KR 20010009679A
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- oxide film
- gate
- oxide layer
- semiconductor substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 40
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims description 16
- 239000010410 layer Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- 230000002265 prevention Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 2
- 238000002513 implantation Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000005676 thermoelectric effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
- H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 메탈 게이트 트랜지스터(metal gate transistor)의 단-채널(short-channel) 게이트 형성을 용이하게 하고, 선택적인 불순물 이온주입을 통해 카운터 도핑(counter doping)을 방지함과 아울러 트랜지스터 특성의 미세조정을 개선하며, 펀치-쓰루(punch-through)를 억제함과 아울러 게이트와 드레인의 겹쳐지는 영역을 최적화하고, 게이트산화막의 두께를 게이트의 가장자리(edge)에서 상대적으로 두껍게 형성하여 게이트와 드레인의 겹쳐지는 영역의 커패시턴스(capacitance)를 감소시키기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, facilitates the formation of short-channel gates of metal gate transistors, and provides counter doping through selective impurity ion implantation. To improve the fine tuning of transistor characteristics, to suppress punch-through, to optimize the overlapping area of the gate and drain, and to adjust the thickness of the gate oxide film at the edge of the gate. The present invention relates to a method of manufacturing a semiconductor device, which is formed relatively thick so as to be suitable for reducing capacitance of overlapping regions of a gate and a drain.
일반적인 반도체소자의 제조방법을 첨부한 도1의 단면도를 참조하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 1 attached to a method for manufacturing a general semiconductor device in detail as follows.
먼저, 반도체기판(1) 상에 산화공정을 통해 게이트산화막(2)을 형성한다.First, the gate oxide film 2 is formed on the semiconductor substrate 1 through an oxidation process.
그리고, 상기 게이트산화막(2)의 상부에 도핑된 폴리실리콘(3), WSix막(4) 및 캡 질화막(5)을 순차적으로 증착한다.The doped polysilicon 3, the WSix film 4 and the cap nitride film 5 are sequentially deposited on the gate oxide film 2.
그리고, 상기 캡 질화막(5) 상에 사진식각공정을 적용하여 캡 질화막(5), WSix막(4) 및 도핑된 폴리실리콘(3)을 식각함으로써, 게이트산화막(2)의 상부 일정한 영역에 게이트를 형성한다.Then, the cap nitride film 5, the WSix film 4 and the doped polysilicon 3 are etched by applying a photolithography process on the cap nitride film 5, so that a gate is formed on the upper portion of the gate oxide film 2. To form.
그리고, 상기 게이트를 마스크로 적용하여 게이트산화막(2)을 통해 반도체기판(1) 내에 저농도 불순물이온을 주입하여 저농도영역(6)을 형성한다.The low concentration region 6 is formed by injecting low concentration impurity ions into the semiconductor substrate 1 through the gate oxide film 2 by applying the gate as a mask.
그리고, 상기 저농도영역(6)이 형성된 구조물의 상부전면에 질화막을 증착하고, 선택적으로 식각하여 상기 게이트의 측면에 질화막 측벽(7)을 형성한다.A nitride film is deposited on the upper surface of the structure in which the low concentration region 6 is formed, and selectively etched to form a nitride film sidewall 7 on the side of the gate.
그리고, 상기 게이트 및 질화막 측벽(7)을 마스크로 적용하여 게이트산화막(2)을 통해 반도체기판(1) 내에 고농도 불순물이온을 주입하여 소스/드레인영역(8)을 형성한다.The gate and nitride sidewalls 7 are applied as a mask to implant a high concentration of impurity ions into the semiconductor substrate 1 through the gate oxide layer 2 to form a source / drain region 8.
여기서, 상기 게이트 하부의 반도체기판(1) 내에 소스/드레인영역(8)을 연결하는 도면상의 미설명 부호 '9'는 채널영역을 나타낸다.Here, reference numeral '9' in the drawing connecting the source / drain region 8 to the semiconductor substrate 1 under the gate represents a channel region.
상기한 바와같이 제조된 종래의 반도체소자, 즉 트랜지스터는 도2의 등가회로도로 알 수 있는 바와같이 게이트에 문턱전압(Vt) 이상의 전압이 인가되면 드레인과 소스 사이에 채널이 형성되어 전류가 흐르고, 게이트에 인가되는 전압을 차단하면 드레인과 소스 사이에 형성된 채널이 차단되어 전류가 흐르지 않게 되는 스위칭(switching) 동작을 대표적 특성이라 할 수 있다.In the conventional semiconductor device manufactured as described above, that is, a transistor, when a voltage equal to or greater than a threshold voltage Vt is applied to a gate as shown in the equivalent circuit diagram of FIG. 2, a channel is formed between the drain and the source, and a current flows. When the voltage applied to the gate is cut off, a switching operation is performed such that a channel formed between the drain and the source is blocked so that no current flows.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 반도체소자가 고집적화되면서 설계-규칙(design-rule)이 감소함에 따라 게이트의 길이가 짧은 트랜지스터가 요구되어 게이트의 전극물질로 폴리실리콘을 적용하게 되면, 단-채널 효과(short-channel effect)와 펀치-쓰루로 인한 소자특성이 열화되는 것이 잘 알려져 있으며, 게이트와 드레인의 겹쳐지는 영역이 넓지 않게 형성됨에 따라 열전자효과(hot carrier effect)로 인해 소자특성이 열화되며, 게이트 가장자리에서 발생되는 누설전류로 인해 트랜지스터의 신뢰성저하 및 게이트산화막의 얇은 두께로 인해 커패시턴스가 증착하여 트랜지스터의 동작속도가 저하를 피할 수 없다.However, the conventional method of manufacturing a semiconductor device as described above requires a transistor having a short gate length as the semiconductor device is highly integrated and the design-rule decreases, and thus polysilicon is applied as the electrode material of the gate. It is well known that device characteristics due to short-channel effects and punch-through deteriorate, and as a result of the hot carrier effect as the overlapping region of the gate and drain is not widened. Due to the deterioration of characteristics and leakage current generated at the gate edges, the reliability of the transistor and the thin thickness of the gate oxide film cause capacitance to be deposited, thereby reducing the operation speed of the transistor.
또한, 고성능(high performance) 트랜지스터의 제작 공정에서는 중첩 도핑(crossed doping)되는 이온들의 효율적인 공정제어에 많은 시행착오가 요구되어 생산성이 저하됨과 아울러 소자특성의 훌륭한 조절(fine tuning)이 어렵고, 일반적인 엘디디(lightly doped drain : LDD) 구조로 제작됨에 따른 소자특성의 최적화 한계 및 고집적화 한계를 보이게 된다.In addition, in the fabrication process of high performance transistors, a lot of trial and error is required for efficient process control of cross-doped ions, which leads to low productivity and fine tuning of device characteristics. As it is manufactured with lightly doped drain (LDD) structure, it shows optimization limit and high integration limit of device characteristics.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 메탈 게이트 트랜지스터의 단-채널 게이트 형성을 용이하게 하고, 선택적인 불순물 이온주입을 통해 카운터 도핑을 방지함과 아울러 트랜지스터 특성의 미세조정을 개선하며, 펀치-쓰루를 억제함과 아울러 게이트와 드레인의 겹쳐지는 영역을 최적화하고, 게이트산화막의 두께를 게이트의 가장자리에서 상대적으로 두껍게 형성하여 게이트와 드레인의 겹쳐지는 영역의 커패시턴스를 감소시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to facilitate the formation of a short-channel gate of a metal gate transistor, and to prevent counter doping through selective impurity ion implantation. In addition, it improves the fine tuning of transistor characteristics, suppresses punch-through, optimizes the overlapping area of the gate and drain, and forms the gate oxide film with a relatively thick thickness at the edge of the gate to overlap the area of the gate and drain. It is to provide a method of manufacturing a semiconductor device that can reduce the capacitance of.
도1은 일반적인 트랜지스터의 단면도.1 is a cross-sectional view of a typical transistor.
도2는 도1의 등가회로도.2 is an equivalent circuit diagram of FIG.
도3a 내지 도3p는 본 발명의 일 실시예를 보인 수순단면도.3a to 3p are cross-sectional views showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***
11:반도체기판 12:패드산화막11: semiconductor substrate 12: pad oxide film
13:고온저압산화막 14:버퍼산화막13: High temperature low pressure oxide film 14: Buffer oxide film
15:질화막 16:펀치쓰루 방지층15: nitride film 16: punch-through prevention layer
17:문턱전압 조절층 18:채널 리세스산화막17: threshold voltage control layer 18: channel recess oxide film
19:저농도영역 20,24:제1,제2게이트산화막19: low concentration region 20, 24: first and second gate oxide films
21:폴리실리콘 22:소스/드레인 영역21: Polysilicon 22: Source / Drain Area
23:층간절연막 25:게이트전극23: interlayer insulating film 25: gate electrode
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 제조방법은 반도체기판의 상부에 패드산화막과 고온저압산화막을 형성한 후, 게이트가 형성될 영역의 고온저압산화막과 패드산화막을 식각하고, 계속해서 반도체기판을 소정의 깊이로 식각하는 공정과; 상기 구조물의 상부전면에 버퍼산화막과 질화막을 증착한 다음 선택적으로 식각하여 식각된 영역의 측면에 내부 질화막측벽을 형성하는 공정과; 상기 구조물에 산화공정을 실시하여 반도체기판과 접촉되는 버퍼산화막 상에 채널 리세스(recess)산화막을 형성하는 공정과; 상기 내부 질화막측벽을 제거한 후, 저농도 불순물이온을 주입하여 반도체기판 내에 저농도영역을 형성하는 공정과; 상기 채널 리세스산화막과 버퍼산화막을 제거한 후, 산화공정을 실시하여 노출된 반도체기판의 표면 상에 제1게이트산화막을 형성하는 공정과; 상기 구조물의 상부전면에 폴리실리콘을 증착하여 식각된 영역을 채운 다음 고온저압산화막이 노출될때까지 평탄화하는 공정과; 상기 고온저압산화막을 제거한 후, 고농도 불순물이온을 주입하여 소스/드레인 영역을 형성하는 공정과; 상기 구조물의 상부전면에 층간절연막을 증착한 다음 폴리실리콘이 노출될때까지 평탄화하는 공정과; 상기 폴리실리콘을 선택적으로 식각하여 내부 폴리실리콘측벽을 형성한 다음 하부에 노출된 제1게이트산화막을 제거하는 공정과; 상기 내부 폴리실리콘측벽을 제거한 다음 산화공정을 통해 반도체기판의 표면 상에 제2게이트산화막을 형성하는 공정과; 상기 구조물의 상부전면에 게이트전극을 형성한 다음 층간절연막이 노출될때까지 평탄화하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In the method of manufacturing a semiconductor device for achieving the object of the present invention as described above, after forming a pad oxide film and a high temperature low pressure oxide film on the semiconductor substrate, the high temperature low pressure oxide film and the pad oxide film in the region where the gate is to be formed are etched, Subsequently etching the semiconductor substrate to a predetermined depth; Depositing a buffer oxide film and a nitride film on an upper surface of the structure and then selectively etching to form an inner nitride film side wall on the side of the etched region; Performing an oxidation process on the structure to form a channel recess oxide film on the buffer oxide film in contact with the semiconductor substrate; Removing the internal nitride film side walls and implanting low concentration impurity ions to form a low concentration region in the semiconductor substrate; Removing the channel recess oxide film and the buffer oxide film, and then performing an oxidation process to form a first gate oxide film on the exposed surface of the semiconductor substrate; Depositing polysilicon on the upper surface of the structure to fill the etched region and then planarizing it until the high temperature low pressure oxide film is exposed; Removing the high temperature low pressure oxide film and then implanting a high concentration of impurity ions to form a source / drain region; Depositing an interlayer insulating film on the upper surface of the structure and then planarizing it until the polysilicon is exposed; Selectively etching the polysilicon to form internal polysilicon sidewalls and then removing the first gate oxide film exposed below; Removing the inner polysilicon sidewall and forming a second gate oxide film on the surface of the semiconductor substrate through an oxidation process; And forming a gate electrode on the upper surface of the structure and then planarizing it until the interlayer insulating film is exposed.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법을 도3a 내지 도3p의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 3A to 3P.
먼저, 도3a에 도시한 바와같이 반도체기판(11)의 상부에 순차적으로 패드산화막(12)과 고온저압산화막(high temperature low pressure deposition : HLD, 13)을 증착한다.First, as shown in FIG. 3A, a pad oxide film 12 and a high temperature low pressure deposition (HLD) 13 are sequentially deposited on the semiconductor substrate 11.
그리고, 도3b에 도시한 바와같이 상기 고온저압산화막(13) 상에 사진식각공정을 적용하여 게이트가 형성될 영역의 고온저압산화막(13)과 패드산화막(12)을 식각하고, 계속하여 노출된 반도체기판(11)을 소정의 깊이로 식각한다.3B, the high temperature low pressure oxide film 13 and the pad oxide film 12 in the region where the gate is to be formed are etched by applying a photolithography process on the high temperature low pressure oxide film 13, and subsequently exposed. The semiconductor substrate 11 is etched to a predetermined depth.
그리고, 도3c에 도시한 바와같이 상기 반도체기판(11)이 식각된 구조물의 상부전면에 버퍼산화막(14)을 증착하고, 그 상부에 질화막(15)을 증착하여 식각된 영역을 채운 다음 선택적으로 식각하여 식각된 영역의 측면 버퍼산화막(14) 상에 내부 질화막(15) 측벽을 형성한다.As shown in FIG. 3C, the buffer oxide film 14 is deposited on the upper surface of the structure on which the semiconductor substrate 11 is etched, and the nitride film 15 is deposited on the top thereof to fill the etched region. The sidewalls of the internal nitride layer 15 are formed on the side buffer oxide layer 14 in the etched region by etching.
그리고, 도3d에 도시한 바와같이 상기 내부 질화막(15) 측벽을 마스크로 적용하여 펀치쓰루 방지 및 문턱전압 조절을 위한 불순물이온을 순차적으로 주입하여 반도체기판(11) 내에 펀치쓰루 방지층(16) 및 문턱전압 조절층(17)을 형성한다.As shown in FIG. 3D, by applying sidewalls of the internal nitride film 15 as a mask, impurity ions are sequentially injected to prevent punch-through and threshold voltage, thereby forming the punch-through prevention layer 16 and the semiconductor substrate 11. The threshold voltage adjusting layer 17 is formed.
그리고, 도3e에 도시한 바와같이 상기 펀치쓰루 방지층(16) 및 문턱전압 조절층(17)이 형성된 구조물 상에 산화공정을 적용하여 상기 반도체기판(11)과 접속되는 버퍼산화막(12) 상에 채널 리세스산화막(18)을 형성한다. 이때, 상기 내부 질화막(15) 측벽이 채널 리세스산화막(18)의 형성을 억제함에 따라 채널 리세스산화막(18)은 내부 질화막(15) 측벽이 형성되지 않은 영역의 버퍼산화막(12)과 반도체기판(11)의 접촉되는 영역에 부풀어 오르는 형상으로 형성된다.As shown in FIG. 3E, an oxidation process is applied to the structure on which the punch-through prevention layer 16 and the threshold voltage control layer 17 are formed, and then on the buffer oxide film 12 connected to the semiconductor substrate 11. A channel recess oxide film 18 is formed. At this time, as the sidewalls of the internal nitride film 15 inhibit the formation of the channel recess oxide film 18, the channel recess oxide film 18 is formed of the buffer oxide film 12 and the semiconductor in the region where the sidewalls of the internal nitride film 15 are not formed. It is formed in a shape that swells in the contact area of the substrate 11.
그리고, 도3f에 도시한 바와같이 상기 내부 질화막(15) 측벽을 제거한 후, 상부전면에 저농도 불순물이온을 주입하여 내부 질화막(15) 측벽이 제거된 영역의 반도체기판(11) 내에 선택적으로 저농도영역(19)을 형성한다.After removing the sidewalls of the internal nitride film 15 as shown in FIG. 3F, low concentration impurity ions are implanted into the upper front surface to selectively select a low concentration region in the semiconductor substrate 11 in a region where the sidewalls of the internal nitride film 15 are removed. (19) is formed.
그리고, 도3g에 도시한 바와같이 상기 채널 리세스산화막(18) 및 버퍼산화막(12)을 제거한다.As shown in Fig. 3G, the channel recess oxide film 18 and the buffer oxide film 12 are removed.
그리고, 도3h에 도시한 바와같이 상기 구조물 상에 산화공정을 실시하여 반도체기판(11)의 노출된 표면상에 제1게이트산화막(20)을 형성한다. 이때, 반도체기판(11)의 표면뿐만 아니라 상기 고온저압산화막(13)의 표면에도 반도체기판(11)의 표면에 비해 얇은 제1게이트산화막(20)이 형성된다.As shown in FIG. 3H, an oxidation process is performed on the structure to form the first gate oxide film 20 on the exposed surface of the semiconductor substrate 11. In this case, the first gate oxide film 20 thinner than the surface of the semiconductor substrate 11 is formed on the surface of the high temperature low pressure oxide film 13 as well as the surface of the semiconductor substrate 11.
그리고, 도3i에 도시한 바와같이 상기 제1게이트산화막(20)이 형성된 반도체기판(11)의 상부전면에 식각된영역이 채워지도록 폴리실리콘(21)을 증착한다.As illustrated in FIG. 3I, polysilicon 21 is deposited to fill an etched region on the upper surface of the semiconductor substrate 11 on which the first gate oxide film 20 is formed.
그리고, 도3j에 도시한 바와같이 상기 폴리실리콘(21)을 고온저압산화막(13)이 노출될때까지 화학기계적 연마(chemical mechanical polishing : CMP)하여 평탄화한다.3J, the polysilicon 21 is planarized by chemical mechanical polishing (CMP) until the high temperature low pressure oxide film 13 is exposed.
그리고, 도3k에 도시한 바와같이 상기 노출된 고온저압산화막(13)을 제거한 후, 폴리실리콘(21)을 마스크로 적용하여 버퍼산화막(12)을 통해 반도체기판(11) 내에 불순물이온을 주입함으로써, 소스/드레인 영역(22)을 형성한다.After removing the exposed high temperature and low pressure oxide film 13 as shown in FIG. 3K, polysilicon 21 is applied as a mask to inject impurity ions into the semiconductor substrate 11 through the buffer oxide film 12. Source / drain regions 22 are formed.
그리고, 도3l에 도시한 바와같이 상기 소스/드레인 영역(22)이 형성된 반도체기판(11)의 상부전면에 층간절연막(inter layer dielectric : ILD, 23)을 증착한 후, 상기 폴리실리콘(21)이 노출될때까지 화학기계적 연마하여 평탄화한다.As shown in FIG. 3L, an interlayer dielectric (ILD) 23 is deposited on the upper surface of the semiconductor substrate 11 on which the source / drain regions 22 are formed, and then the polysilicon 21 is deposited. It is planed by chemical mechanical polishing until it is exposed.
그리고, 도3m에 도시한 바와같이 상기 노출된 폴리실리콘(21)을 선택적으로 식각하여 제1게이트산화막(20)의 측면 상에 내부 폴리실리콘(21) 측벽을 형성한 다음 노출된 제1게이트산화막(20)을 식각하여 반도체기판(11)을 노출시킨다.3M, the exposed polysilicon 21 is selectively etched to form sidewalls of the internal polysilicon 21 on the side of the first gate oxide film 20, and then the exposed first gate oxide film. The semiconductor substrate 11 is exposed by etching 20.
그리고, 도3n에 도시한 바와같이 내부 폴리실리콘(21) 측벽을 제거한 다음 산화공정을 실시하여 상기 노출된 반도체기판(11)의 표면상에 제2게이트산화막(24)을 형성한다. 이때, 제2게이트산화막(24)은 제1게이트산화막(20)에 비해 얇게 형성하는 것이 바람직하다.As shown in FIG. 3N, the sidewalls of the inner polysilicon 21 are removed and then an oxidation process is performed to form the second gate oxide film 24 on the exposed surface of the semiconductor substrate 11. In this case, the second gate oxide film 24 may be formed thinner than the first gate oxide film 20.
그리고, 도3o에 도시한 바와같이 상기 제2게이트산화막(24)이 형성된 반도체기판(11)의 상부전면에 게이트전극(25)을 형성한다. 이때, 게이트전극(25)은 금속물질을 적용하며, W 또는 Al 중에 선택된 하나로 형성하는 것이 바람직하다.As shown in FIG. 3O, the gate electrode 25 is formed on the upper surface of the semiconductor substrate 11 on which the second gate oxide film 24 is formed. At this time, the gate electrode 25 is applied to a metal material, it is preferable to form one selected from W or Al.
그리고, 도3p에 도시한 바와같이 상기 게이트전극(25)을 층간절연막(23)이 노출될때까지 화학기계적 연마하여 평탄화한 다음 열처리를 통해 주입된 불순물이온을 최적화한다.As shown in FIG. 3P, the gate electrode 25 is chemically polished and planarized until the interlayer insulating film 23 is exposed, and then the impurity ions implanted through heat treatment are optimized.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 반도체기판 상에 게이트가 형성될 영역을 소정의 깊이로 식각하고, 내부 질화막 측벽을 형성하여 펀치쓰루 방지 및 문턱전압 조절을 위한 불순물이온을 해당영역에만 선택적으로 실시함에 따라 채널영역에서 저농도영역 및 소스/드레인 영역을 형성할 때 주입되는 불순물이온과의 카운터도핑을 방지할 수 있으며, 채널 리세스산화막을 형성한 다음 내부 질화막 측벽을 제거하고, 저농도 불순물이온을 주입하여 해당영역에 선택적으로 저농도영역을 형성함에 따라 소스/드레인 영역을 형성할 때 주입되는 불순물이온과의 카운터도핑을 방지함과 아울러 게이트와 저농도영역의 겹쳐지는 영역을 최적화하여 수직전계에 의해 저농도영역의 내부저항을 최소화함으로써, 트랜지스터의 구동능력을 향상시킴과 아울러 수직전계를 상대적으로 저감시킬 수 있게 됨으로써, 열전자효과를 개선시킴과 아울러 단채널효과 및 펀치쓰루를 억제할 수 있다.The method of manufacturing a semiconductor device according to the present invention as described above etches an area on which a gate is to be formed on a semiconductor substrate to a predetermined depth, and forms an internal nitride film sidewall to deal with impurity ions for preventing punch through and adjusting a threshold voltage. By selectively performing only the region, counter-doping with impurity ions implanted when forming the low concentration region and the source / drain region in the channel region can be prevented, and after forming the channel recess oxide layer, the inner nitride sidewall is removed, As low concentration impurity ions are implanted to selectively form low concentration regions in the corresponding region, counter doping with impurity ions implanted when forming source / drain regions is prevented, and the overlapping area of gate and low concentration regions is optimized by vertical By minimizing the internal resistance of low concentration region by electric field, In addition, the vertical electric field can be relatively reduced, thereby improving the thermoelectric effect and suppressing the short channel effect and punch through.
또한, 게이트의 가장자리에서 게이트산화막을 보다 두껍게 형성함에 따라 게이트와 저농도영역의 겹쳐지는 영역이 최적화됨에 따른 커패시턴스 증가를 방지할 수 있으며, 전체적으로 자기정렬(self-align)되는 내부 질화막측벽, 채널 리세스산화막 및 내부 폴리실리콘측벽을 적용함에 따라 이온주입을 원하는 영역의 면적을 자유롭게 선택할 수 있게 되므로, 공정의 제어가 용이함과 아울러 금속재질의 게이트전극을 쉽게 형성할 수 있게 되어 생산성을 향상시킬 수 있는 효과가 있다.In addition, by forming a thicker gate oxide film at the edge of the gate, it is possible to prevent capacitance increase due to the optimization of the overlapping region of the gate and the low concentration region, and the internal nitride film side walls and channel recesses which are self-aligned as a whole. By applying the oxide film and the inner polysilicon side wall, the area of the desired region for ion implantation can be freely selected, thereby facilitating control of the process and easily forming a gate electrode made of metal, thereby improving productivity. There is.
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| KR100402102B1 (en) * | 2001-06-29 | 2003-10-17 | 주식회사 하이닉스반도체 | method for manufacturing of transistor of semiconductor device |
| KR100900145B1 (en) * | 2002-07-18 | 2009-06-01 | 주식회사 하이닉스반도체 | Method for manufacturing a transistor |
| KR101068137B1 (en) * | 2004-04-19 | 2011-09-27 | 매그나칩 반도체 유한회사 | Method for manufacturing high voltage transistor |
| CN106910671A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
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1999
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402102B1 (en) * | 2001-06-29 | 2003-10-17 | 주식회사 하이닉스반도체 | method for manufacturing of transistor of semiconductor device |
| KR100900145B1 (en) * | 2002-07-18 | 2009-06-01 | 주식회사 하이닉스반도체 | Method for manufacturing a transistor |
| KR101068137B1 (en) * | 2004-04-19 | 2011-09-27 | 매그나칩 반도체 유한회사 | Method for manufacturing high voltage transistor |
| CN106910671A (en) * | 2015-12-23 | 2017-06-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic installation |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100328827B1 (en) | 2002-03-14 |
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