KR20010008620A - Method for manufacturing transistor of a semiconductor device - Google Patents
Method for manufacturing transistor of a semiconductor device Download PDFInfo
- Publication number
- KR20010008620A KR20010008620A KR1019990026540A KR19990026540A KR20010008620A KR 20010008620 A KR20010008620 A KR 20010008620A KR 1019990026540 A KR1019990026540 A KR 1019990026540A KR 19990026540 A KR19990026540 A KR 19990026540A KR 20010008620 A KR20010008620 A KR 20010008620A
- Authority
- KR
- South Korea
- Prior art keywords
- epitaxial silicon
- gate electrode
- oxide film
- layer
- polysilicon
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000000034 method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 9
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
Description
본 발명은 반도체장치의 트랜지스터 제조 방법에 관한 것으로서, 보다 상세하게는 STI구조에서 산화막 사이에 에피실리콘을 성장하여 채널을 형성하고 폴리실리콘을 이용하여 산화막 표면에 소오스와 드레인을 형성하여 정션 커패시턴스를 감소시킨 반도체장치의 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, to form a channel by growing episilicon between oxide films in an STI structure, and to reduce junction capacitance by forming a source and a drain on the oxide film surface using polysilicon. The present invention relates to a transistor manufacturing method of a semiconductor device.
전계효과 트랜지스터(Field-Effect Transistor; FET)라 함은 다수 캐리어가 반도체 표면을 따라서 드리프트 하는 것을 게이트 전계에 의해 제어하는 방식의 트랜지스터를 말하는 것으로서 소수캐리어의 주입이 없으므로 축적효과에 의한 응답 속도의 저하가 없고, 잡음이 적은 장점이 있다. 전계효과 트랜지스터에는 게이트의 구조에 의해 접합형 전계효과 트랜지스터(Junction Field-Effect Transistor ; JFET)와 쇼트키 장벽 게이트형 및 절연 게이트형 전계효과 트랜지스터(Insulator Gate Field Effect Transistor ; IGFET)가 있다.Field-Effect Transistors (FETs) refer to transistors in which a majority of carriers drift along the semiconductor surface by means of a gate electric field, and there is no injection of a small number of carriers, thereby reducing the response speed due to the accumulation effect. There is no noise and low noise. Field effect transistors include junction field-effect transistors (JFETs) and Schottky barrier gate type and insulator gate field effect transistors (IGFETs) by gate structures.
MOS트랜지스터의 경우에는 쇼트 채널화와 함께 핫캐리어에 의한 소자의 특성 저하가 심화되어 소자의 동작 전압을 그만큼 낮게 설정하게 되었으며 소자의 드레인 구조도 n+ 농도의 드레인 구조의 주위를 저농도로 감싸준 DDD(Double Diffused Drain)구조와 드레인과 채널과의 연결 부위의 농도를 낮추어 준 LDD(Lightly Doped Drain)구조로 개량되었다.In the case of MOS transistors, short channelization and deterioration of device characteristics due to hot carriers have increased, and the operating voltage of the device has been set as low as possible. Diffused Drain (LDD) structure and LDD (Lightly Doped Drain) structure that reduced the concentration of the connection between the drain and the channel.
도 1은 종래의 LDD구조의 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view showing a transistor of a conventional LDD structure.
여기에 도시된 바와 같이 반도체 기판(10)에 소자간 격리를 위한 필드산화막을 형성하고 게이트산화막과 제 1폴리실리콘과 텅스텐 실리사이드와 제 2폴리실리콘과 제 1절연막을 차례로 증착한 후 적층구조의 게이트전극(20)을 형성하고, LDD 이온주입을 통해 소오스와 드레인의 확산층(30)을 형성한 후 게이트전극(30)의 측벽에 스페이서(40)를 형성하여 트랜지스터를 완성하게 된다. 이후 랜딩플러그(50)를 형성하여 금속 배선을 연결하게 된다.As shown here, a field oxide film for inter-device isolation is formed on the semiconductor substrate 10, and the gate oxide film, the first polysilicon, tungsten silicide, the second polysilicon, and the first insulating film are sequentially deposited, and then the gate of the laminated structure. After forming the electrode 20 and forming the diffusion layer 30 of the source and the drain through LDD ion implantation, a spacer 40 is formed on the sidewall of the gate electrode 30 to complete the transistor. Thereafter, the landing plug 50 is formed to connect the metal wires.
이와 같은 트랜지스터에는 소오스와 드레인의 불순물들이 옆으로 확산되어 펀치스루 효과를 유발하기 쉽게 되어 이를 방지하기 위한 이온주입 공정이 많아지는 문제가 있다. 또한, 채널 길이 및 농도조절이 어려워 문턱 전압 조절이 어렵다는 문제가 있다.In such a transistor, impurities of a source and a drain are diffused to the side to easily cause a punch-through effect, thereby increasing the ion implantation process to prevent this. In addition, it is difficult to adjust the channel length and concentration, there is a problem that difficult to adjust the threshold voltage.
그리고, 커패시터를 형성하기 위한 콘택 정션이 손상될 경우 커패시터 및 리플레쉬 특성이 악화될 뿐만 아니라 소오스 및 드레인과 웰사이의 정션 커패시턴스로 인해 저항성분이 증가한다는 문제점이 있다.In addition, when the contact junction for forming the capacitor is damaged, not only the capacitor and the refresh characteristics deteriorate, but also the resistance component increases due to the junction capacitance between the source and the drain and the well.
본 발명은 상기와 같은 문제점을 해결하기 위해 창작된 것으로서, 본 발명의 목적은 STI구조에서 산화막 사이에 에피텍셜실리콘을 성장시켜 채널을 형성하고 폴리실리콘을 이용하여 산화막 표면에 소오스와 드레인을 형성하여 정션 커패시턴스를 감소시킨 반도체장치의 트랜지스터 제조 방법을 제공함에 있다.The present invention has been made to solve the above problems, an object of the present invention is to grow epitaxial silicon between the oxide film in the STI structure to form a channel and to form a source and drain on the oxide film surface using polysilicon The present invention provides a method for manufacturing a transistor of a semiconductor device with reduced junction capacitance.
도 1은 종래의 LDD구조의 트랜지스터를 나타낸 단면도이다.1 is a cross-sectional view showing a transistor of a conventional LDD structure.
도 2내지 도 6은 본 발명에 의한 반도체장치의 트랜지스터 제조 방법을 설명하기 위한 단면도들이다.2 to 6 are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device according to the present invention.
도 7내지 도 11은 본 발명의 다른 실시예에 따른 반도체장치의 트랜지스터 제조 방법을 설명하기 위한 단면도들이다.7 through 11 are cross-sectional views illustrating a method of fabricating a transistor in a semiconductor device in accordance with another embodiment of the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
10 : 기판 20 : 게이트전극10: substrate 20: gate electrode
30 : 확산층 40 : 스페이서30: diffusion layer 40: spacer
50 : 랜딩플러그 60 : 산화막50: landing plug 60: oxide film
62 : 에피텍셜실리콘 64 : 폴리실리콘62: epitaxial silicon 64: polysilicon
상기와 같은 목적을 실현하기 위한 본 발명은 반도체 기판에 트랜치 식각한 후 셀웰 인플란트를 진행하고 트랜치 부위에 산화막을 증착한 후 평탄화하는 단계와, 산화막을 채널마스크를 통해 식각하고 그 부위에 에피텍셜실리콘을 성장시킨 후 평탄화시키는 단계와, 에피텍셜실리콘을 성장시킨 후 소오스/드레인 마스크를 통해 산화막을 식각하고 폴리실리콘을 증착하고 평탄화하는 단계와, 에피텍셜실리콘 위로 폴리사이드구조의 게이트전극을 형성하는 단계와, 폴리실리콘의 소오스/드레인 영역에 이온주입을 통해 LDD구조 및 게이트전극 측벽에 스페이서를 형성하는 단계와, 결과물 전면에 층간절연막을 증착한후 평탄화 하고 랜딩 플러그를 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The present invention for achieving the above object is to trench-etch a semiconductor substrate and then proceed with a cellwell implant and to deposit an oxide film on the trench portion and to planarize, and to etch the oxide film through a channel mask and epitaxial silicon on the portion Growing and planarizing, growing an epitaxial silicon, etching an oxide film through a source / drain mask, depositing and planarizing polysilicon, and forming a gate electrode having a polyside structure on the epitaxial silicon And forming spacers on the LDD structure and the gate electrode sidewalls through ion implantation into the source / drain regions of the polysilicon, and depositing an interlayer insulating film on the entire surface of the resultant to planarize and form a landing plug. It features.
또한, 산화막을 기판에 매립되도록 구성하는 대신 기판 위로 형성할 수도 있다.Alternatively, the oxide film may be formed over the substrate instead of being embedded in the substrate.
또한, 트랜지스터의 구조는 반도체 기판상에 형성된 산화막과, 산화막 사이에 성장되어 채널을 형성하는 에피텍셜실리콘과, 에피텍셜실리콘 양쪽의 산화막 위로 형성되어 소오스와 드레인 영역을 형성하는 폴리실리콘과, 에피텍셜실리콘의 상부에 형성된 게이트전극과, 게이트전극 에지 하부의 폴리실리콘에 형성된 LDD구조의 확산층과, 게이트전극 측벽에 형성된 스페이서와, 확산층에 수직으로 형성된 랜딩 플러그로 이루어진 것을 특징으로 한다.Further, the structure of the transistor includes an oxide film formed on a semiconductor substrate, epitaxial silicon grown between the oxide film to form a channel, polysilicon formed over the oxide film on both epitaxial silicon to form a source and a drain region, and epitaxial And a gate electrode formed on the silicon, a diffusion layer of an LDD structure formed on polysilicon under the gate electrode edge, a spacer formed on the sidewall of the gate electrode, and a landing plug perpendicular to the diffusion layer.
위와 같이 이루어진 본 발명은 소오스와 드레인이 산화막 위에 형성되고 소오스와 드레인 사이에 에피텍셜실리콘이 채널로 형성되어 있어 소오스와 드레인에 주입된 불순물의 확산영향을 감소시킬 수 있으며 소오스와 드레인과 산화막 사이에 정션이 형성되지 않으므로 정션 손상 및 정션 커패시턴스를 감소시킬 수 있게 된다.In the present invention made as described above, the source and the drain are formed on the oxide film, and epitaxial silicon is formed as the channel between the source and the drain, thereby reducing the diffusion effect of impurities injected into the source and the drain, and between the source and the drain and the oxide film. Since no junction is formed, it is possible to reduce junction damage and junction capacitance.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.
도 2내지 도 6은 본 발명에 의한 반도체장치의 트랜지스터 제조 방법을 설명하기 위한 단면도들이다.2 to 6 are cross-sectional views illustrating a transistor manufacturing method of a semiconductor device according to the present invention.
도 2에서 보는 바와 같이 기판(10)에 트랜치 식각을 실시한다. 그런다음 셀웰 인플란트를 진행하고 HDP 산화막(60)을 증착한 후 평탄화시킨다.As shown in FIG. 2, trench etching is performed on the substrate 10. Then, the cellwell implant is performed and the HDP oxide layer 60 is deposited and planarized.
그런다음, 도 3과 같이 채널마스크를 통해 산화막(60)을 식각하고 그 부위에 에피텍셜실리콘(62)을 성장시킨 후 평탄화시킨다.Next, as shown in FIG. 3, the oxide layer 60 is etched through the channel mask, and the epitaxial silicon 62 is grown on the planarized portion.
그리고, 도 4와 같이 소오스/드레인 마스크를 통해 산화막(60)을 일정 깊이 식각하고 폴리실리콘(64)을 증착하고 평탄화시킨다.Then, the oxide film 60 is etched to a certain depth through the source / drain mask as shown in FIG. 4, and the polysilicon 64 is deposited and planarized.
그리고, 도 5와 같이 에피텍셜실리콘(62) 위로 도프드 폴리실리콘과 텅스텐 실리사이드와 마스크산화막을 순차적으로 증착한 후 패터닝하여 게이트전극(20)을 형성하고 LDD 구조의 확산층(30)을 형성한 후 게이트전극(20) 측벽에 스페이서(40)를 형성한다.5, after the doped polysilicon, the tungsten silicide, and the mask oxide film are sequentially deposited on the epitaxial silicon 62, the gate electrode 20 is formed by patterning, and then the diffusion layer 30 having the LDD structure is formed. The spacer 40 is formed on the sidewall of the gate electrode 20.
그리고, 도 6과 같이 층간절연막(70)으로 BPSG와 PETEOS를 증착한 후 평탄화시킨다음 랜딩 플러그 콘택을 형성한 후 랜딩플러그 폴리를 증착하여 랜딩 플러그(50)를 형성한다.Then, as shown in FIG. 6, the BPSG and the PETEOS are deposited and planarized with the interlayer insulating layer 70, and then the landing plug contact is formed. Then, the landing plug poly is deposited to form the landing plug 50.
도 7내지 도 11은 본 발명의 다른 실시예에 따른 반도체장치의 트랜지스터 제조 방법을 설명하기 위한 단면도들이다.7 through 11 are cross-sectional views illustrating a method of fabricating a transistor in a semiconductor device in accordance with another embodiment of the present invention.
도 7에서 보는 바와 같이 기판(10)에 셀웰 인플란트를 진행하고 기판 표면 위로 산화막(60)을 증착한 후 평탄화시킨다.As shown in FIG. 7, a cellwell implant is applied to the substrate 10, an oxide film 60 is deposited on the substrate surface, and then planarized.
그런다음, 도 8과 같이 채널마스크를 통해 산화막(60)을 식각하고 그 부위에 에피텍셜실리콘(62)을 성장시킨 후 평탄화시킨다.Next, as shown in FIG. 8, the oxide layer 60 is etched through the channel mask, and the epitaxial silicon 62 is grown on the planarized portion.
그리고, 도 9와 같이 소오스/드레인 마스크를 통해 산화막(60)을 일정 깊이 식각하고 폴리실리콘(64)을 증착하고 평탄화시킨다.9, the oxide layer 60 is etched to a certain depth through the source / drain mask, and the polysilicon 64 is deposited and planarized.
그리고, 도10과 같이 에피텍셜실리콘(62) 위로 도프드 폴리실리콘과 텅스텐 실리사이드와 마스크산화막을 순차적으로 증착한 후 패터닝하여 게이트전극(20)을 형성하고 LDD 구조의 확산층(30)을 형성한 후 게이트전극(20) 측벽에 스페이서(40)를 형성한다.10, the doped polysilicon, the tungsten silicide, and the mask oxide film are sequentially deposited on the epitaxial silicon 62, and then patterned to form the gate electrode 20, and then the diffusion layer 30 having the LDD structure is formed. The spacer 40 is formed on the sidewall of the gate electrode 20.
그리고, 도 11과 같이 층간절연막(70)으로 BPSG와 PETEOS를 증착한 후 평탄화시킨다음 랜딩 플러그 콘택을 형성한 후 랜딩플러그 폴리를 증착하여 랜딩 플러그(50)를 형성한다.Then, as illustrated in FIG. 11, the BPSG and the PETEOS are deposited and planarized with the interlayer insulating layer 70, and then the landing plug contact is formed. Then, the landing plug poly is deposited to form the landing plug 50.
상기한 바와 같이 본 발명은 소오스 및 드레인이 산화막 위에 형성되므로 소오스 및 드레인 확산 영향을 감소시켜 펀치 특성 및 채널 농도조절을 향상시킬 수 있다. 또한, 소오스 및 드레인이 산화막 위에 형성되므로 정션 손상으로 인한 커패시터 및 리플레쉬 특성저하를 막을 수 있다.As described above, according to the present invention, since the source and the drain are formed on the oxide film, the influence of the source and the drain diffusion can be reduced to improve punch characteristics and channel concentration control. In addition, since the source and the drain are formed on the oxide film, it is possible to prevent the capacitor and the refresh characteristics from deterioration due to junction damage.
그리고, 소오스 및 드레인과 소오스간의 정션이 형성되지 않기 때문에 정션 커패시턴스가 감소된다는 이점이 있다.And since the junction between the source and the drain and the source is not formed, there is an advantage that the junction capacitance is reduced.
한편, 산화막을 반도체 기판 표면에 증착하여 형성하므로 채널을 반도체 기판 표면위에 형성함으로써 셀웰의 농도조절을 위한 이온 주입공정을 줄일 수 있다는 이점이 있다.On the other hand, since the oxide film is formed by depositing on the surface of the semiconductor substrate, the channel is formed on the surface of the semiconductor substrate, thereby reducing the ion implantation process for controlling the concentration of the cell well.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026540A KR20010008620A (en) | 1999-07-02 | 1999-07-02 | Method for manufacturing transistor of a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990026540A KR20010008620A (en) | 1999-07-02 | 1999-07-02 | Method for manufacturing transistor of a semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20010008620A true KR20010008620A (en) | 2001-02-05 |
Family
ID=19598893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990026540A KR20010008620A (en) | 1999-07-02 | 1999-07-02 | Method for manufacturing transistor of a semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20010008620A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491141B1 (en) * | 2001-03-02 | 2005-05-24 | 삼성에스디아이 주식회사 | TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT |
-
1999
- 1999-07-02 KR KR1019990026540A patent/KR20010008620A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491141B1 (en) * | 2001-03-02 | 2005-05-24 | 삼성에스디아이 주식회사 | TFT and Method for Fabricating the Same and Active Matrix display device and Method for fabricating the Same using the TFT |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100204805B1 (en) | Method for fabricating transistor | |
| US20060211197A1 (en) | Mos transistor and method of manufacturing the same | |
| KR100840661B1 (en) | Semiconductor Device and Manufacturing Method Thereof | |
| US7018899B2 (en) | Methods of fabricating lateral double-diffused metal oxide semiconductor devices | |
| KR950008257B1 (en) | Mos fet and its making method | |
| US6680504B2 (en) | Method for constructing a metal oxide semiconductor field effect transistor | |
| KR20010096350A (en) | Method For Forming The Gate Oxide Of MOS-FET Transistor | |
| KR100390907B1 (en) | Method for manufacturing of semiconductor device | |
| KR20040009748A (en) | Method of Fabricating MOS Transistor | |
| KR20010008620A (en) | Method for manufacturing transistor of a semiconductor device | |
| KR100349367B1 (en) | Method of manufacturing semiconductor device | |
| KR100916120B1 (en) | method for fabricating MOS transistor | |
| KR20000066568A (en) | Method of fabricating a semiconductor device | |
| US6905932B2 (en) | Method for constructing a metal oxide semiconductor field effect transistor | |
| KR100334967B1 (en) | Method for forming transistor of a semiconductor device | |
| KR20010064328A (en) | Method for fabricating MOS transistor with ITLDD structure | |
| KR0165421B1 (en) | Process of fabricating mos transistor | |
| JPH07273329A (en) | Semiconductor device and its manufacture | |
| KR0161873B1 (en) | Method of manufacturing semiconductor device | |
| KR100348314B1 (en) | Semiconductor device and method for fabricating the same | |
| KR20000061772A (en) | method of manufacturing semiconductor device | |
| KR20020044861A (en) | Method For Forming The MOS-FET Transistor | |
| KR20000003980A (en) | Transistor of semiconductor devices and method thereof | |
| KR20000046967A (en) | Fabrication method and construction of transistor | |
| KR19990062220A (en) | Manufacturing Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |