KR100280517B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100280517B1 KR100280517B1 KR1019980047964A KR19980047964A KR100280517B1 KR 100280517 B1 KR100280517 B1 KR 100280517B1 KR 1019980047964 A KR1019980047964 A KR 1019980047964A KR 19980047964 A KR19980047964 A KR 19980047964A KR 100280517 B1 KR100280517 B1 KR 100280517B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 종래에는 트렌치 상부의 가장자리가 손실됨에 따라 반도체소자의 험프를 유발시켜 반도체소자의 누설전류가 증가하는 문제점이 있었다. 따라서, 본 발명은 반도체기판의 상부에 버퍼산화막과 질화막을 형성하는 공정과; 1차 사진식각공정을 통해 필드가 형성될 영역의 질화막, 버퍼산화막 및 반도체기판을 식각한 후, 그 식각된 영역에 산화막을 채워서 트렌치를 형성하는 공정과; 2차 사진식각공정을 통해 게이트가 형성될 영역의 질화막 및 트렌치를 식각한 후, 그 식각된 영역에 게이트를 형성하고 평탄화하는 공정과; 상기 질화막을 제거한 후, 반도체기판의 상부전면에 절연막을 증착하고 선택적으로 식각하여 상기 게이트의 측벽을 형성하는 공정과; 반도체기판의 상부전면에 폴리실리콘을 증착하고 에치백하여 플러그를 형성하는 공정으로 이루어지는 반도체소자의 제조방법을 통해 트렌치의 손실을 차단하여 반도체소자의 누설전류를 감소시킬 수 있는 효과와; 질화막의 제거를 통해 플러그가 패터닝되므로, 층간절연막의 형성공정을 생략할 수 있어 열처리에 따른 반도체소자의 특성변화를 억제함과 아울러 플러그에 폴리실리콘을 채우기가 용이해져서 전체 공정이 단순화되는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the related art, as the edge of the upper portion of the trench is lost, a hump of the semiconductor device is induced, thereby increasing the leakage current of the semiconductor device. Therefore, the present invention comprises the steps of forming a buffer oxide film and a nitride film on the semiconductor substrate; Etching the nitride film, the buffer oxide film, and the semiconductor substrate in the region where the field is to be formed through a primary photolithography process, and then filling the etched region with an oxide film to form a trench; Etching the nitride film and the trench in the region where the gate is to be formed by a secondary photolithography process, and then forming and planarizing the gate in the etched region; Removing the nitride film, depositing an insulating film on an upper surface of the semiconductor substrate, and selectively etching to form sidewalls of the gate; A method of manufacturing a semiconductor device comprising a process of depositing polysilicon on an upper surface of a semiconductor substrate and etching back to form a plug, thereby preventing the loss of trenches to reduce leakage current of the semiconductor device; Since the plug is patterned by removing the nitride film, the formation process of the interlayer insulating film can be omitted, thereby suppressing the characteristic change of the semiconductor device due to heat treatment, and the polysilicon can be easily filled in the plug, thereby simplifying the overall process. .
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 절연(isolation)에서 플러그(plug) 형성에 이르는 제조공정을 단순화함과 아울러 전기적특성의 안정화를 도모한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, which simplifies the manufacturing process from isolation to plug formation and stabilizes electrical characteristics.
종래 반도체소자의 제조방법을 도1a 내지 1i에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be described in detail with reference to the procedure cross-sectional view shown in FIGS.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부전면에 버퍼산화막(2)과 질화막(3)을 순차적으로 형성한다.First, as shown in FIG. 1A, the buffer oxide film 2 and the nitride film 3 are sequentially formed on the upper surface of the semiconductor substrate 1.
그리고, 도1b에 도시한 바와같이 사진식각공정을 통해 상기 질화막(3)과 버퍼산화막(2)의 일부를 식각하고, 계속해서 노출된 반도체기판(1)을 소정깊이로 식각한다.As shown in FIG. 1B, a part of the nitride film 3 and the buffer oxide film 2 are etched through the photolithography process, and the subsequently exposed semiconductor substrate 1 is etched to a predetermined depth.
그리고, 도1c에 도시한 바와같이 상기 반도체기판(1)의 식각면을 산화시켜 얇은 산화막(4)을 형성한 후, 반도체기판(1)의 상부전면에 산화막(5)을 증착한 후 열처리한다.1C, the etching surface of the semiconductor substrate 1 is oxidized to form a thin oxide film 4, and then the oxide film 5 is deposited on the upper surface of the semiconductor substrate 1 and then heat treated. .
그리고, 도1d에 도시한 바와같이 상기 반도체기판(1)상의 버퍼산화막(2)이 노출될때까지 화학기계적 연마공정을 통해 평탄화하여 트렌치(trench)를 형성한다.As shown in FIG. 1D, a trench is formed by planarization through a chemical mechanical polishing process until the buffer oxide film 2 on the semiconductor substrate 1 is exposed.
그리고, 도1e에 도시한 바와같이 상기 트렌치가 형성된 반도체기판(1)상에 불순물이온을 주입하여 웰(6)을 형성하고, 반도체소자의 문턱전압을 조절하기 위한 불순물이온을 주입하여 이온주입영역(7)을 형성한다.As shown in FIG. 1E, the well 6 is formed by implanting impurity ions into the trench-formed semiconductor substrate 1, and implanting impurity ions to control the threshold voltage of the semiconductor device. (7) is formed.
그리고, 도1f에 도시한 바와같이 상기 반도체기판(1)의 상부전면에 순차적으로 게이트산화막(8), 폴리실리콘(9), WSix막(10), 캡산화막(11) 및 캡질화막(12)을 형성한다.1F, the gate oxide film 8, the polysilicon 9, the WSix film 10, the cap oxide film 11, and the cap nitride film 12 are sequentially disposed on the upper surface of the semiconductor substrate 1, as shown in FIG. To form.
그리고, 도1g에 도시한 바와같이 상기 캡질화막(12), 캡산화막(11), WSix막(10), 폴리실리콘(9) 및 게이트산화막(8)을 패터닝하여 상기 트렌치의 상부 및 반도체기판(1)의 상부에 각기 소정거리 이격되는 게이트패턴을 형성한다.As shown in FIG. 1G, the cap nitride film 12, the cap oxide film 11, the WSix film 10, the polysilicon 9, and the gate oxide film 8 are patterned to form an upper portion of the trench and a semiconductor substrate ( A gate pattern spaced a predetermined distance apart from each other is formed on 1).
그리고, 도1h에 도시한 바와같이 상기 게이트패턴이 형성된 반도체기판(1)의 상부전면에 질화막을 증착한 후 선택적으로 식각하여 게이트패턴의 측벽(13)을 형성하고, 노출된 반도체기판(1) 상에 불순물이온을 주입하여 소스/드레인영역을 형성한 후, 반도체기판(1)의 상부전면에 층간절연막(14)을 증착하여 평탄화한다.As shown in FIG. 1H, a nitride film is deposited on the upper surface of the semiconductor substrate 1 on which the gate pattern is formed, and then selectively etched to form sidewalls 13 of the gate pattern, thereby exposing the semiconductor substrate 1. After implanting impurity ions onto the source / drain regions, the interlayer insulating film 14 is deposited on the upper surface of the semiconductor substrate 1 to be planarized.
그리고, 도1i에 도시한 바와같이 사진식각공정을 통해 상기 게이트패턴의 이격영역에 형성된 층간절연막(14)을 식각하여 반도체기판(1)의 소스/드레인영역을 노출시킨 후, 반도체기판(1)의 상부전면에 폴리실리콘(15)을 증착하고 에치백하여 플러그를 형성한다.As shown in FIG. 1I, the interlayer insulating layer 14 formed in the spaced apart region of the gate pattern is etched through the photolithography process to expose the source / drain regions of the semiconductor substrate 1, and then the semiconductor substrate 1 is exposed. Polysilicon (15) is deposited on the upper surface of the etched back to form a plug.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 산화막을 증착하고 화학기계적 연마공정을 통해 평탄화하여 트렌치를 형성할 때, 그 산화막 상부의 가장자리가 손실(loss)됨에 따라 트렌치의 상부에 형성되는 게이트패턴의 불량으로 반도체소자의 험프(hump)를 유발시켜 반도체소자의 누설전류가 증가하는 문제점이 있었고, 또한 층간절연막의 형성시에 열처리를 수반함에 따라 반도체기판상에 주입된 불순물이온이 확산되어 반도체소자의 특성을 변화시키는 문제점과 아울러 사진식각공정을 통해 층간절연막을 식각한 후, 그 식각된 영역에 폴리실리콘을 채우는 공정이 쉽지않은 문제점이 있었다.However, in the method of manufacturing a conventional semiconductor device as described above, when an oxide film is deposited and planarized by a chemical mechanical polishing process to form a trench, a gate formed on the upper portion of the trench as the edge of the oxide film is lost. There was a problem in that the leakage current of the semiconductor device was increased by causing a hump of the semiconductor device due to a bad pattern, and impurity ions implanted on the semiconductor substrate were diffused due to the heat treatment during the formation of the interlayer insulating film. In addition to the problem of changing the characteristics of the device, there is a problem that the process of filling the polysilicon in the etched region after etching the interlayer insulating film through a photolithography process.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 제조공정을 단순화함과 아울러 전기적특성을 안정화시킬 수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the conventional problems as described above, an object of the present invention is to provide a method of manufacturing a semiconductor device that can simplify the manufacturing process and stabilize the electrical characteristics.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:반도체기판 22:버퍼산화막21: semiconductor substrate 22: buffer oxide film
23:웰 24:질화막23: well 24: nitride film
25:산화막 26:이온주입영역25: oxide film 26: ion implantation region
27:폴리실리콘 28:WSix막27: polysilicon 28: WSix film
29:캡산화막 30:측벽29: cap oxide film 30: side wall
31:플러그It is a plug 31
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자 제조방법의 바람직한 일 실시예는 반도체기판의 상부에 버퍼산화막과 질화막을 형성하는 공정과; 1차 사진식각공정을 통해 필드가 형성될 영역의 질화막, 버퍼산화막 및 반도체기판을 식각한 후, 그 식각된 영역에 산화막을 채워서 트렌치를 형성하는 공정과; 2차 사진식각공정을 통해 게이트가 형성될 영역의 질화막 및 트렌치를 식각한 후, 그 식각된 영역에 게이트를 형성하고 평탄화하는 공정과; 상기 질화막을 제거한 후, 반도체기판의 상부전면에 절연막을 증착하고 선택적으로 식각하여 상기 게이트의 측벽을 형성하는 공정과; 반도체기판의 상부전면에 폴리실리콘을 증착하고 에치백하여 플러그를 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.One preferred embodiment of the semiconductor device manufacturing method for achieving the object of the present invention as described above comprises the steps of forming a buffer oxide film and a nitride film on top of the semiconductor substrate; Etching the nitride film, the buffer oxide film, and the semiconductor substrate in the region where the field is to be formed through a primary photolithography process, and then filling the etched region with an oxide film to form a trench; Etching the nitride film and the trench in the region where the gate is to be formed by a secondary photolithography process, and then forming and planarizing the gate in the etched region; Removing the nitride film, depositing an insulating film on an upper surface of the semiconductor substrate, and selectively etching to form sidewalls of the gate; And depositing polysilicon on the upper surface of the semiconductor substrate and etching back to form a plug.
상기한 바와같은 본 발명에 의한 반도체소자 제조방법의 바람직한 일 실시예를 도2a 내지 도2g에 도시한 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A preferred embodiment of the semiconductor device manufacturing method according to the present invention as described above will be described in detail with reference to the cross-sectional view shown in Figures 2a to 2g.
먼저, 도2a에 도시한 바와같이 반도체기판(21)의 상부에 버퍼산화막(22)을 형성하고 불순물이온을 주입하여 웰(23)을 형성한 후, 그 버퍼산화막(22)의 상부에 질화막(24)을 증착한다. 이때, 질화막(24)은 게이트 높이만큼의 두께로 증착한다.First, as shown in FIG. 2A, a buffer oxide film 22 is formed on the semiconductor substrate 21 and impurity ions are implanted to form a well 23, and then a nitride film () is formed on the buffer oxide film 22. 24) is deposited. At this time, the nitride film 24 is deposited to a thickness equal to the gate height.
그리고, 도2b에 도시한 바와같이 사진식각공정을 통해 상기 질화막(24), 버퍼산화막(22) 및 반도체기판(21)의 일부를 식각한 후, 반도체기판(21)의 상부전면에 산화막(25)을 증착하고 화학기계적 연마공정을 통해 평탄화하여 필드영역에 트렌치를 형성한다.As shown in FIG. 2B, after etching the portions of the nitride film 24, the buffer oxide film 22, and the semiconductor substrate 21 through a photolithography process, the oxide film 25 is formed on the upper surface of the semiconductor substrate 21. ) Is deposited and planarized through a chemical mechanical polishing process to form trenches in the field region.
그리고, 도2c에 도시한 바와같이 상기 트렌치가 형성된 반도체기판(21) 상에 문턱전압을 조절하기 위한 불순물이온을 주입하여 이온주입영역(26)을 형성한 후, 사진식각공정을 통해 게이트가 형성될 영역의 질화막(24) 및 트렌치에 채워진 산화막(25)을 식각한다. 이때, 질화막(24) 및 트렌치에 채워진 산화막(25)은 식각시간을 조절하여 원하는 깊이로 식각한다.As shown in FIG. 2C, the ion implantation region 26 is formed by implanting impurity ions for adjusting the threshold voltage on the trench-formed semiconductor substrate 21 and then forming a gate through a photolithography process. The nitride film 24 and the oxide film 25 filled in the trench are etched. At this time, the oxide film 25 filled in the nitride film 24 and the trench is etched to a desired depth by controlling the etching time.
그리고, 도2d에 도시한 바와같이 상기 반도체기판(21)에 열산화공정을 수행한 후, 상기 식각된 영역에 폴리실리콘(27), WSix막(28) 및 캡산화막(29)의 적층구조를 형성하고, 화학기계적 연마공정을 통해 평탄화하여 게이트를 형성한다. 이때, 폴리실리콘(27)은 자기정렬되는 선택적인 화학기상증착법(self aligned selective CVD)을 통해 식각된 영역에 형성하며, WSix막(28)은 자기정렬되는 실리사이드(self aligned silicide : SALICIDE)공정을 통해 상기 폴리실리콘(27)의 상부에만 형성하며, 캡산화막(29)은 상기 WSix막(28)이 형성된 반도체기판(21)의 상부전면에 증착한 후, 화학기계적 연마공정을 통해 연마하여 형성한다.As shown in FIG. 2D, a thermal oxidation process is performed on the semiconductor substrate 21, and then a stacked structure of the polysilicon 27, the WSix film 28, and the cap oxide film 29 is formed in the etched region. And planarize through a chemical mechanical polishing process to form a gate. In this case, the polysilicon 27 is formed in the etched region through self aligned selective CVD, and the WSix film 28 performs a self aligned silicide (SALICIDE) process. It is formed only on the upper portion of the polysilicon 27, the cap oxide film 29 is deposited on the upper surface of the semiconductor substrate 21 on which the WSix film 28 is formed, and then formed by polishing through a chemical mechanical polishing process .
그리고, 도2e에 도시한 바와같이 상기 질화막(24)을 제거한 후, 반도체기판(21) 상에 불순물이온을 주입하여 소스/드레인영역을 형성한다.After the nitride film 24 is removed as shown in FIG. 2E, impurity ions are implanted onto the semiconductor substrate 21 to form a source / drain region.
그리고, 도2f에 도시한 바와같이 반도체기판(21)의 상부전면에 질화막을 증착하고 선택적으로 식각하여 상기 게이트의 측벽(30)을 형성한다.As shown in FIG. 2F, a nitride film is deposited on the upper surface of the semiconductor substrate 21 and selectively etched to form sidewalls 30 of the gate.
그리고, 도2g에 도시한 바와같이 반도체기판(21)의 상부전면에 폴리실리콘을 증착하고, 에치백하여 플러그(31)를 형성한다.As shown in FIG. 2G, polysilicon is deposited on the upper surface of the semiconductor substrate 21 and etched back to form a plug 31. As shown in FIG.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 산화막의 손실을 차단하여 반도체소자의 누설전류를 감소시킬 수 있는 효과와; 질화막의 제거를 통해 플러그가 패터닝되므로, 층간절연막의 형성공정을 생략할 수 있어 열처리에 따른 반도체소자의 특성변화를 억제함과 아울러 플러그에 폴리실리콘을 채우기가 용이해져서 전체 공정이 단순화되는 효과가 있다.The method of manufacturing a semiconductor device according to the present invention as described above has the effect of reducing the leakage current of the semiconductor device by blocking the loss of the oxide film; Since the plug is patterned by removing the nitride film, the formation process of the interlayer insulating film can be omitted, thereby suppressing the characteristic change of the semiconductor device due to heat treatment, and the polysilicon can be easily filled in the plug, thereby simplifying the overall process. .
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