KR100818084B1 - Transister and method for forming the same - Google Patents

Transister and method for forming the same Download PDF

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Publication number
KR100818084B1
KR100818084B1 KR20050132151A KR20050132151A KR100818084B1 KR 100818084 B1 KR100818084 B1 KR 100818084B1 KR 20050132151 A KR20050132151 A KR 20050132151A KR 20050132151 A KR20050132151 A KR 20050132151A KR 100818084 B1 KR100818084 B1 KR 100818084B1
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South Korea
Prior art keywords
active region
gate
region
forming
formed
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KR20050132151A
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Korean (ko)
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KR20070087844A (en
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김승완
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주식회사 하이닉스반도체
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Abstract

The present invention discloses a transistor and a method of forming the same. The disclosed transistor of the present invention is defined by a device isolation film and includes a semiconductor substrate having an active region in which a central portion of the gate formation region protrudes, a gate formed on a substrate portion including a protrusion of the active region, and formed in an active region on both sides of the gate. And a source / drain region.

Description

Transistor and Formation Method {TRANSISTER AND METHOD FOR FORMING THE SAME}

1 is a plan view of a transistor formed according to the prior art.

2 is a cross-sectional view taken along the line a-a 'of FIG.

3A to 3E are cross-sectional views of processes for describing a method of forming a transistor according to an embodiment of the present invention.

4 is a plan view corresponding to FIG. 3B.

5 is a plan view corresponding to FIG. 3E;

Explanation of symbols on the main parts of the drawings

200: silicon substrate 210: device isolation film

M: mask pattern 215: sidewall insulating film

220: gate insulating film 230: gate conductive film

240: hard mask 250: gate

260: spacer 270: source / drain area

270: spacer 280a: source region

280b: drain region A: active region

The present invention relates to a transistor and a method of forming the same, and more particularly, to a transistor and a method of forming the same that can improve the operating characteristics and refresh characteristics by increasing the effective length of the channel to suppress the short-channel effect.

As semiconductor devices become more integrated, channel lengths and area of junction regions (source / drain regions) of transistors are decreasing, and doping concentrations in channel regions and junction regions are increasing. As a result, the gate's controllability is degraded to cause a short channel effect in which the threshold voltage (Vt) is drastically reduced, and the junction leakage current increases as the electric field increases to refresh. Deterioration of device characteristics is caused, such as deterioration of characteristics.

More specifically, the short channel effect may cause a so-called bit failure in which an undesired gate is turned on during an operation of reading and writing data in a cell region transistor. In the case of a transistor in the peripheral circuit region, the transistor operation speed is abnormally increased, which may cause a malfunction.

1 is a plan view of a semiconductor device formed according to the prior art, and FIG. 2 is a cross-sectional view taken along the line a-a 'of FIG. 1, hereinafter, referring to FIGS. 1 and 2 to form a transistor of the semiconductor device according to the prior art. The method and its problems will be described.

In general, as shown in FIGS. 1 and 2, a transistor of a semiconductor device may include a gate insulating layer 120 and a gate conductive layer on a semiconductor substrate 100 having a device isolation layer 110 defining an active region A. FIG. After forming the film 130 and the hard mask film 140, the gates 150 are formed by etching the films 140, 130, and 120, and spacers 160 are formed on both sidewalls of the gate 150. After the process, the impurities are implanted into the active region A on both sides of the gate 150 including the spacer 160 to form the source / drain region 170.

However, in the above-described conventional technology, as described above, the short channel effect is caused by the high integration of the device as the length of the channel region corresponding to the substrate region under the gate 150 is shortened and the doping concentration of the source / drain regions is increased. There is a problem that the characteristics of the device deteriorate, such as the refresh time is increased.

Accordingly, an object of the present invention is to provide a transistor and a method for forming the same, which are devised to solve the conventional problems as described above, which can suppress short channel effects and improve refresh characteristics by increasing the effective length of a channel. have.

A transistor of the present invention for achieving the above object is a semiconductor substrate defined by an isolation layer, the semiconductor substrate having an active region protruding the center portion of the gate formation region; A gate formed on the substrate portion including the protrusion of the active region; And source / drain regions formed in active regions at both sides of the gate.

Herein, the protrusions of the active region protrude from 200 to 600 mm 3 and have a width of 100 to 400 mm 3.

On the other hand, the method of forming a transistor of the present invention for achieving the above object comprises the steps of providing a silicon substrate having a device isolation film defining an active region; Projecting a central portion of the gate formation region of the substrate active region; Forming a gate on the substrate portion including the protrusion of the active region; And forming a source / drain region in the active regions at both sides of the gate.

The protruding of the central portion of the gate forming region of the substrate active region may include forming a second gate from the central portion of the first gate forming region of the active region on the substrate when two gates are formed on one active region. Forming a mask pattern exposing up to the center of the region; Growing an epitaxial silicon film at a height lower than that of the mask pattern on the exposed portion of the active region; Forming a sidewall insulating film on sidewalls of the mask pattern on which the epitaxial silicon film is not formed; Etching the epi silicon film using the sidewall insulating film and the mask pattern as an etching mask; And removing the sidewall insulating layer and the mask pattern.

The protrusion of the active region protrudes from 200 to 600 mm 3, and has a width of 100 to 400 mm 3.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of the transistor to be implemented in the present invention and its advantages will be briefly described.

The transistor of the present invention is defined by a device isolation film and includes a semiconductor substrate having an active region in which a central portion of the gate formation region protrudes, a gate formed on a portion of the substrate including a protrusion of the active region, and formed in an active region on both sides of the gate. It is composed of source / drain regions, and when the active region portion corresponding to the center portion of the gate formation region is protruded, the channel is bent to increase its effective length, thereby suppressing short channel effects and improving device characteristics. You can. Hereinafter, a method of forming a transistor in the cell region among the transistors having the above structure will be described.

3A to 3E are cross-sectional views of processes for describing a method of forming a transistor according to an embodiment of the present invention.

Referring to FIG. 3A, after the silicon substrate 200 having the device isolation layer 210 defining the active region is provided, a second gate is formed on the substrate 200 from the center of the first gate forming region of the active region. The mask pattern M exposing up to the center portion of the formation region is formed. The mask pattern M may be formed of an oxide film or a nitride film.

Referring to FIG. 3B, the epitaxial silicon film 200 ′ formed by the selective epitaxial growth (SEG) process on the active region exposed by the mask pattern M is lower than the mask pattern M. Grow to height

FIG. 4 is a plan view corresponding to FIG. 3B, in which the epitaxial silicon film 200 ′ is formed at the center of the active region A in the longitudinal direction.

Referring to FIG. 3C, an insulating film of the same material as that of the mask pattern M is conformally formed to a uniform thickness on the entire surface of the substrate product on which the epi silicon film 200 ′ is formed, and the insulating film is anisotropic. The sidewall insulating layer 215 is formed on the sidewall of the mask pattern M where the epitaxial silicon layer 200 ′ is not formed by etching.

Referring to FIG. 3D, the exposed part of the epi silicon layer 200 ′ is etched using the sidewall insulating layer 215 as an etching mask.

As described above, in order to protrude the active region corresponding to the central portion of the gate formation region in the present invention, after forming the mask pattern M exposing the central portion in the longitudinal direction of the active region including the central portion of the gate formation region, An epitaxial silicon film 200 'is formed on a portion of the active region exposed by the mask pattern M and the center portion of the epitaxial silicon film 200' is removed. The reason for this is that it is difficult to form a mask pattern that selectively exposes only the central portion of the gate formation region due to the limitation of the exposure process.

Referring to FIG. 3E, the sidewall insulating layer and the mask pattern are removed by a dry etching process. As a result, an active region protruding from the center portion of the gate formation region is formed, wherein the protrusion of the active region has a rounded shape.

Herein, the protrusions of the active region are formed to protrude from 200 to 600 microseconds and have a width of 100 to 400 microseconds, wherein the width of the protrusions is preferably about 1/3 of the gate line width to be subsequently formed.

Subsequently, gates 250 including a stacked layer of the gate insulating layer 220, the gate conductive layer 230, and the hard mask layer 240 are formed on the substrate portion including the protrusion of the active region. In this case, the gate formed on the left side may be referred to as a first gate, and the gate formed on the right side may be referred to as a second gate.

Next, after the spacers 260 are formed on both sidewalls of the gate 250, impurities are implanted into the active regions on both sides of the gate 250 including the spacers 260 to form the source / drain regions 270. do. As a result, the transistor of the present invention is formed.

FIG. 5 is a plan view corresponding to FIG. 3E, wherein a dotted line inner region shows a protrusion of the active region A, and FIG. 3E is a cross-sectional view taken along the line b-b 'of FIG. 5.

Meanwhile, although the transistor of the cell region for forming two gates in one active region has been described and described in the above embodiments of the present invention, the transistor structure of the present invention has a peripheral circuit for forming one gate in one active region. It is also applicable to transistors in the region.

As described above, the present invention protrudes the active region portion corresponding to the central portion of the gate formation region by a selective epitaxial growth process, and forms the gate 250 on the substrate portion including the protruding active region portion. In this case, since the active region, that is, the channel region, of the substrate corresponding to the lower portion of the gate 250 is curved, the effective length of the channel is increased, thereby improving the threshold voltage margin and effectively preventing the short channel effect. Can be.

Therefore, the present invention can suppress the bit fail of the cell region transistor due to the decrease of the threshold voltage, and prevent the malfunction of the peripheral circuit region transistor, thereby improving the operation characteristics of the device. . In addition, by reducing the leakage current in the off state it is possible to improve the refresh characteristics, and to reduce the power consumption.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention protrudes the active region corresponding to the center portion of the gate predetermined region according to the selective epitaxial growth process, thereby increasing the effective channel length of the transistor, thereby improving the short channel effect and the threshold voltage margin. Can be improved.

Therefore, the present invention can suppress the bit fail of the cell region transistor due to the decrease in the threshold voltage, and prevent the malfunction of the peripheral circuit region transistor, thereby improving the operation characteristics of the device. In addition, the leakage current in the off state can be reduced to improve refresh characteristics and reduce power consumption.

Claims (7)

  1. A semiconductor substrate defined by an isolation layer and having an active region protruding from a center portion of the gate formation region;
    A gate formed on a substrate portion including a protrusion of the active region; And
    And a source / drain region formed in active regions on both sides of the gate.
  2. The transistor of claim 1, wherein the protrusion of the active region protrudes from 200 to 600 microseconds.
  3. The transistor of claim 1, wherein the protrusion of the active region has a width of about 100 to about 400 microseconds.
  4. Providing a silicon substrate having an isolation layer defining an active region;
    Protruding a central portion of the gate formation region of the substrate active region;
    Forming a gate on a substrate portion including a protrusion of the active region; And
    And forming a source / drain region in the active region at both sides of the gate.
  5. The method of claim 4, wherein the projecting of the central portion of the gate forming region of the substrate active region comprises:
    In the case of forming two gates on one active region,
    Forming a mask pattern on the substrate, the mask pattern exposing from the center portion of the first gate formation region to the center portion of the second gate formation region of the active region;
    Growing an epitaxial silicon film at a height lower than a mask pattern on the exposed portion of the active region;
    Forming a sidewall insulating film on sidewalls of the mask pattern on which the epitaxial silicon film is not formed;
    Etching the epi silicon layer using the sidewall insulating layer and the mask pattern as an etching mask; And
    And removing the sidewall insulating layer and the mask pattern.
  6. The method of claim 4, wherein the protrusion of the active region is formed to protrude from 200 to 600 microseconds.
  7. 5. The method of claim 4, wherein the protrusion of the active region is formed to have a width of 100 to 400 microseconds.
KR20050132151A 2005-12-28 2005-12-28 Transister and method for forming the same KR100818084B1 (en)

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KR100818084B1 true KR100818084B1 (en) 2008-03-31

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298543A (en) * 2016-09-30 2017-01-04 无锡宏纳科技有限公司 The manufacture method of the p-type metal-oxide-semiconductor that depletion type grid substrate protrudes
CN106449410A (en) * 2016-09-30 2017-02-22 无锡宏纳科技有限公司 Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040092017A (en) * 2003-04-23 2004-11-03 삼성전자주식회사 Mosfet and method of fabricating the same
KR20050079270A (en) * 2004-02-05 2005-08-10 삼성전자주식회사 Method for fabricating fin field effect transistor and structure thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040092017A (en) * 2003-04-23 2004-11-03 삼성전자주식회사 Mosfet and method of fabricating the same
KR20050079270A (en) * 2004-02-05 2005-08-10 삼성전자주식회사 Method for fabricating fin field effect transistor and structure thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106298543A (en) * 2016-09-30 2017-01-04 无锡宏纳科技有限公司 The manufacture method of the p-type metal-oxide-semiconductor that depletion type grid substrate protrudes
CN106449410A (en) * 2016-09-30 2017-02-22 无锡宏纳科技有限公司 Fabrication method of enhanced N-type MOS (Metal Oxide Semiconductor) transistor with protruding grid substrate

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