CN109786328A

CN109786328A - Semiconductor devices and its manufacturing method

Info

Publication number: CN109786328A
Application number: CN201711106070.5A
Authority: CN
Inventors: 闫德海; 靳颖; 黄海英; 牛健
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-11-10
Filing date: 2017-11-10
Publication date: 2019-05-21

Abstract

The present invention provides a kind of semiconductor devices and its manufacturing method, threshold voltage is carried out to each transistor area using comprehensive ion implantation technology and adjusts ion implanting, to form threshold voltage adjustment layer, adjust the threshold voltage and leakage current of the transistor formed, it can be omitted the ion implanting step for once needing mask plate exposure mask of grid polycrystalline silicon simultaneously, and the common well structure of the first conduction type in the transistor areas such as the low voltage PMOS transistor area of the first well structure alternative semiconductors substrate with the first conduction type can be used, save the technique that the common well structure of the first conduction type in low voltage PMOS transistor is formed with mask plate exposure mask, it is possible thereby to save two lithography mask versions, improve the wasting of resources, simplify technique.

Description

Semiconductor devices and its manufacturing method

Technical field

The present invention relates to ic manufacturing technology field more particularly to a kind of semiconductor devices and its manufacturing methods.

Background technique

In existing certain semiconductor devices, generally require to be provided simultaneously with following five transistorlike: low pressure PMOS crystal Manage (Low Voltage P Metal Oxide Semiconductor, LVPMOS), low voltage nmos transistor (LVNMOS), in Press N-type lateral direction bilateral diffusion MOS transistor (Medium Voltage N Lateral Diffusion MOS, MVN-LDMOS), in Press middle pressure N-type ldmos transistor (the ISO MVN- of p-type lateral direction bilateral diffusion MOS transistor (MVP-LDMOS) and isolation LDMOS).In the manufacturing process of these semiconductor devices, usually require to carry out the injection of N trap (NW IMP) to form N trap (nwell, NW), but actually only have LVPMOS that can use the N trap to be formed, it is clear that cause the wasting of resources；In addition, being The resistance of adjustment grid polycrystalline silicon, these five types of transistors require to carry out ion implanting (GPIMP) to its polysilicon gate, by This makes technique become relative complex.

Summary of the invention

It is an object of the invention to a kind of semiconductor devices and its manufacturing methods, can improve the wasting of resources, simplify technique.

To achieve the goals above, the present invention provides a kind of manufacturing method of semiconductor devices, comprising the following steps:

The semiconductor substrate for having multiple transistor areas, the lining of semiconductor described in the ion pair using the first conduction type are provided Bottom carries out the first trap ion implanting, to form first well structure with the first conduction type at least in a transistor area；

Semiconductor substrate described in ion pair using the second conduction type carries out the second trap ion implanting, at least at one Second well structure with the second conduction type is formed in transistor area；

Threshold voltage is carried out to each transistor area using comprehensive ion implantation technology and adjusts ion implanting, to be formed Threshold voltage adjustment layer；

Corresponding gate stack structure is formed on the surface of each transistor area；

Source region and drain region are formed in the semiconductor substrate of each gate stack structure two sides, in each crystalline substance Body area under control forms corresponding transistor.

Optionally, before the second trap ion implanting of the progress of the semiconductor substrate described in the ion pair using the second conduction type Or later, corresponding field oxygen isolation structure is formed using field oxygen isolation technology, to define the active area of each transistor area.

Optionally, using each transistor area of the ion pair of first conduction type carry out threshold voltage adjust from Son injection, forms the threshold voltage adjustment layer with the active area surface layer in each transistor area.

Optionally, the Implantation Energy of the threshold voltage adjustment ion implanting is 50KeV~200KeV, and implantation dosage is 1.0E10/cm²~1.0E12/cm²。

Optionally, include: the step of forming corresponding gate stack structure on the surface of each transistor area

Gate dielectric layer and polysilicon layer are sequentially formed on the surface of the semiconductor substrate；

Ion implanting is carried out to the polysilicon layer using comprehensive ion implantation technology, to adjust the electricity of the polysilicon layer Resistance, the resistance value for the polysilicon resistance for being subsequently formed the resistance value of the polysilicon layer；

The polysilicon layer and the gate dielectric layer are performed etching, to be formed simultaneously the gate stack structure and more Crystal silicon resistance.

Optionally, after forming the source region and drain region, by the gate stack structure at least one transistor area surface Metal gate stack structures are replaced with, the metal gate stack structures include the high K grid stacked gradually on the surface of transistor area Dielectric layer and metal gate electrode layer.

Optionally, after forming the source region and drain region, in the source region, drain region, gate stack structure and polysilicon Metal silicide and the metal contact hole with metal silicide electrical contact are formed on the surface of resistance.

Optionally, the transistor formed in the semiconductor substrate include low voltage PMOS transistor, low voltage nmos transistor, Middle pressure N-type lateral direction bilateral diffusion MOS transistor, middle pressure p-type lateral direction bilateral diffusion MOS transistor and the middle pressure N-type LDMOS of isolation are brilliant At least two in body pipe.

It optionally, include the transistor area for being used to form the low voltage PMOS transistor, shape in the multiple transistor area At the low voltage PMOS transistor include: first well structure being formed in the transistor area；It is formed in described One threshold voltage adjustment layer on the first well structure surface layer；The grid being formed on the threshold voltage adjustment layer surface Pole stacked structure；And it is formed in the source region in first well structure of the gate stack structure two sides and drain region.

It optionally, include the transistor area for being used to form the low voltage nmos transistor, shape in the multiple transistor area At the low voltage nmos transistor include: second well structure being formed in the transistor area；It is formed in described One threshold voltage adjustment layer on the second well structure surface layer；The grid being formed on the threshold voltage adjustment layer surface Pole stacked structure；And it is formed in the source region in second well structure of the gate stack structure two sides and drain region.

It optionally, include being used to form medium pressure N-type lateral direction bilateral diffusion MOS transistor in the multiple transistor area The medium pressure N-type lateral direction bilateral diffusion MOS transistor of transistor area, formation includes: to be laterally distributed in the transistor area One first well structure and second well structure have certain between first well structure and second well structure Interval, first well structure are equipped with an oxygen isolation structure close to the side of second well structure；From the first trap knot Structure surface layer extends to a threshold voltage adjustment layer on second well structure surface layer；It is formed in the threshold voltage adjustment layer surface On a gate stack structure, described gate stack structure one end is located at the top of second well structure, other end position In the top of the field oxygen isolation structure；And it is respectively formed at the source in second well structure and first well structure Area and drain region, the source region and drain region are lived apart the two sides of the gate stack structure.

It optionally, include being used to form medium pressure p-type lateral direction bilateral diffusion MOS transistor in the multiple transistor area Transistor area, the medium pressure p-type lateral direction bilateral diffusion MOS transistor of formation include: the institute being formed in the transistor area State the first well structure；Be formed in first well structure, second well structure；It is formed in second well structure An oxygen isolation structure；The threshold value electricity on second well structure surface layer is extended to from the surface layer of first well structure Press adjustment layer；The gate stack structure being formed on the threshold voltage adjustment layer surface, the gate stack structure One end is located at the top of first well structure on the outside of second well structure, and the other end is located at the field oxygen isolation structure Top；And be respectively formed at drain region in the first well structure on the outside of second well structure and second well structure and Source region, the source region and drain region are lived apart the two sides of the gate stack structure.

It optionally, include the crystalline substance for being used to form the middle pressure N-type ldmos transistor of the isolation in the multiple transistor area Body area under control, the middle pressure N-type ldmos transistor of the isolation of formation include: one described be formed in the transistor area One well structure；Be formed in first well structure, second well structure；It is formed on the outside of second well structure An oxygen isolation structure in first well structure；The one of second well structure surface layer is extended to from first well structure surface layer Threshold voltage adjustment layer；The gate stack structure being formed on the threshold voltage adjustment layer surface, the grid pile Stack structure one end is located at the top of second well structure, and the other end is located at the top of the field oxygen isolation structure；And respectively Be formed in source region and drain region in the first well structure on the outside of second well structure and second well structure, the source region and Drain region is lived apart the two sides of the gate stack structure.

The present invention also provides a kind of semiconductor devices, comprising:

Semiconductor substrate with multiple transistor areas；

The first well structure with the first conduction type is formed at least in a transistor area；

The second well structure with the second conduction type is formed at least in a transistor area；

Threshold voltage adjustment layer is formed in the first well structure of each transistor area and/or the table of the second well structure Layer；

Gate stack structure is formed on the surface of the threshold voltage adjustment layer of each transistor area；

Source region and drain region are formed in the semiconductor substrate of the gate stack structure two sides of each transistor area.

Optionally, the multiple transistor area is used to form low voltage PMOS transistor, low voltage nmos transistor, middle pressure N-type In the middle pressure N-type ldmos transistor of lateral direction bilateral diffusion MOS transistor, middle pressure p-type lateral direction bilateral diffusion MOS transistor and isolation At least two transistors.

It optionally, include being used to form medium pressure N-type lateral direction bilateral diffusion MOS transistor in the multiple transistor area The medium pressure N-type lateral direction bilateral diffusion MOS transistor of transistor area, formation includes: to be laterally distributed in the transistor area One first well structure and second well structure have certain between first well structure and second well structure Interval, first well structure are equipped with an oxygen isolation structure close to the side of second well structure；From the first trap knot Structure surface layer extends to the threshold voltage adjustment layer on second well structure surface layer；It is formed in the threshold voltage adjustment layer A gate stack structure on surface, described gate stack structure one end is located at the top of second well structure, another End is located at the top of the field oxygen isolation structure；And it is respectively formed in second well structure and first well structure Source region and drain region, the source region and drain region live apart the two sides of the gate stack structure.

Compared with prior art, technical solution of the present invention has the advantages that

1, threshold voltage is carried out to each transistor area using comprehensive ion implantation technology and adjusts ion implanting, carry out shape At threshold voltage adjustment layer, the threshold voltage and leakage current of the transistor of formation are adjusted, while grid polycrystalline silicon can be reduced The ion implanting step of mask plate exposure mask is once needed, technique, save the cost are simplified；

It 2, further include middle pressure N-type lateral direction bilateral diffusion MOS (MVN- when the semiconductor devices includes low voltage PMOS transistor LDMOS) the middle pressure N-type LDMOS crystal of transistor, middle pressure p-type lateral direction bilateral diffusion MOS (MVP-LDMOS) transistor and isolation When at least one of (the MVN ISO-LDMOS) of pipe transistor, deeper tool can be formed in these transistor areas simultaneously There are the first well structure (i.e. deep trap structure) of the first conduction type, i.e., the first trap knot formed in low voltage PMOS transistor area Structure be used to substitute the first shallower conduction type in original low voltage PMOS transistor area common well structure (its depth with Second well structure is suitable), thus cancel the forming step of the common trap of first conduction type, it is conductive to have saved described first The lithography mask version of the common trap of type improves depositing for the common trap because of the first conduction type described in low voltage PMOS transistor And caused by the wasting of resources, simplify technique.

Detailed description of the invention

Figure 1A is a kind of the schematic diagram of the section structure of LVPMOS transistor；

Figure 1B is a kind of the schematic diagram of the section structure of LVNMOS transistor；

Fig. 1 C is a kind of the schematic diagram of the section structure of MVN-LDMOS transistor；

Fig. 1 D is a kind of the schematic diagram of the section structure of MVP-LDMOS transistor；

Fig. 1 E is a kind of the schematic diagram of the section structure of MVN ISO-LDMOS transistor；

Fig. 2 is the manufacturing method flow chart of the semiconductor devices of the specific embodiment of the invention；

Fig. 3 A is the schematic diagram of the section structure of the LVPMOS transistor of manufacturing method production shown in Fig. 2；Fig. 3 B is Fig. 2 institute The schematic diagram of the section structure of the LVNMOS transistor for the manufacturing method production shown；

Fig. 3 C is the schematic diagram of the section structure of the MVN-LDMOS transistor of manufacturing method production shown in Fig. 2；

Fig. 3 D is the schematic diagram of the section structure of the MVP-LDMOS transistor of manufacturing method production shown in Fig. 2；

Fig. 3 E is the schematic diagram of the section structure of the MVN ISO-LDMOS transistor of manufacturing method production shown in Fig. 2.

Specific embodiment

As described in the background art, certain semiconductor devices need to be provided simultaneously with LVPMOS transistor, LVNMOS crystal Pipe, MVN-LDMOS transistor, MVP-LDMOS transistor and MVN ISO-LDMOS transistor these fifth types transistor, please refer to The manufacturing method of Figure 1A to 1E, these semiconductor devices generally include following steps:

Firstly, providing the P-type semiconductor substrate having there are five transistor area, hot oxygen can be passed through on semiconductor substrate surface Chemical industry skill forms one layer of lining oxide layer (not shown), to protect semiconductor substrate；In order to facilitate signal, Figure 1A to 1E is shown respectively Structure on five transistor areas and its surface；Five transistor areas are respectively the crystalline substance for being used to form LVPMOS transistor Body area under control 100a, the transistor area 100b for being used to form LVNMOS transistor, the transistor for being used to form MVN-LDMOS transistor Area 100c, the transistor area 100d for being used to form MVP-LDMOS transistor and it is used to form MVN ISO-LDMOS transistor Transistor area 100e；

Then, deep N-well (Deep N Well, DNW) is prepared, i.e., light is carried out using DNW lithography mask version (DNW mask) It carves, to carry out phosphorus Plasma inpouring in transistor area 100c, 100d, 100e, simultaneously in transistor area 100c, 100d, 100e It is middle to form corresponding DNW, specifically, DNW 101c is formed in the 100c of transistor area, forms DNW in the 100d of transistor area 101d forms DNW 101e in the 100e of transistor area；

Then, active area (AA) is defined, i.e., lithography and etching is carried out using active area lithography mask version (AA mask), with It defines corresponding active area in transistor area 100a, 100b, 100c, 100d, 100e, and is formed and adjacent have for being isolated The field oxygen isolation structure of source region, midfield oxygen isolation structure can be fleet plough groove isolation structure (STI)；

Then, N trap (N Well) is prepared, i.e., photoetching is carried out using NW lithography mask version (NW mask), in transistor area 100a carries out phosphorus Plasma inpouring (i.e. N trap injects, NW IMP), to form NW 101a in the 100a of transistor area；

Then, p-well (P Well) is prepared, i.e., photoetching is carried out using PW lithography mask version (PW mask), in transistor area 100b, 100c, 100d, 100e carry out boron Plasma inpouring, to be formed in transistor area 100b, 100c, 100d, 100e simultaneously Corresponding PW specifically forms PW 101b in the 100b of transistor area；PW 105c, PW are formed in the 100c of transistor area 105c and DNW 101c is laterally distributed in the 100c of transistor area and has certain intervals (as schemed between PW105c and DNW 101c 2 microns shown in 1C)；PW 105d is formed in the DNW 101d of transistor area 100d；The DNW of 100e in transistor area PW 105e is formed in 101e；

Then, polysilicon resistance (HighResistancePolysilicon, HRP) is prepared, i.e., in entire semiconductor substrate It deposits silica and polysilicon layer on surface, and comprehensive the is carried out to the polysilicon layer using comprehensive ion implantation technology Primary ions injection, to adjust the resistance of the polysilicon layer, the polycrystalline for being subsequently formed the resistance value of the polysilicon layer The resistance value of silicon resistor；,

Then, carry out polysilicon gate ion implanting (GPIM), i.e., using corresponding gate mask version (gate mask) into Row photoetching to define the forming region of grid polycrystalline silicon in the polysilicon layer, and uses second of ion implantation technology The polysilicon layer of the forming region of grid polycrystalline silicon is doped, to adjust the resistance of grid polycrystalline silicon, wherein the grid Polysilicon is divided into P-type grid electrode polysilicon and N-type grid polycrystalline silicon, the P-type grid electrode polysilicon and the N-type grid polycrystalline silicon The process requirement of photoetching and second of ion implanting separately carries out, second of ion implanting of the P-type grid electrode polysilicon Impurity is p type impurity, and the impurity of second of ion implanting of the N-type grid polycrystalline silicon is N-type impurity.Specifically, P is first used The region that type grid polycrystalline silicon lithography mask version (P Gatepoly mask) lithographic definition goes out P-type grid electrode polysilicon (is covered on Partial polysilicon layer above transistor area 100a and 100d), and second of P-type ion injection is carried out, p type impurity is injected Into the polysilicon layer in the region of P-type grid electrode polysilicon；N-type grid polycrystalline silicon lithography mask version (N is used again Gatepoly mask) lithographic definition goes out the region of N-type grid polycrystalline silicon and (is covered on transistor area 100b, 100c, 100e The partial polysilicon layer of side), and second of N-type ion injection is carried out, N-type impurity is injected into the area of N-type grid polycrystalline silicon In the polysilicon layer in domain；Alternatively, first defining the region of N-type grid polycrystalline silicon using photoetching process, and carry out second of N Type ion implanting, N-type impurity is injected into the polysilicon layer in the region of N-type grid polycrystalline silicon, then uses photoetching work Skill defines the region of P-type grid electrode polysilicon, and carries out second of P-type ion injection, and p type impurity is injected into P-type grid electrode In the polysilicon layer in the region of polysilicon；

Then, polysilicon gate stacked structure (GP) is prepared, i.e., light is carried out using gate lithography mask plate (gate mask) It carves and etches, while defining polysilicon gate stacked structure (polysilicon gate including silica and its top) and polycrystalline Silicon resistor, specifically, the polysilicon gate extremely 102a in the polysilicon gate stacked structure formed on the surface 100a of transistor area, Polysilicon gate extremely 102b in the polysilicon gate stacked structure formed on the surface 100b of transistor area, transistor area 100c table Polysilicon gate extremely 102c in the polysilicon gate stacked structure formed on face, the polycrystalline formed on the surface 100d of transistor area Polysilicon gate extremely 102d in silicon gate stacked structure, the polysilicon gate stacked structure formed on the surface 100e of transistor area In polysilicon gate extremely 102e；

Then, source region and drain region are prepared, i.e., carries out source in the transistor area of each polysilicon gate stacked structure two sides Ion implanting is leaked, forms corresponding source region and drain region, wherein the technique of NMOS transistor and PMOS transistor source and drain ion implanting It needs to separate progress, specifically, transistor area 100a and 100d is first gone out using corresponding lithography mask version lithographic definition, and with crystalline substance Polysilicon gate 102a and 102d are exposure mask in body area under control 100a and 100d, NW101a to the two sides polysilicon gate 102a and The transistor area 100d (side is DNW 101d, and the other side is PW 105d) of the two sides polysilicon gate 102d carries out P-type ion note Enter, to form the source region 103a and drain region 104a of the separation two sides polysilicon gate 102a, the shape in DNW 101d in NW101a At source region 103d, drain region 104d is formed in PW105d, LVPMOS transistor and MVP-LDMOS transistor is consequently formed, The channel length of LVPMOS transistor is 1 μm, is 2 μm at a distance from source region 103d and PW 105d in MVP-LDMOS transistor；So Afterwards, transistor area 100b, 100c and 100e are gone out using corresponding lithography mask version lithographic definition, and with transistor area 100b, Polysilicon gate 102b, 102c and 102e are exposure mask in 100c and 100e, to PW 101b of the two sides polysilicon gate 102b, more The transistor area 100c (side is DNW 101c, and the other side is PW 105c) and polysilicon gate of the two sides polysilicon gate 102c The transistor area 100e (side is DNW 101e, and the other side is PW 105e) of the two sides 102e carries out N-type ion injection, in PW The source region 103b and drain region 104b that the separation two sides polysilicon gate 102b are formed in 101b, form source region 103c in PW105c, Drain region 104c is formed in DNW 101c, forms source region 103e in PW105e, drain region 104e is formed in DNW 101e, thus Form LVNMOS transistor, MVN-LDMOS transistor and MVN ISO-LDMOS transistor, the ditch road length of LVNMOS transistor Degree is 1 μm, and source region 103c and its distance between boundary of PW 105c closely are 2 μm in MVN-LDMOS transistor, MVN The distance between source region 103e and its boundary of PW 105e closely are 1.5 μm in ISO-LDMOS transistor；

Later, contact hole (CT) and metal interconnection structure (TM) can be made, each transistor that will be formed carries out Corresponding electrical connection, to complete the manufacture of semiconductor devices.

In the manufacturing method of above-mentioned semiconductor devices, need by N trap inject (NW IMP) come formed N trap (nwell, NW), actually only have LVPMOS that can use the N trap to be formed, it is clear that cause the wasting of resources；In addition, in order to adjust The resistance of grid polycrystalline silicon also needs to carry out the second ion implanting to the polysilicon of area of grid after preparing polysilicon resistance (GPIMP), so that technique becomes relative complex.

Based on this, the present invention proposes a kind of semiconductor devices and its manufacturing method, can cancel the injection of N trap and to gate regions The polysilicon in domain carries out the second ion implanting, to save at least two lithography mask versions, simplifies technique, save the cost.

To be clearer and more comprehensible the purpose of the present invention, feature, a specific embodiment of the invention is made with reference to the accompanying drawing Further instruction, however, the present invention can be realized with different forms, it should not be to be confined to the embodiment described.

Referring to FIG. 2, the present invention provides a kind of manufacturing method of semiconductor devices, comprising the following steps:

S1 provides the semiconductor substrate with multiple transistor areas, partly leads described in the ion pair using the first conduction type Body substrate carries out the first trap ion implanting, to form the first trap knot with the first conduction type at least in a transistor area Structure；

S2, semiconductor substrate described in the ion pair using the second conduction type carries out the second trap ion implanting, at least to exist Second well structure with the second conduction type is formed in one transistor area, and second well structure is shallower than first trap Structure；

S3 carries out threshold voltage to each transistor area using comprehensive ion implantation technology and adjusts ion implanting, with Form threshold voltage adjustment layer；

S4 forms corresponding gate stack structure on the surface of each transistor area；

S5 forms source region and drain region, in each institute in the semiconductor substrate of each gate stack structure two sides It states transistor area and forms corresponding transistor.

Fig. 3 A to Fig. 3 E is please referred to, in step sl, firstly, providing a semiconductor substrate with multiple transistor areas (P-SUB in such as Fig. 3 A to Fig. 3 E), the semiconductor substrate can be any semiconductor material well known to those skilled in the art Material, this semiconductor material may include but be not limited to: Si (silicon), SiC (carbon silicon), SiGe (germanium silicon), SiGeC (carbon germanium silicon), Ge are closed Gold, GeAs (arsenic germanium), InAs (indium arsenide), InP (indium phosphide) and other III-V or group Ⅱ-Ⅵ compound semiconductor.Partly lead Body substrate 300 is not limited to body material, can also include epitaxial layer (epitaxy Si Ge in such as Si substrate) or layered semiconductor (as absolutely Silicon SOI on edge body, SiGe etc. on insulator).The size of semiconductor substrate, which is capable of providing, multiple is used to form different types of crystalline substance The transistor area of body pipe, the multiple transistor area can be selected from transistor area 300a at least two into 300e, wherein brilliant Body area under control 300a is used to form LVPMOS transistor, and transistor area 300b is used to form LVNMOS transistor, transistor area 300c It is used to form MVN-LDMOS transistor, transistor area 300d is used to form MVP-LDMOS transistor, and transistor area 300e is used for Form MVN ISO-LDMOS transistor.The conduction type of semiconductor substrate can be p-type (i.e. the second conduction type).

Please continue to refer to Fig. 3 A to Fig. 3 E, in step sl, then, the first trap knot with the first conduction type is prepared Structure, that is, thermal oxidation technology etc. can be first passed through and form the first hard mask layer on semiconductor substrate surface, the first hard mask layer Material can be silicon oxide or silicon nitride；Then, the first photoresist layer is coated on the surface of the first hard mask layer, and using deep Trap lithography mask version (for example, DNW mask) such as is exposed to the first photoresist layer, develops at the photoetching treatments, to form first Pattern photoresist；Then, using the first patterning photoresist as exposure mask, the first hard mask layer of etching to semiconductor substrate surface, To expose corresponding transistor area surface, the first trap ion implanting opening is formed；Then, the first patterning of removal photoresist, And the first trap ion is carried out using the semiconductor substrate in the opening of the first trap ion implanting described in the ion pair of the first conduction type Injection, to form first well structure with the first conduction type in corresponding transistor area, first well structure is deep Identical the second common well structure of well structure, i.e. its propulsion depth in the semiconductor substrate is deep, for example, using phosphorus, The N-type ions such as arsenic carry out ion implanting to transistor area 300a, 300c, 300d, 300e, to be formed simultaneously following first well structure (DNW) at least two in: the first well structure (DNW) 301a in the 300a of transistor area, it is located in the 300c of transistor area The first well structure (DNW) 301c, be located at transistor area 300d in the first well structure (DNW) 301d and be located at transistor area 300e In the first well structure (DNW) 301e.First well structure (DNW) is capable of forming potential barrier, to avoid the semiconductor in its underpart Substrate generate charge flow into top formed transistor in, avoid it is compound between charge and hole, reduce by charge with Crosstalk between the transistor that machine drift generates.First well structure can be about 3 μm~10 μm of the surface from semiconductor substrate Depth has maximum concentration, and can have about 1 μm~5 μm of thickness.The first hard mask layer can be removed later.Work as institute Stating semiconductor devices includes low voltage PMOS transistor, further include middle pressure N-type lateral direction bilateral diffusion MOS (MVN-LDMOS) transistor, in Press (the MVN ISO- of the middle pressure N-type ldmos transistor of p-type lateral direction bilateral diffusion MOS (MVP-LDMOS) transistor and isolation At least one of) LDMOS when transistor, can be formed in these transistor areas simultaneously deeper has the first conduction type The first well structure (i.e. deep trap structure), i.e., this step compare prior art, for making the transistor area of LVPMOS transistor First well structure (as shown in the 301a in Fig. 3 A) formed in (300a in Fig. 3 A) is used to substitute originally shallower The first conduction type common well structure (its depth is relatively shallower, as shown in the 101a in Figure 1A), such as with deep N-well structure (DNW) original N trap (NW) is replaced, the formation step of the common trap (for example, NW) of first conduction type is thus eliminated Suddenly, the lithography mask version for having saved the common trap (for example, NW) of first conduction type, improves because of low pressure PMOS crystal The presence of the common trap of first conduction type described in pipe and caused by the wasting of resources, simplify technique.

Please continue to refer to Fig. 3 A to Fig. 3 E, in step s 2, second well structure with the second conduction type is prepared, that is, First the second hard mask layer and the second photoresist layer are formed on semiconductor substrate surface, then using trap lithography mask version (such as Photoetching is carried out to second photoresist layer for PW mask), to form the second patterning photoresist；Then, with the second patterning Photoresist is exposure mask, the second hard mask layer of etching to semiconductor substrate surface, to expose corresponding transistor area surface, is formed Second trap ion implanting opening；Then, the second patterning of removal photoresist, and using the described in the ion pair of the second conduction type Semiconductor substrate in two trap ion implantings opening carries out the second trap ion implanting, has to be formed in corresponding transistor area Second well structure of the second conduction type, and the depth (i.e. second of the second well structure (PW) 305d with the second conduction type The propulsion depth of conductive type ion in the semiconductor substrate) than having the depth of the first well structure (DNW) of the first conduction type Spend (i.e. the propulsion depth of the first conductive type ion in the semiconductor substrate) shallowly, thus the second trap knot in certain transistor areas Structure is formed directly into the first well structure.For example, using P-type ions such as boron, indiums to transistor area 300b, 300c, 300d, 300e Carry out ion implanting, be formed simultaneously in following well structure (PW) at least two: the second trap in the 300b of transistor area Structure (PW) 301b, the second well structure (PW) 305c, the first trap positioned at transistor area 300d in the 300c of transistor area The second well structure (PW) 305d in structure 301d and the second trap knot in the first well structure 301e of transistor area 300e Structure (PW) 305e, wherein the second well structure (PW) 305c and the first well structure 301c in the 300c of transistor area are laterally distributed in In the 300c of transistor area and between the two with certain intervals.The second hard mask layer can be removed later.

It should be noted that can before or after step S2, using field oxygen isolation technology formed corresponding field oxygen every From structure (FOX), to define the active area (AA) of each transistor area, the field oxygen isolation technology can be shallow trench isolation (STI) (LOCOS) technique is isolated in technique, local field oxygen.Specifically, it is covered firmly firstly, forming third on semiconductor substrate surface Film layer (not shown) simultaneously coats third photoresist layer on third hard mask layer surface；Then active area lithography mask version is used (AA mask) carries out photoetching to the third photoresist layer, to form third patterning photoresist；Then, it is patterned with third Photoresist is exposure mask, the semiconductor substrate of etching third hard mask layer to partial depth, to form multiple grooves being spaced apart； Then, removal third patterns photoresist, and forms silicon dioxide layer in flute surfaces using the methods of thermal oxide；Then, lead to The modes such as chemical vapor deposition are crossed, the depositing isolation material in silicon dioxide layer and third hard mask layer surface, and material is isolated Material fills groove；Later, using the modes such as chemical mechanical grinding remove semiconductor substrate isolated material and third it is hard Mask layer etc. is consequently formed shallow trench isolation (STI) structure for defining each transistor area active area and is located at crystal Field oxygen isolation structure in area under control, for example, the sti structure that transistor area 300a to 300e passes through boundary respectively is adjacent with left and right Device area keep apart, meanwhile, the first well structure 301c (i.e. the first well structure 301c not formed of transistor area 300c The part of two well structure 305c) close to the side of the second well structure 305c it is also formed with an oxygen isolation structure 307c, transistor The second well structure 305d of area 300d is close to the first well structure 301d (i.e. not formed second well structure 305d of the first well structure 301d Part) side be also formed with first well structure 301e (i.e. the first trap of oxygen an isolation structure 307d, transistor area 300e The part of the not formed second well structure 305e of structure 301e) close to the side of the second well structure 305e it is also formed with the isolation of oxygen Structure 307e.

Please continue to refer to Fig. 3 A to Fig. 3 E, in step s3, prepare threshold voltage adjustment layer (VTP), i.e., using comprehensively from Sub- injection technology carries out comprehensive ion implanting to the semiconductor substrate, and the conduction type of the ion of injection is the first conductive-type Thus type forms threshold voltage adjustment layer on the active area surface layer of each transistor area, to adjust the threshold of transistor to be formed Threshold voltage.For example, using implantation dosage for 1.0E10/cm²~1.0E12/cm²The N-type ions such as phosphorus, arsenic, and be aided with 50KeV~ The Implantation Energy of 200KeV carries out comprehensive ion implanting to the semiconductor substrate, to be formed simultaneously with lower threshold voltages tune Flood: positioned at the active area (i.e. the first well structure 301a between two STI of transistor area 300a or so) of transistor area 300a Surface layer threshold voltage adjustment layer 306a, positioned at active area (i.e. two STI of transistor area 300b or so of transistor area 300b Between the first well structure 301b) surface layer threshold voltage adjustment layer 306b, the active area positioned at transistor area 300c is (i.e. brilliant The STI in region and field oxygen isolation structure 307c and right side on the left of the 300c of body area under control between STI and field oxygen isolation structure 307c Between the first well structure 301c) surface layer threshold voltage adjustment layer 306c, the active area positioned at transistor area 300d is (i.e. brilliant The STI in region and field oxygen isolation structure 307d and right side on the left of the 300d of body area under control between STI and field oxygen isolation structure 307d Between the second well structure 305d) surface layer threshold voltage adjustment layer 306d, the active area positioned at transistor area 300e is (i.e. brilliant The STI in region and field oxygen isolation structure 307e and right side on the left of the 300e of body area under control between STI and field oxygen isolation structure 307e Between the first well structure 301e) surface layer threshold voltage adjustment layer 306e.

Please continue to refer to Fig. 3 A to Fig. 3 E, in step s 4, gate stack structure is prepared, that is, first in the semiconductor The gate dielectric layers such as silica, and deposit polycrystalline silicon (poly) layer on the surface of gate dielectric layer are formed on substrate surface；Then, Comprehensive primary ions injection (HRP) is carried out to the polysilicon layer using comprehensive ion implantation technology, which will be from Son is injected into the polysilicon layer and adjusts the resistance of the polysilicon layer, makes the subsequent shape of the resistance value of the polysilicon layer At polysilicon resistance resistance value；Then, the 4th hard mask layer and the 4th photoresist are formed on the polysilicon layer surface Layer, and photoetching is carried out to the 4th photoresist layer using gate lithography mask plate (gate mask), it is more to define grid with formation 4th patterning photoresist of the forming region of crystal silicon；Then, it using the 4th patterning photoresist as exposure mask, etches described more Crystal silicon layer and gate dielectric layer, with formed polysilicon gate stacked structure (polysilicon gate including gate dielectric layer and its top) and Polysilicon resistance, specifically, the polysilicon gate in polysilicon gate stacked structure formed on the surface 300a of transistor area is extremely 302a, the polysilicon gate extremely 302b in polysilicon gate stacked structure formed on the surface 300b of transistor area, transistor area Polysilicon gate extremely 302c in the polysilicon gate stacked structure formed on the surface 300c, transistor area are formed on the surface 300d Polysilicon gate stacked structure in polysilicon gate extremely 302d, the polysilicon gate heap formed on the surface 300e of transistor area Polysilicon gate extremely 302e in stack structure.And the extremely one end 302c of the polysilicon gate above the 300c of transistor area is covered on part The top of second well structure 305c, the other end are covered on the top of part oxygen isolation structure 307c；Above the 300d of transistor area Polysilicon gate extremely one end 302d be covered on part the first well structure 301d (i.e. the second trap be not formed in the first well structure 301d The region of structure 305d, in other words the first well structure 301d not by the second well structure 305d cover region) top, the other end It is covered on the top of part oxygen isolation structure 307d；Polysilicon gate extremely one end 302e above the 300e of transistor area is covered on The top of part the second well structure 301e, the other end are covered on the top of part oxygen isolation structure 307e.Each in this step The gate stack structure formed on a transistor area surface is not by the first well structure and the second well structure in the transistor area All coverings, and the technique that polysilicon gate is formed in this step compares prior art, and the polysilicon layer as grid is omitted Second of ion implanting, save one for grid polycrystalline silicon the second ion implanting lithography mask version, simplify work Skill reduces costs.

Please continue to refer to Fig. 3 A to Fig. 3 E, in step s 5, N-type transistor (NMOS) and P-type transistor are prepared respectively (PMOS) the preparation sequence of source region and drain region, the source region and drain region of N-type transistor (NMOS) and P-type transistor (PMOS) is not done It is specific to limit.For example, first forming the 5th photoresist layer on the surfaces such as semiconductor substrate and polysilicon gate, and using corresponding The 5th photoresist layer of lithography mask version photoetching to define transistor area 300a and 300d；Then, with the 5th light after photoetching Polysilicon gate 302a and 302d are exposure mask in photoresist layer and transistor area 300a and 300d, to the two sides polysilicon gate 302a (side is the first well structure 301d to the transistor area 300d of first well structure 301a and the two sides polysilicon gate 302d, another Side is the second well structure 305d) P-type ion injection is carried out, to form separation polysilicon gate 302a in the first well structure 301a The source region 303a and drain region 304a of two sides form source region 303d, the shape in the second well structure 305d in the first well structure 301d At drain region 304d, LVPMOS transistor and MVP-LDMOS transistor is consequently formed, the channel length drawing of LVPMOS transistor is 1.5 μm, source region 303d is 2 μm at a distance from the second well structure (PW) 305d in MVP-LDMOS transistor；Then, the 5th is removed Photoresist layer, and the 6th photoresist layer is formed on the surfaces such as semiconductor substrate and polysilicon gate, and use corresponding light The 6th photoresist layer of mask plate photoetching is carved to define transistor area 300b, 300c and 300e, and with the 6th photoetching after photoetching Polysilicon gate 302b, 302c and 302e are exposure mask in glue-line and transistor area 300b, 300c and 300e, to polysilicon gate The second well structure (PW) 301b of the two sides 302b, the two sides polysilicon gate 302c transistor area 300c (side is the first trap knot Structure 301c, the other side are the second well structure 305c) and (side first transistor area 300e of the two sides polysilicon gate 302e Well structure 301e, the other side are the second well structure 305e) N-type ion injection is carried out, with the shape in the second well structure (PW) 301b The source region 303b and drain region 304b of the two sides ingredient polysilicon gate 302b in the majority form source region in the second well structure (PW) 305c 303c forms drain region 104c in the first well structure (DNW) 301c, and source region 103e is formed in the second well structure (PW) 305e, In the first well structure (DNW) 301e formed drain region 304e, be consequently formed LVNMOS transistor, MVN-LDMOS transistor and MVN ISO-LDMOS transistor, the channel length of LVNMOS transistor can be 1.5 μm, source region 303c in MVN-LDMOS transistor The distance between its boundary of the second well structure (PW) 305c closely is 2.5 μm, source region in MVN ISO-LDMOS transistor The distance between 303e and its boundary of the second well structure (PW) 305e closely are 1.7 μm.Wherein in each transistor area Source region and the depth in drain region are deeper than the depth of the threshold voltage adjustment layer in the transistor area.

In other embodiments of the invention, N-type transistor can also be prepared using embedded source and drain technique respectively (NMOS) and the source region of P-type transistor (PMOS) and drain region, for example, first passing through one of lithography and etching technique etches each N-type The active area of gate stack structure two sides in transistor area forms corresponding source and drain groove (shape is, for example, U-shaped), then exists The corresponding source and drain semiconductor material of extension in the source and drain groove, to form source region and the drain region of each N-type transistor；Passing through Another road lithography and etching technique etches the active area of the gate stack structure two sides in each P-type crystal area under control, is formed corresponding Source and drain groove (shape is, for example, Σ shape), the then corresponding source and drain semiconductor material of extension in the source and drain groove, with shape Source region and drain region at each P-type transistor.

In addition, in other embodiments of the invention, rear grid technique can also be used, polysilicon gate stacked structure is replaced On behalf of high-K metal gate stacked structure (high-K gate dielectric layer and metal gate electrode layer that are greater than 4 including dielectric constant).

Later, corresponding metal silicide can be first made in gate stack structure, source region and the top in drain region, to reduce Contact resistance then interlayer dielectric layer and makes contact hole (CT) and metal interconnection structure (TM), will be formed each A transistor is electrically connected accordingly, to complete the manufacture of semiconductor devices.

After tested, one kind made from the manufacturing method using semiconductor devices of the invention is provided simultaneously with LVPMOS crystal Pipe, LVNMOS transistor, MVN-LDMOS transistor, MVP-LDMOS transistor and MVN ISO-LDMOS transistor are these five types of In the semiconductor devices of transistor, the breakdown voltage of each transistor is enhanced, and leakage current is lowered.It can be seen that this The manufacturing method of the semiconductor devices of invention carries out threshold voltage to each transistor area using comprehensive ion implantation technology Ion implanting is adjusted, to form threshold voltage adjustment layer, adjusts the threshold voltage and leakage current of the transistor of formation, while can be with That omits grid polycrystalline silicon once needs the ion implanting step of mask plate exposure mask, and can be used with the first conduction type The common trap of the first conduction type in the transistor areas such as the low voltage PMOS transistor area of the first well structure alternative semiconductors substrate Structure is saved and needs mask plate exposure mask come the work of the common well structure of the first conduction type formed in low voltage PMOS transistor Skill improves the wasting of resources it is possible thereby to save two lithography mask versions, simplifies technique.The manufacture of semiconductor devices of the invention Method is suitable for the manufacture of power circuit (including mobile power source, electric power management circuit, power supply circuit etc.).

Fig. 3 A to Fig. 3 E is please referred to, the present invention also provides made from a kind of manufacturing method using above-mentioned semiconductor devices Semiconductor devices, comprising: the semiconductor substrate (P-SUB in such as Fig. 3 A to Fig. 3 E) with multiple transistor areas；With first The first well structure (DNW) of conduction type is formed at least in a transistor area；The second trap with the second conduction type Structure (PW) is formed at least in a transistor area；Threshold voltage adjustment layer (VTP) is formed in each transistor First well structure (DNW) in area and/or the surface layer of the second well structure (PW)；Gate stack structure is formed in each crystal On the surface of the threshold voltage adjustment layer (VTP) in area under control；Source region and drain region are formed in the gate stack of each transistor area In the semiconductor substrate of structure two sides.

In the present embodiment, the multiple transistor area includes at least two in following transistor area: being used to form low pressure The transistor area 300a of PMOS transistor, the transistor area 300b for being used to form low voltage nmos transistor, it is used to form middle pressure N-type The transistor area 300c of lateral direction bilateral diffusion MOS transistor, the transistor for being used to form middle pressure p-type lateral direction bilateral diffusion MOS transistor Area 300d and be used to form isolation middle pressure N-type ldmos transistor transistor area 300e, lead between adjacent transistor area Interlude oxygen isolation structure (such as fleet plough groove isolation structure STI) is kept apart.

The semiconductor devices includes the laterally double expansions of low voltage PMOS transistor, low voltage nmos transistor, middle pressure N-type as a result, Dissipate at least two in the middle pressure N-type ldmos transistor of MOS transistor, middle pressure p-type lateral direction bilateral diffusion MOS transistor and isolation Kind transistor, the specific structure of various transistors are as follows:

The low voltage PMOS transistor includes: the with the first conduction type being formed in the transistor area 300a One well structure (DNW) 301a；It is formed in the threshold value with the first conduction type on the surface layer the first well structure (DNW) 301a Voltage adjustment layer (VTP) 306a；The gate stack structure being formed on the surface the threshold voltage adjustment layer 306a (such as wraps Include polysilicon gate 302a and gate dielectric layer below)；And it is formed in described the first of the gate stack structure two sides Source region 303a and drain region 304a in well structure (DNW) 301a, wherein gate stack structure can be including polysilicon gate The polysilicon gate stacked structure of 302a and gate dielectric layer below are also possible to include metal gate electrode layer and below The high-K metal gate stacked structure of high-K gate dielectric layer.

The low voltage nmos transistor includes: that one be formed in the transistor area 300b has the second conduction type Second well structure (PW) 301b；It is formed in the threshold value with the first conduction type on the surface layer the second well structure (PW) 301b Voltage adjustment layer (VTP) 306b；The gate stack structure being formed on the surface the threshold voltage adjustment layer (VTP) 306b； And it is formed in source region 303b and drain region 304b in second well structure of the gate stack structure two sides, wherein grid Pole stacked structure can be the polysilicon gate stacked structure of gate dielectric layer including polysilicon gate 302b and below, can also To be the high-K metal gate stacked structure for including metal gate electrode layer and high-K gate dielectric layer below.

Medium pressure N-type lateral direction bilateral diffusion MOS transistor includes: the tool being laterally distributed in the transistor area 300c There is the first well structure (DNW) 301c and one of the first conduction type that there is the second well structure (PW) 305c of the second conduction type, There is certain intervals, the first trap knot between first well structure (DNW) 301c and second well structure (PW) 305c Structure (DNW) 301c is equipped with an oxygen isolation structure 307c close to the side of the second well structure (PW) 305c；One is located at crystal Threshold voltage adjustment layer (VTP) 306c with the first conduction type on the active area surface layer of area under control 300c, threshold voltage adjustment Layer (VTP) 306c extends to the surface layer the second well structure (PW) 305c from the surface layer the first well structure (DNW) 301c； The gate stack structure being formed on the surface the threshold voltage adjustment layer (VTP) 306c, described gate stack structure one end Positioned at the top of the second well structure (PW) 305c, the other end is located at the top of the field oxygen isolation structure 307c；And shape At in the second well structure (PW) 305c source region 303c and be formed in drain region in the first well structure (DNW) 301c 304c, the source region 303c and drain region 304c live apart the two sides of the gate stack structure, wherein gate stack structure can be The polysilicon gate stacked structure of gate dielectric layer including polysilicon gate 302c and below is also possible to include metal gate electricity The high-K metal gate stacked structure of pole layer and high-K gate dielectric layer below.

Medium pressure p-type lateral direction bilateral diffusion MOS transistor includes: that one be formed in the transistor area 300d has the The first well structure (DNW) 301d of one conduction type；One be formed in the first well structure (DNW) 301d has second to lead The second well structure (PW) 305d of electric type；An oxygen isolation structure being formed in the second well structure (PW) 305d 307d；One is located at the threshold voltage adjustment layer (VTP) with the first conduction type on the active area surface layer of transistor area 300d 306d, threshold voltage adjustment layer (VTP) 306d are from (the area not occupied by PW 305d the first well structure (DNW) 301d Domain) surface layer extend to the surface layer the second well structure (PW) 305d, and the region oxygen isolation structure 307d on the scene is truncated, or It says, threshold voltage adjustment layer (VTP) 306d forms the surface layer the first well structure (DNW) 301d on the left of oxygen isolation structure 307d on the scene And the surface layer the second well structure (PW) 305d on the right side of the oxygen isolation structure 307d of field；It is formed in the threshold voltage adjustment layer (VTP) gate stack structure on the surface 306d, described gate stack structure one end are located at second well structure (PW) The top of the first well structure (DNW) 301d (region not occupied by PW 305d partially) on the outside of 305d, other end position In the top of the field oxygen isolation structure 307d；And it is formed in the first trap knot on the outside of the second well structure (PW) 305d Source region 303d in structure (DNW) 301d (i.e. not by region that PW 305d is occupied) and it is formed in second well structure (PW) Drain region 304d in 305d, the source region 303d and drain region 304d live apart the two sides of the gate stack structure, wherein grid pile Stack structure can be the polysilicon gate stacked structure of gate dielectric layer including polysilicon gate 302c and below, be also possible to The high-K metal gate stacked structure of high-K gate dielectric layer including metal gate electrode layer and below.

The middle pressure N-type ldmos transistor of the isolation includes: to be formed in the transistor area 300e to have first to lead The first well structure (DNW) 301e of electric type；One be formed in the first well structure (DNW) 301e has the second conductive-type The second well structure (PW) 305e of type；The first well structure (DNW) 301e being formed on the outside of the second well structure (PW) 305e An oxygen isolation structure 307e in (region not occupied by PW 305e)；One is located at the active area table of transistor area 300e Threshold voltage adjustment layer (VTP) 306e with the first conduction type of layer, threshold voltage adjustment layer (VTP) 306e are from described the The surface layer of one well structure (DNW) 301e (i.e. not by region that PW 305e is occupied) extends to the second well structure (PW) 305e Surface layer, and the region oxygen isolation structure 307e on the scene is truncated, in other words, threshold voltage adjustment layer (VTP) 306e forms oxygen on the scene The first well structure on the right side of the second well structure surface layer (PW) 305e and field oxygen isolation structure 307d on the left of isolation structure 307d (DNW) 301e (region not occupied by PW 305e) surface layer；It is formed in the surface the threshold voltage adjustment layer (VTP) 306e On a gate stack structure, described gate stack structure one end is located at the top of the second well structure (PW) 305e, another End is located at the top of the field oxygen isolation structure 307e；And it is formed in the source region in the second well structure (PW) 305e 303e and the first well structure (DNW) 301e being formed on the outside of the second well structure (PW) 305e (are not occupied by PW 305e Region) in drain region 304e, the source region 303e and drain region 304e live apart the two sides of the gate stack structure, wherein grid Pole stacked structure can be the polysilicon gate stacked structure of gate dielectric layer including polysilicon gate 302c and below, can also To be the high-K metal gate stacked structure for including metal gate electrode layer and high-K gate dielectric layer below.

In addition, semiconductor devices of the invention further includes being formed simultaneously with the polysilicon gate in the gate stack structure Polysilicon resistance.

Semiconductor devices of the invention, including the laterally double expansions of low voltage PMOS transistor, low voltage nmos transistor, middle pressure N-type Dissipate at least two in the middle pressure N-type ldmos transistor of MOS transistor, middle pressure p-type lateral direction bilateral diffusion MOS transistor and isolation Kind transistor, the breakdown voltage of each transistor is relatively high, and leakage current is relatively low, the overall performance of semiconductor devices Improved.Semiconductor devices of the invention can be power supply management device or power supply unit (such as mobile power source), either Attachment in power supply management device or power supply unit.

Obviously, those skilled in the art can carry out various modification and variations without departing from spirit of the invention to invention And range.If in this way, these modifications and changes of the present invention belong to the claims in the present invention and its equivalent technologies range it Interior, then the present invention is also intended to include these modifications and variations.

Claims

1. a kind of manufacturing method of semiconductor devices, which comprises the following steps:

The semiconductor substrate for having multiple transistor areas is provided, semiconductor substrate described in the ion pair using the first conduction type into Row the first trap ion implanting, to form first well structure with the first conduction type at least in a transistor area；

Semiconductor substrate described in ion pair using the second conduction type carries out the second trap ion implanting, at least in a crystal Second well structure with the second conduction type is formed in area under control, and second well structure is shallower than first well structure；

Threshold voltage is carried out to each transistor area using comprehensive ion implantation technology and adjusts ion implanting, to form threshold value Voltage adjustment layer；

Source region and drain region are formed in the semiconductor substrate of each gate stack structure two sides, in each transistor Area forms corresponding transistor.

2. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that using second conduction type from Before or after son carries out the second trap ion implanting to the semiconductor substrate, corresponding field oxygen is formed using field oxygen isolation technology Isolation structure, to define the active area of each transistor area.

3. the manufacturing method of semiconductor devices as claimed in claim 2, which is characterized in that using first conduction type The each transistor area of ion pair carries out threshold voltage and adjusts ion implanting, in the active area table of each transistor area Layer forms the threshold voltage adjustment layer.

4. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the threshold voltage adjustment ion note The Implantation Energy entered is 50KeV~200KeV, implantation dosage 1.0E10/cm²~1.0E12/cm²。

5. the manufacturing method of semiconductor devices as described in claim 1, which is characterized in that the table in each transistor area The step of corresponding gate stack structure is formed on face include:

First time ion implanting is carried out to the polysilicon layer using comprehensive ion implantation technology, to adjust the polysilicon layer Resistance, the resistance value for the polysilicon resistance for being subsequently formed the resistance value of the polysilicon layer；

The polysilicon layer and the gate dielectric layer are performed etching, to be formed simultaneously the gate stack structure and polysilicon Resistance.

6. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that formed the source region and drain region it Afterwards, the gate stack structure at least one transistor area surface is replaced with into metal gate stack structures, the metal gates heap Stack structure includes the high-K gate dielectric layer and metal gate electrode layer stacked gradually on the surface of transistor area.

7. the manufacturing method of semiconductor devices as claimed in claim 5, which is characterized in that formed the source region and drain region it Afterwards, on the surface of the source region, drain region, gate stack structure and polysilicon resistance formed metal silicide and with the gold Belong to the metal contact hole of silicide electrical contact.

8. the manufacturing method of the semiconductor devices as described in any one of claims 1 to 7, which is characterized in that the semiconductor The transistor formed on substrate includes low voltage PMOS transistor, low voltage nmos transistor, middle pressure N-type lateral direction bilateral diffusion MOS crystal At least two in the middle pressure N-type ldmos transistor of pipe, middle pressure p-type lateral direction bilateral diffusion MOS transistor and isolation.

9. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that include in the multiple transistor area Be used to form the transistor area of the low voltage PMOS transistor, the low voltage PMOS transistor of formation include: be formed in it is described First well structure in transistor area；It is formed in the threshold voltage adjustment layer on first well structure surface layer； The gate stack structure being formed on the threshold voltage adjustment layer surface；And it is formed in the gate stack knot Source region and drain region in first well structure of structure two sides.

10. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the multiple transistor area Zhong Bao The transistor area for being used to form the low voltage nmos transistor is included, the low voltage nmos transistor of formation includes: to be formed in institute State second well structure in transistor area；It is formed in the threshold voltage adjustment on second well structure surface layer Layer；The gate stack structure being formed on the threshold voltage adjustment layer surface；And it is formed in the gate stack Source region and drain region in second well structure of structure two sides.

11. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the multiple transistor area Zhong Bao The transistor area for being used to form medium pressure N-type lateral direction bilateral diffusion MOS transistor is included, the medium pressure N-type of formation is laterally double to expand Scattered MOS transistor includes: first well structure and second well structure being laterally distributed in the transistor area, There are certain intervals, first well structure is close to the second trap knot between first well structure and second well structure The side of structure is equipped with an oxygen isolation structure；An institute on second well structure surface layer is extended to from first well structure surface layer State threshold voltage adjustment layer；The gate stack structure being formed on the threshold voltage adjustment layer surface, the grid Stacked structure one end is located at the top of second well structure, and the other end is located at the top of the field oxygen isolation structure；And point It is not formed in second well structure and source region and drain region in first well structure, the source region and the drain region separation grid The two sides of pole stacked structure.

12. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the multiple transistor area Zhong Bao The transistor area for being used to form medium pressure p-type lateral direction bilateral diffusion MOS transistor is included, the medium pressure p-type of formation is laterally double to expand Scattered MOS transistor includes: first well structure being formed in the transistor area；It is formed in first well structure Second well structure；An oxygen isolation structure being formed in second well structure；From first well structure Surface layer extends to the threshold voltage adjustment layer on second well structure surface layer；It is formed in the threshold voltage adjustment layer table A gate stack structure on face, described gate stack structure one end are located at described first on the outside of second well structure The top of well structure, the other end are located at the top of the field oxygen isolation structure；And be respectively formed at second well structure and Drain region in the first well structure and source region on the outside of second well structure, the source region and drain region are lived apart the gate stack knot The two sides of structure.

13. the manufacturing method of semiconductor devices as claimed in claim 8, which is characterized in that the multiple transistor area Zhong Bao Include the transistor area for being used to form the middle pressure N-type ldmos transistor of the isolation, the middle pressure N-type LDMOS of the isolation of formation Transistor includes: first well structure being formed in the transistor area；One be formed in first well structure Second well structure；An oxygen isolation structure being formed in the first well structure on the outside of second well structure；From described First well structure surface layer extends to the threshold voltage adjustment layer on second well structure surface layer；It is formed in the threshold value electricity A gate stack structure in pressure adjustment layer surface, described gate stack structure one end is located at the upper of second well structure Side, the other end are located at the top of the field oxygen isolation structure；And it is respectively formed at second well structure and second trap Source region in the first well structure and drain region on the outside of structure, the source region and drain region are lived apart the two sides of the gate stack structure.

14. a kind of semiconductor devices characterized by comprising

Semiconductor substrate with multiple transistor areas；

The second well structure with the second conduction type is formed at least in a transistor area, and second well structure It is shallower than first well structure；

Threshold voltage adjustment layer is formed in the first well structure of each transistor area and/or the surface layer of the second well structure；

15. semiconductor devices as claimed in claim 14, which is characterized in that the multiple transistor area is used to form low pressure PMOS transistor, low voltage nmos transistor, middle pressure N-type lateral direction bilateral diffusion MOS transistor, middle pressure p-type lateral direction bilateral diffusion MOS crystal At least two transistors in pipe and the middle pressure N-type ldmos transistor of isolation.

16. semiconductor devices as claimed in claim 15, which is characterized in that include being used to form in the multiple transistor area The transistor area of the low voltage PMOS transistor, the low voltage PMOS transistor of formation include: to be formed in the transistor area In first well structure；It is formed in the threshold voltage adjustment layer on first well structure surface layer；It is formed in institute State the gate stack structure on threshold voltage adjustment layer surface；And it is formed in the gate stack structure two sides Source region and drain region in first well structure.

17. semiconductor devices as claimed in claim 15, which is characterized in that include being used to form in the multiple transistor area The transistor area of the low voltage nmos transistor, the low voltage nmos transistor of formation include: to be formed in the transistor area In second well structure；It is formed in the threshold voltage adjustment layer on second well structure surface layer；It is formed in institute State the gate stack structure on threshold voltage adjustment layer surface；And it is formed in the gate stack structure two sides Source region and drain region in second well structure.

18. semiconductor devices as claimed in claim 15, which is characterized in that include being used to form in the multiple transistor area The transistor area of medium pressure N-type lateral direction bilateral diffusion MOS transistor, the medium pressure N-type lateral direction bilateral diffusion MOS transistor of formation It include: first well structure and second well structure being laterally distributed in the transistor area, first trap There are certain intervals, first well structure is set close to the side of second well structure between structure and second well structure There is an oxygen isolation structure；The threshold voltage on second well structure surface layer is extended to from first well structure surface layer Adjustment layer；The gate stack structure being formed on the threshold voltage adjustment layer surface, the gate stack structure one End is located at the top of second well structure, and the other end is located at the top of the field oxygen isolation structure；And it is respectively formed at institute State the second well structure and source region and drain region in first well structure, the source region and the drain region separation gate stack structure Two sides.

19. semiconductor devices as claimed in claim 15, which is characterized in that include being used to form in the multiple transistor area The transistor area of medium pressure p-type lateral direction bilateral diffusion MOS transistor, the medium pressure p-type lateral direction bilateral diffusion MOS transistor of formation It include: first well structure being formed in the transistor area；One be formed in first well structure described Two well structures；An oxygen isolation structure being formed in second well structure；It is extended to from the surface layer of first well structure One threshold voltage adjustment layer on second well structure surface layer；The institute being formed on the threshold voltage adjustment layer surface Gate stack structure is stated, described gate stack structure one end is located at the upper of first well structure on the outside of second well structure Side, the other end are located at the top of the field oxygen isolation structure；And it is respectively formed at second well structure and second trap Drain region in the first well structure and source region on the outside of structure, the source region and drain region are lived apart the two sides of the gate stack structure.

20. semiconductor devices as claimed in claim 15, which is characterized in that include being used to form in the multiple transistor area The transistor area of the middle pressure N-type ldmos transistor of the isolation, the middle pressure N-type ldmos transistor packet of the isolation of formation It includes: 1 be formed in the transistor area, first well structure；One described second be formed in first well structure Well structure；An oxygen isolation structure being formed in the first well structure on the outside of second well structure；From the first trap knot Structure surface layer extends to a threshold voltage adjustment layer on second well structure surface layer；It is formed in the threshold voltage adjustment layer surface On a gate stack structure, described gate stack structure one end is located at the top of second well structure, other end position In the top of the field oxygen isolation structure；And it is respectively formed on the outside of second well structure and second well structure Source region and drain region in first well structure, the source region and drain region are lived apart the two sides of the gate stack structure.