CN106653836A - Insulated gate bipolar transistor device with low conduction voltage drop, and manufacturing method for insulated gate bipolar transistor device - Google Patents
Insulated gate bipolar transistor device with low conduction voltage drop, and manufacturing method for insulated gate bipolar transistor device Download PDFInfo
- Publication number
- CN106653836A CN106653836A CN201611089631.0A CN201611089631A CN106653836A CN 106653836 A CN106653836 A CN 106653836A CN 201611089631 A CN201611089631 A CN 201611089631A CN 106653836 A CN106653836 A CN 106653836A
- Authority
- CN
- China
- Prior art keywords
- interarea
- type
- conduction type
- region
- conduction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 88
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000007667 floating Methods 0.000 claims abstract description 29
- 230000004224 protection Effects 0.000 claims abstract description 27
- 230000001413 cellular effect Effects 0.000 claims description 122
- 239000002184 metal Substances 0.000 claims description 117
- 229910052751 metal Inorganic materials 0.000 claims description 117
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 52
- 238000009825 accumulation Methods 0.000 claims description 34
- 230000000694 effects Effects 0.000 claims description 32
- 238000005530 etching Methods 0.000 claims description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims description 32
- 239000012535 impurity Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 26
- 238000009413 insulation Methods 0.000 claims description 25
- 230000007704 transition Effects 0.000 claims description 23
- 230000005684 electric field Effects 0.000 claims description 16
- 210000000746 body region Anatomy 0.000 claims description 15
- 238000002347 injection Methods 0.000 claims description 12
- 239000007924 injection Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 150000002739 metals Chemical class 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 239000010931 gold Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005253 cladding Methods 0.000 claims description 2
- 230000010355 oscillation Effects 0.000 abstract description 5
- 230000008569 process Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000002955 isolation Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 certainly Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
Abstract
The invention relates to an insulated gate bipolar transistor device with low conduction voltage drop, and a manufacturing method for the insulated gate bipolar transistor device. The device comprises an active region located on a semiconductor substrate, and a terminal protection region. Active cells of the active region on the section of the device employ a trench structure, and comprise active cells and non-active cells. The bottom of an active cell trench and the bottom of a non-active cell trench are respectively provided with a floating region of a second conductive type, wherein the floating region of the second conductive type below the active cell trench wraps the bottom of the active cell trench, and the floating region of the second conductive type below the non-active cell trench wraps the bottom of the non-active cell trench. The device has extremely low conduction voltage drop and extremely quick cut-off speed under the condition that the withstand voltage is guaranteed, is lower in current and voltage oscillation, and greatly improves the work reliability.
Description
Technical field
The present invention relates to a kind of insulated-gate bipolar transistor device and its manufacture method, especially a kind of to have low conducting
The insulated-gate bipolar transistor device and its manufacture method of pressure drop, belongs to the technical field of semiconductor devices.
Background technology
The full name of IGBT is Insulate Gate Bipolar Transistor, i.e. igbt.It is simultaneous
The multiple advantages of tool MOSFET and GTR, greatly extend the application of power semiconductor.Partly lead as novel electric power
The main representative of body device, IGBT is widely used in industry, information, new forms of energy, medical science, traffic, military affairs and aviation field.IGBT
It is one of currently the most important ones power device, IGBT is because with input impedance height, on-state voltage drop is low, and drive circuit is simple, peace
Full workspace width, the advantages of current handling capability is strong, increasingly causes the attention of people in various power switch applications.It
Motor control, IF switch power supply and inverter, robot, air-conditioning and the quick low-loss many fields of requirement have extensively
Application.
Since IGBT inventions, people are devoted to improving the performance of IGBT always.Through the development of twenties years, carry in succession
Various IGBT device structures are gone out, have made device performance obtain steady lifting.By using dummy trench gate electrodes, industry
Propose IEGT device architectures.IEGT device dummy trench gate electrodes cause the spacing between trench gate to increase, and reduce transmitting
The extracting channel of extreme minority carrier, introduces the carrier enhancement effect of device emitter terminal, enhances the load of drift region
Stream injection, this improves the conductance modulation of N-type drift region, improve the carrier concentration profile of whole N-type drift region,
IGBT is set to obtain forward conduction voltage drop and the compromise of turn-off power loss of low forward conduction voltage drop and improvement.
1), due to the employing of dummy trench gate electrodes however, for IEGT device architectures, cause：Device grids electric capacity
(particularly grid-collector capacitance) is big, but the switching process of IGBT device is exactly the mistake rushed to grid capacitance, discharged
Journey, grid capacitance more favourable opposition, discharge time is longer, and big grid capacitance (particularly grid-collector capacitance) reduces device
Switching speed, increase the switching loss of device, have impact on the forward conduction voltage drop of device and the compromise characteristic of switching loss；
2), due to the presence in floating body area, cause：Internal current potential is inconsistent in break-over of device turn off process, shows larger electricity
Pressure, current oscillation, bring serious EMI problems, have a strong impact on system reliability.
In view of above defect of the prior art, a kind of new construction of effective raising IGBT performances and its manufacture method
Proposition is extremely necessary.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided a kind of insulated gate with low conduction voltage drop
Bipolar transistor device and its manufacture method, its compact conformation can be in the case where guarantee be pressure, with extremely low conducting
Pressure drop and the turn-off speed being exceedingly fast, and vibrate with relatively low Current Voltage, greatly improve the reliability of work.
According to the technical scheme that the present invention is provided, the insulated gate bipolar transistor device with low conduction voltage drop
Part, in the top plan view of the insulated-gate bipolar transistor device, including the active area on the semiconductor substrate and
Terminal protection area, the active area is located at the center of semiconductor substrate, and terminal protection area is located at the outer ring of active area, and surround
Surround the active area；On the section of the insulated-gate bipolar transistor device, semiconductor substrate have the first interarea with
And the second interarea corresponding with the first interarea, the first conduction type drift region is included between first interarea and the second interarea；
On the section of the insulated-gate bipolar transistor device, the active area cellular adopts groove structure, described
Active area cellular includes active cellular and nonactive cellular；The trench wall of active cellular and diapire growth have insulation grid oxygen
Change layer, have in the active cellular groove of insulation gate oxide in the growth and fill active cellular conductive polycrystalline silicon, activity unit
The notch of born of the same parents' groove is covered by the first insulating medium layer；It is provided with the second conductivity type body region between adjacent active cellular groove, and
The bottom of second conductivity type body region is provided with the first conduction type carrier accumulation layer；Set in the second conductivity type body region
There are the first conduction type launch site and the second conduction type activity ohmic contact regions, the first conduction type launch site and activity unit
The lateral wall contact of born of the same parents' groove, it is interval that the second conduction type activity ohmic contact regions are located at the transmitting of the first conduction type, and with two
The first conduction type launch site contact of side；First conduction type launch site, the second conduction type activity ohmic contact regions and the
The first emitter metal Ohmic contact above one interarea；Gate electrode gold above active cellular conductive polycrystalline silicon and the first interarea
Category Ohmic contact；
The trench wall of nonactive cellular and diapire growth have insulation gate oxide, have insulation gate oxidation in the growth
Nonactive cellular conductive polycrystalline silicon is filled with the nonactive cellular groove of layer, is all provided with the both sides of the nonactive cellular groove
There are the second conduction type Wei Ti areas, in the second conduction type Wei Ti areas the nonactive Ohmic contact of the second conduction type is provided with
Area, the nonactive ohmic contact regions of second conduction type contact with the lateral wall of nonactive cellular groove, the second conduction type
Nonactive ohmic contact regions and nonactive cellular conductive polycrystalline silicon connect with second emitter metal ohm on the first interarea
Touch；Second emitter metal is dielectrically separated from the first emitter metal；
The second conduction type floating region is equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove,
The bottom land of the active cellular groove of the second conduction type floating region cladding of active cellular beneath trenches, nonactive cellular beneath trenches
The second conduction type floating region coat the bottom land of nonactive cellular groove.
First emitter metal is connected with the second emitter metal by diode, the first emitter metal and two poles
The anode tap connection of pipe, the second emitter metal is connected with the cathode terminal of diode.
First emitter metal is connected by external diode with the second emitter metal, or by being arranged at
Integrated diode on one interarea is connected with the second emitter metal；Integrated diode is located at first master in terminal protection area
On face, integrated diode includes diode P-type conduction region and the diode with the diode P-type conduction area adjacency
N-type conductive region.
The terminal protection area includes transition region, field limiting ring structure and cut-off ring structure, and the transition region adjoins active
Area, ends the outer ring that ring structure is located at terminal protection area, and field limiting ring structure is located between transition region and cut-off ring structure.
The second conduction type collecting zone, the second conduction type collection are provided with the second interarea of the semiconductor substrate
Electric area is provided with the first conduction type electric field cut-off region, the second conduction type collecting zone and current collection with the first conduction type drift interval
Pole metal ohmic contact.
A kind of manufacture method of the insulated-gate bipolar transistor device with low conduction voltage drop, the insulated gate bipolar
The manufacture method of transistor device comprises the steps：
A, the semiconductor substrate with two opposing main faces is provided, two opposing main faces include the first interarea and with first
The second corresponding interarea of interarea, includes the first conduction type drift region between the first interarea and the second interarea；
B, field oxide is deposited on the first interarea of above-mentioned semiconductor substrate, the field oxide covers semiconductor substrate
The first interarea；
C, above-mentioned field oxide is optionally sheltered and etched, to form ion implanting window, and noted using the ion
Entering window carries out the injection of the second conductive type impurity, pushes away main knot, field limiting ring needed for being formed in semiconductor substrate after trap
Structure and the second conduction type Wei Ti areas；
After d, the field oxide removed on above-mentioned semiconductor substrate active area, and the field oxide needed for removing, the
Hard mask layer is deposited on one interarea, the hard mask layer is covered on the first interarea of active area, and be covered in terminal protection area
The first interarea and field oxide on；
E, above-mentioned hard mask layer is optionally sheltered and etched, to obtain required hard mask window, covered firmly using described
Film window is performed etching to semiconductor substrate, to form multiple grooves in the first conduction type drift region of semiconductor substrate；
The second conductive type impurity is injected above the first interarea of semiconductor substrate for forming groove, after pushing away trap, the needed for being formed
Two conduction type floating regions, the second conduction type floating region coats the bottom land of groove；
F, the hard mask layer removed on the above-mentioned interarea of semiconductor substrate first, and after hard mask layer is removed, in above-mentioned ditch
The inwall of groove and diapire growth insulation gate oxide, and fill conductive polycrystalline silicon growing to have in the groove of insulation gate oxide；
G, on the first interarea of above-mentioned semiconductor substrate the first photoresist layer is coated, institute is being carried out to the first photoresist layer
After the etching for needing, the first conductive type impurity is injected above the first interarea, with the drift of the first conduction type of semiconductor substrate
The the first conduction type carrier accumulation layer moved needed for being formed in area；
H, above-mentioned first photoresist layer of removal, and the second photoresist layer is coated on the first interarea of semiconductor substrate,
After etching needed for carrying out to the second photoresist layer, the second conductive type impurity is injected above the first interarea, with semiconductor-based
The second conductivity type body region is formed in first conduction type drift region of plate, it is conductive that second conductivity type body region is located at first
Directly over type of carrier accumulation layer, the second conductivity type body region contacts with the first conduction type carrier accumulation layer；
I, above-mentioned second photoresist layer of removal, and the 3rd photoresist layer is coated on the first interarea of semiconductor substrate,
After etching needed for carrying out to the 3rd photoresist layer, the first conductive type impurity is injected above the first interarea, with semiconductor
The first conduction type launch site and the first conduction type cut-off region are formed in substrate；
K, the first insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, and to first dielectric
Layer is performed etching, and the first insulating medium layer top after etching carries out the second conductive type impurity injection, with semiconductor
The second conduction type ohmic contact regions needed for being formed in the active area of substrate；
L, the second emitter metal is set on the first interarea of above-mentioned semiconductor substrate, the second emitter metal with it is corresponding
The second conduction type ohmic contact regions and respective groove in conductive polycrystalline silicon Ohmic contact, with nonactive needed for being formed
Cellular；
N, the second insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, and to second dielectric
The second required insulating medium layer contact hole is formed after layer etching；
O, on the first interarea of above-mentioned semiconductor substrate, deposited metal, to the metal level for obtaining etching after, formed
Required the first emitter metal, gate electrode metal and cut-off ring metal, the first emitter metal is sent out with the first conduction type
Area and corresponding second conduction type ohmic contact regions Ohmic contact are penetrated, to form required active cellular, the first conductive-type
In type drift region except with the conductive polycrystalline silicon of the second emitter metal Ohmic contact with gate electrode metal Ohmic contact, end ring
Metal and the first conduction type cut-off region Ohmic contact；
P, the first conduction type electric field cut-off region and second needed for the second interarea of above-mentioned semiconductor substrate is formed
Conduction type collecting zone, the first conduction type electric field cut-off region is located at the first conduction type drift region and the second conduction type collection
It is electric interval, and the second conduction type collecting zone is adjacent with the first conduction type electric field cut-off region；
Q, deposit on above-mentioned second conduction type collecting zone required collector electrode metal, the collector electrode metal and second
Conduction type collecting zone Ohmic contact.
The material of the semiconductor substrate includes silicon.
In step g, when the first conduction type carrier accumulation layer is formed, shape is gone back on the first interarea of semiconductor substrate
Into diode N-type conductive region；In step h, when the second conductivity type body region is formed, in the first interarea of semiconductor substrate
On also form diode P-type conduction region, the diode P-type conduction region adjoins with diode N-type conductive region, to be formed
Integrated diode；Second emitter metal and diode N-type conductive region Ohmic contact, the first emitter metal and diode
P-type conduction region Ohmic contact.
In both " first conduction type " and " the second conduction type ", for N-type insulated gate bipolar transistor device
Part, the first conduction type refers to N-type, and the second conduction type is p-type；For p-type insulated-gate bipolar transistor device, first is conductive
Type is contrary with N-type semiconductor device with the type of the second conduction type indication.
Advantages of the present invention：
1st, during break-over of device, positioned at the first conduction type carrier accumulation layer of the second conductivity type body region bottom, due to
The presence of Built-in potential can hinder circulation of the minority carrier to emitter stage, can form the accumulation of minority carrier, and conductance is adjusted
Effect processed strengthens；Meanwhile, the accumulation of nonactive cellular B areas minority carrier further enhances the conductivity modulation effect of device,
Therefore, it can significantly reduce IGBT device saturation voltage drop, reduce conduction loss.
2nd, when device is blocked, positioned at the presence of the second conduction type floating region, active cellular region A bodies area is shielded,
Therefore, it is possible to when the first conduction type carrier accumulation layer concentration is adjusted, it is ensured that it is unaffected that device is pressure.
3rd, the presence in nonactive cellular B areas causes effective gate electrode area to reduce so that gate electrode and the electricity for launching interpolar
Hold and gate electrode is substantially reduced with the electric capacity of inter-collector, reduce switching loss, improve the switching speed of device.
4th, nonactive cellular B areas, the second emitter metal and nonactive cellular conductive polycrystalline silicon Ohmic contact, and with two poles
The cathode terminal connection of pipe, reduces the Voltage unbalance inside IGBT structure, it is thereby possible to reduce the electricity during devices switch
Stream, oscillation.
Description of the drawings
Fig. 1 is the sectional view of active area of the present invention.
Fig. 2 is the top view of the present invention.
Fig. 3 is the sectional view of A1-A1 ' in Fig. 2 of the present invention.
Fig. 4 is the sectional view of B1-B1 ' in Fig. 2 of the present invention.
Fig. 5 is the sectional view of B2-B2 ' in Fig. 2 of the present invention.
Fig. 6 is the sectional view of C1-C1 ' in Fig. 2 of the present invention.
Fig. 7～Figure 19 is embodied as processing step sectional view for the present invention, wherein
Fig. 7 is the sectional view of semiconductor substrate of the present invention.
Fig. 8 is that the present invention obtains the sectional view after field oxide.
Fig. 9 is that the present invention obtains the sectional view behind PXing Weiti areas.
Figure 10 is that the present invention obtains the sectional view after hard mask layer.
Figure 11 is the sectional view that the present invention obtains p-type floating region.
Figure 12 is the sectional view after present invention filling conductive polycrystalline silicon.
Figure 13 is that the present invention obtains the sectional view after N-type carrier accumulation layer.
Figure 14 is that the present invention obtains the sectional view behind p-type ohmic contact regions.
Figure 15 is that the present invention obtains the sectional view after the second emitter metal.
Figure 16 is that the present invention obtains the sectional view after the second insulating medium layer.
Figure 17 is that the present invention obtains the sectional view after the first emitter metal.
Figure 18 is that the present invention obtains the sectional view after p-type collecting zone.
Figure 19 is that the present invention obtains the sectional view after collector electrode metal.
Description of reference numerals：1-N types drift region, 2-P Xing Weiti areas, 3-P type floating regions, 4-N type carrier accumulation layers, 5-
PXing Ti areas, 6- insulation gate oxides, 7- activity cellular conductive polycrystalline silicons, 7-1- diode N-type conductive regions, 7-2- diode P
Type conductive region, 8-N+ launch sites, 9-P types activity ohmic contact regions, the insulating medium layers of 10- first, the emitter stages of 11- second gold
Category, the insulating medium layers of 12- second, the emitter metals of 13- first, 14- field oxides, 15-P type transition regions, 16- gate electrodes gold
Category, 17- cut-off ring metals, 18-N+ electric field cut-off regions, 19-P+ collecting zones, 20- collector electrode metals, 21-N+ cut-off regions, 22-P types
The nonactive cellular conductive polycrystalline silicon of field limiting ring, 23-, 24- dielectric isolation layers, 25- activity cellulars draw conductive polycrystalline silicon, 26-P types
Nonactive ohmic contact regions, 27- hard mask layers, 100- active areas and 200- terminal protections area.
Specific embodiment
With reference to concrete drawings and Examples, the invention will be further described.
As shown in Figure 1, Figure 2, shown in Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Figure 19：In order in the case where guarantee is pressure, with pole
Low conduction voltage drop and the turn-off speed being exceedingly fast, and vibrate with relatively low Current Voltage, the reliability of work is greatly improved, with
As a example by N-type insulated-gate bipolar transistor device, the present invention is specifically included：In bowing for the insulated-gate bipolar transistor device
On view plane, including the active area 100 on semiconductor substrate and terminal protection area 200, the active area 100 is located at half
The center of conductor substrate, terminal protection area 200 is located at the outer ring of active area 100, and around the encirclement active area 100；
On the section of the insulated-gate bipolar transistor device, semiconductor substrate has the first interarea and corresponding with the first interarea
Second interarea, includes N-type drift region 1 between first interarea and the second interarea；
On the section of the insulated-gate bipolar transistor device, the cellular of the active area 100 adopts groove structure, institute
Active area cellular is stated including activity cellular A and nonactive cellular B；The trench wall of active cellular A and diapire growth have absolutely
Edge gate oxide 6, has in the active cellular groove of insulation gate oxide 6 in the growth and fills active cellular conductive polycrystalline silicon
7, the notch of active cellular A grooves is covered by the first insulating medium layer 10；PXing Ti areas 5 are provided between adjacent active cellular groove, and
N-type carrier accumulation layer 4 is provided with the bottom in the PXing Ti areas 5；N+ launch sites 8 and p-type activity Europe are provided with P bodies area 5
Nurse contact zone 9, N+ launch sites 8 contact with the lateral wall of active cellular groove, and p-type activity ohmic contact regions 9 are located at N+ launch sites 8
Between, and contact with the N+ launch sites 8 of both sides；First above the interarea of N+ launch sites 8, p-type activity ohmic contact regions 9 and first
The Ohmic contact of emitter-base bandgap grading metal 13；The Ohmic contact of gate electrode metal 16 above the interarea of active cellular conductive polycrystalline silicon 7 and first；
The trench wall of nonactive cellular and diapire growth have insulation gate oxide 6, have insulation grid oxygen in the growth
Change and be filled with the nonactive cellular groove of layer 6 nonactive cellular conductive polycrystalline silicon 23, the two of the nonactive cellular groove
Side is equipped with PXing Weiti areas 2, and in the PXing Weiti areas 2 the nonactive ohmic contact regions 26 of p-type are provided with, and the p-type is nonactive
Ohmic contact regions 26 contact with the lateral wall of nonactive cellular groove, the nonactive ohmic contact regions 26 of p-type and nonactive cellular
Conductive polycrystalline silicon 23 with the first interarea on the Ohmic contact of the second emitter metal 11；Second emitter metal 11 and first
Emitter-base bandgap grading metal 13 is dielectrically separated from；
P-type floating region 3, active cellular are equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove
The p-type floating region 3 of beneath trenches coats the bottom land of active cellular groove, and the p-type floating region 3 of nonactive cellular beneath trenches is coated
The bottom land of nonactive cellular groove.
Specifically, semiconductor substrate can select silicon substrate, can have to active area 100 by terminal protection area 200
Effect protection, the concrete matching relationship between active area 100 and terminal protection area 200 is known to those skilled in the art, herein not
Repeat again.In the embodiment of the present invention, the groove of active cellular A is same technique manufactures layer with the groove of nonactive cellular B, that is, live
The groove of property cellular A is identical with the gash depth of nonactive cellular B, the insulation gate oxide 6 and non-live in active cellular A grooves
Property cellular B grooves in insulation gate oxide 6 be same process layer, the active cellular conductive polycrystalline silicon 7 in active cellular A grooves
It is same process layer with the nonactive cellular conductive polycrystalline silicon 23 in nonactive cellular B grooves.
In Fig. 3, A1-A1 ', along section view is carried out perpendicular to the direction of groove, is parallel to groove and first along activity in Fig. 4
The direction of born of the same parents' conductive polycrystalline silicon 7 carries out section view, is parallel to groove, and along the side of nonactive cellular conductive polycrystalline silicon 7 in Fig. 5
To carrying out section view.
The notch of active cellular A grooves is covered by the first insulating medium layer 10 so that the activity unit in active cellular A grooves
It is dielectrically separated between the emitter metal 13 of born of the same parents' conductive polycrystalline silicon 7 and first and the second emitter metal 12, the first emitter metal
13 are isolated by N+ launch sites 8 and p-type activity ohmic contact regions 9 with PXing Ti areas 5, N+ launch sites 8 and activity cellular A grooves
Lateral wall overlying contact, N-type carrier accumulation layer 4 is located at the lower section in PXing Ti areas 5, and usually, N-type carrier accumulation layer 4 is located at
The top of active cellular A groove bottom lands, N-type carrier accumulation layer 4 is not contacted with p-type floating region 3, and PXing Ti areas 5 are carried by N-type
Flow sub- accumulation layer 4 to isolate with N-type drift region 1.In break-over of device, hole accumulates in the bottom of N-type carrier accumulation layer 4, with N
Type carrier accumulation layer 4 forms Built-in potential；The accumulation in hole reduces the resistivity of N-type drift region 1, leads so as to effectively reduction
Logical pressure drop.
Nonactive cellular conductive polycrystalline silicon 23 is formed with the conductive polycrystalline silicon of the direct Ohmic contact of the second emitter metal 11,
PXing Weiti areas 2 are respectively formed in the both sides of nonactive cellular B grooves, PXing Weiti areas 2 contact with p-type floating region 3.P-type non-live
Property ohmic contact regions 26 and nonactive cellular B grooves lateral wall top be connected.In the insulated-gate bipolar transistor device
On section, the p-type floating region 3 of active cellular A groove bottom lands is separated from each other, the p-type floating region 3 of nonactive cellular B groove bottom lands
Can contact with each other, it is also possible to be separated from each other.
In the embodiment of the present invention, the first emitter metal 13 is by the second insulating medium layer 12 and the second emitter metal 11
It is dielectrically separated from, the emitter terminal of insulated-gate bipolar transistor device can be formed by the first emitter metal 13, by grid
Electrode metal 16 can form the gate electrode end of insulated-gate bipolar transistor device.
In the embodiment of the present invention, during break-over of device, the minority carrier of nonactive cellular B forms accumulation, further strengthens
The conductivity modulation effect of device, therefore, it can significantly reduce IGBT device saturation voltage drop, reduce conduction loss；Nonactive unit
The presence of born of the same parents B causes effective gate electrode area to reduce so that the grid of device and the electric capacity of transmitting interpolar and the grid of device
Substantially reduce with the electric capacity of inter-collector, reduce switching loss, improve the switching speed of device.It is active when being embodied as
The quantity of the quantity of active cellular A and nonactive cellular B in area 100, can be according to the tool of insulated-gate bipolar transistor device
Body use requirement is adjusted.
Further, first emitter metal 13 is connected with the second emitter metal 11 by diode, first
Emitter-base bandgap grading metal 13 is connected with the anode tap of diode, and the second emitter metal 11 is connected with the cathode terminal of diode.
In the embodiment of the present invention, the first emitter metal 13 after diode is connected with the second emitter metal 11, energy
Reduce device internal voltage imbalance, so as to reduce devices switch during electric current and voltage oscillation.When being embodied as,
First emitter metal 13 is connected by external diode with the second emitter metal, or by being arranged at the first interarea
On integrated diode be connected with the second emitter metal 11；Integrated diode is located at first master in terminal protection area 200
On face, integrated diode include diode P-type conduction region 7-2 and with the diode P-type conduction region 7-2 adjoin
Diode N-type conductive region 7-1.
Further, the terminal protection area 200 includes transition region C, field limiting ring structure D and cut-off ring structure E, described
Transition region C adjoins active area 100, ends the outer ring that ring structure E is located at terminal protection area 200, and field limiting ring structure D is located at transition region
Between C and cut-off ring structure E.
In the embodiment of the present invention, transition region C, field limiting ring structure D and cut-off ring structure E in a ring, in transition region C
Including the side of the p-type transition region 15 being arranged in N-type drift region 1, the p-type transition region 15 and the outmost turns groove of active area 100
The p-type floating region 3 of wall and the channel bottom is contacted.On corresponding first interarea of transition region C, dielectric isolation layer 24 is provided with
And be arranged at the active cellular of the dielectric isolation layer 24 and draw conductive polycrystalline silicon 25, active cellular draws conductive polycrystalline silicon 25
Isolated with p-type transition region 15 by dielectric isolation layer 24, active cellular draws conductive polycrystalline silicon 25 with activity unit in active area 100
Born of the same parents' conductive polycrystalline silicon 7 links into an integrated entity, and active cellular conductive polycrystalline silicon 7 draws conductive many by active cellular in active area 100
Crystal silicon 25 and the Ohmic contact of gate electrode metal 16.Active cellular draws conductive polycrystalline silicon 25 by the first insulating medium layer 10 and the
Two emitter metals 11 are dielectrically separated from.Gate electrode metal 16 is insulated by the second insulating medium layer 12 with the second emitter metal 11
Isolation.
In field limiting ring structure D, including the p-type field limiting ring 22 being arranged in N-type drift region 1, the p-type field limiting ring 22 with
P-type transition region 15 is same technique manufactures layer.The first insulating medium layer is additionally provided with the first interarea of the top of p-type field limiting ring 22
10 etc., field limiting ring structure D can adopt the version that the art is commonly used, specially known to those skilled in the art,
Here is omitted.
In cut-off ring structure E, including N+ cut-off rings 21, the cut-off ring metal on the N+ cut-offs interarea of ring 21 and first
17 Ohmic contacts, N+ cut-offs ring 21 and N+ launch sites 8 are same technique manufactures layer, the concrete structure of prosperous cut-off ring structure E and
Effect is same as the prior art, and specially known to the machine commandant personnel, here is omitted.
Further, P+ collecting zones 19, the P+ collecting zones 19 and N are provided with the second interarea of the semiconductor substrate
N+ electric fields cut-off region 18, P+ collecting zones 19 and the Ohmic contact of collector electrode metal 20 are provided between type drift region 1.The embodiment of the present invention
In, the doping content of N+ electric fields cut-off region 18 more than N-type drift region 1 doping content, P+ collecting zones 19 can be it is continuous,
Can be in discontinuous form, when P+ collecting zones 19 are in discontinuous form, collector electrode metal 20 and the Ohmic contact of N+ electric fields cut-off region 18,
The collector terminal of device can be formed by collector electrode metal 20.
As shown in Fig. 7～Figure 19, the above-mentioned insulated-gate bipolar transistor device with low conduction voltage drop, under can passing through
The manufacture method stated is prepared, and specifically, the manufacture method of the insulated-gate bipolar transistor device comprises the steps：
A, the semiconductor substrate with two opposing main faces is provided, two opposing main faces include the first interarea and with first
The second corresponding interarea of interarea, includes N-type drift region 1 between the first interarea and the second interarea；
As shown in fig. 7, the material of the semiconductor substrate includes silicon, certainly, semiconductor substrate can also adopt this technology
Other conventional materials of field, will not enumerate herein.
B, on the first interarea of above-mentioned semiconductor substrate deposit field oxide 14, the field oxide 14 cover semiconductor
First interarea of substrate；
As shown in figure 8, field oxide 14 is silicon dioxide layer, it is this that deposit obtains the specific embodiment of field oxide 14
Known to technical field personnel, here is omitted.
C, above-mentioned field oxide 14 is optionally sheltered and etches, to form ion implanting window, and using the ion
Injection window carries out the injection of p type impurity, pushes away main knot, the field limiting ring structure D and P needed for being formed in semiconductor substrate after trap
Xing Weiti areas 2；
As shown in figure 9, ion implanting window insertion field oxide 14, N can be injected using ion implanting window by p type impurity
In type drift region 1, p type impurity injects and pushes away the specific embodiment of trap and is known to those skilled in the art, herein not
Repeat again.The master becomes the PN junction formed by the N-type drift region 1 of p-type transition region 15 and the lower section of the p-type transition region 15, P
Xing Weiti areas 2 are located in active area 100, and main knot and field limiting ring structure D are respectively positioned in terminal protection area 200.
D, the field oxide 14 removed on above-mentioned semiconductor substrate active area 100, and the field oxide 14 needed for removing
Afterwards, hard mask layer 27 is deposited on the first interarea, the hard mask layer 27 is covered on the first interarea of active area 100, and is covered
Cover on first interarea and field oxide 14 in terminal protection area 200；
As shown in Figure 10, the field oxide 14 on active area 100 is removed using modes such as photoresist maskings, field oxidation is removed
The detailed process of layer 14 is that here is omitted known to those skilled in the art.Hard mask layer 14 is LPTEOS, thermal oxide
Silica adds chemical vapor deposition silica or thermal silicon dioxide plus silicon nitride.Due to the field oxide on active area 100
14 all remove, and the field oxide 14 in terminal protection area 200 is retained, therefore, hard mask layer 27 has been directly overlayed
First interarea of source region 100, and it is covered in the field oxide 14 in terminal protection area 200 and the of part terminal protection area 200
One interarea.
E, above-mentioned hard mask layer 27 is optionally sheltered and etches, to obtain required hard mask window, using described hard
Mask window is performed etching to semiconductor substrate, to form multiple grooves in the N-type drift region 1 of semiconductor substrate；Formed
The first interarea top implanting p-type impurity of the semiconductor substrate of groove, after pushing away trap, the p-type floating region 3 needed for being formed, the p-type
Floating region 3 coats the bottom land of groove；
As shown in figure 11, the technological means commonly used using the art, can etch hard mask layer 27 and obtain hard mask windows
Mouthful, the hard mask window insertion hard mask layer 27, using hard mask window, to N-type drift region 1 anisotropic etching is carried out,
Can obtain some grooves, the groove vertically extends from the first interarea into N-type drift region 1.After formation of the groove, by note
Enter p type impurity, p-type floating region 3 can be obtained, it is those skilled in the art that p type impurity injects and push away the specific embodiment of trap
Known, here is omitted.
F, the hard mask layer 27 removed on the above-mentioned interarea of semiconductor substrate first, and after hard mask layer 27 is removed, upper
The inwall and diapire growth insulation gate oxide 6 of groove is stated, and has filling in the groove of insulation gate oxide 6 conductive many in growth
Crystal silicon；
Specifically, the technological means commonly used using the art, can realize the removal of hard mask layer 27, and insulate gate oxidation
Layer 6 can be obtained by thermal oxide growth, after growth has insulation gate oxide 6, by depositing conductive polycrystalline in the first interarea
Silicon, can realize that conductive polycrystalline silicon is filled in groove.After in the filling groove, need to lead respective regions on the first interarea
Electric etching polysilicon is removed, to carry out follow-up technique.The technological means commonly used using the art is realized corresponding conductive
The etching of polysilicon is removed, and specially known to those skilled in the art, here is omitted.
G, on the first interarea of above-mentioned semiconductor substrate the first photoresist layer is coated, institute is being carried out to the first photoresist layer
After the etching for needing, N-type impurity is injected above the first interarea, with the N needed for being formed in the N-type drift region 1 of semiconductor substrate
Type carrier accumulation layer 4；
Specifically, the first photoresist layer is coated on the first interarea, and after performing etching to the first photoresist layer, be easy into
The injection of row N-type impurity, with the N-type carrier accumulation layer 4 needed for being formed in active area 100, as shown in figure 12, concrete technology
Process is that here is omitted known to those skilled in the art.
Additionally, when the first emitter metal 13 is connected with the second emitter metal 11 using integrated diode, in shape
During into N-type carrier accumulation layer 4, moreover it is possible to diode N-type conductive region 7-1, diode are formed on the first interarea of transition region C
N-type conductive region 7-1 can carry out N-type impurity injection and obtain by the conductive polycrystalline silicon on the interarea of transition region C first.
H, above-mentioned first photoresist layer of removal, and the second photoresist layer is coated on the first interarea of semiconductor substrate,
After etching needed for carrying out to the second photoresist layer, the implanting p-type impurity above the first interarea, with the drift of the N-type of semiconductor substrate
Move in area 1 and form PXing Ti areas 5, the PXing Ti areas 5 are located at the surface of N-type carrier accumulation layer 4, NXing Ti areas 5 and N-type current-carrying
Sub- accumulation layer contacts；
As shown in figure 13, the technological means commonly used using the art, can remove the first photoresist layer, to the second light
After photoresist layer etching, p type impurity can be convenient for, to obtain PXing Ti areas 5.Additionally, can also on the first interarea of transition region C
Diode P-type conduction region 7-2 is formed, diode P-type conduction region 7-2 is connected with diode N-type conductive region 71-, with shape
Into the structure of diode.
I, above-mentioned second photoresist layer of removal, and the 3rd photoresist layer is coated on the first interarea of semiconductor substrate,
After etching needed for carrying out to the 3rd photoresist layer, N-type impurity is injected above the first interarea, to be formed in semiconductor substrate
N+ launch sites 8 and N+ cut-off regions 21；
Specifically, the technological means commonly used using the art, removes the second photoresist layer；In coating simultaneously photoetching the 3rd
After photoresist layer, N-type impurity injection is carried out, obtain N+ launch sites 8 and N+ cut-off regions 21, N+ launch sites 8 are located at active area 100
It is interior.After N+ launch sites 8 and N+ cut-off regions 21 is obtained, the 3rd photoresist layer is removed.
K, the first insulating medium layer 10 is deposited on the first interarea of above-mentioned semiconductor substrate, and the described first insulation is situated between
Matter layer 10 is performed etching, and the top of the first insulating medium layer 10 after etching carries out p type impurity injection, with semiconductor substrate
Active area 100 in formed needed for p-type ohmic contact regions；
As shown in figure 14, after performing etching to the first insulating medium layer 10, can cause in active area 100, the first insulation
The notch of the covering part groove of dielectric layer 10, additionally, the first insulating medium layer 10 after using etching, can realize that p type impurity is noted
Enter, obtain p-type ohmic contact regions, specifically, the p-type ohmic contact regions include that p-type activity ohmic contact regions 9 and p-type are non-
Active ohmic contact regions 26, p-type active contact area 9 contacts with N+ launch sites 8, and the first of the top of p-type activity ohmic contact regions 9 is exhausted
Edge dielectric layer 10 is etched.The both sides of the nonactive ohmic contact regions 26 of p-type are without N+ launch sites 8.
L, the second emitter metal 11 is set on the first interarea of above-mentioned semiconductor substrate, the second emitter metal 11 with
Conductive polycrystalline silicon Ohmic contact in corresponding p-type ohmic contact regions and respective groove, to form required nonactive cellular
B；
As shown in figure 15, because when etching to the first insulating medium layer 10, the notch of part of trench is in open state,
When the second emitter metal 11 is deposited, the second emitter metal 11 and the nonactive ohmic contact regions 26 of p-type and underface
Conductive polycrystalline silicon Ohmic contact, after forming nonactive cellular B, the conductive polycrystalline silicon becomes nonactive cellular conductive polycrystalline silicon
23.When the second emitter metal 11 is obtained, the second emitter metal 11 can connect with diode N-type conductive region 7-1 ohms
Touch.
N, the second insulating medium layer 12 is deposited on the first interarea of above-mentioned semiconductor substrate, and the described second insulation is situated between
Matter layer 12 forms the second required insulating medium layer contact hole after etching；
As shown in figure 16, deposit after the second insulating medium layer 12, in desired position region the second insulating medium layer is formed
Contact hole, the position of the second insulating medium layer contact hole can be selected as needed, specially those skilled in the art institute
Know, here is omitted.
O, on the first interarea of above-mentioned semiconductor substrate, deposited metal, to the metal level for obtaining etching after, formed
Required the first emitter metal 13, gate electrode metal 16 and cut-off ring metal 17, the first emitter metal 13 is launched with N+
Area 8 and corresponding p-type ohmic contact regions Ohmic contact, are removed and second with being formed in required active cellular A, N-type drift region 1
The conductive polycrystalline silicon of the Ohmic contact of emitter metal 11 ends with the Ohmic contact of gate electrode metal 16, cut-off ring metal 17 and N+
The Ohmic contact of area 21；
As shown in figure 17, in deposited metal, and after etching, using the second above-mentioned insulating medium layer contact hole, can make
The first emitter metal 13 is obtained with N+ launch sites 8 and p-type activity ohmic contact regions 9 Ohmic contact, cut-off ring metal 17 and N+
The Ohmic contact of cut-off region 21.In active area 100, form nonactive with the conductive polycrystalline silicon of the Ohmic contact of the second emitter metal 11
Cellular conductive polycrystalline silicon 23, the conductive polycrystalline silicon in remaining groove forms active cellular conductive polycrystalline silicon 7, and active cellular is conductive more
Crystal silicon 7 is parallel with one another, and draws conductive polycrystalline silicon 25 and the Ohmic contact of gate electrode metal 16 by the active cellular in transition region,
Active cellular is drawn conductive polycrystalline silicon 25 and is obtained for same process layer, i.e. step f with active cellular conductive polycrystalline silicon 7, concrete system
Standby process is that here is omitted known to those skilled in the art.
P, the N+ electric fields cut-off region 18 needed for the second interarea of above-mentioned semiconductor substrate is formed and P+ collecting zones 19, N+
Electric field cut-off region 18 is located between N-type drift region 1 and P+ collecting zones 19, and P+ collecting zones 19 are adjoined with N+ electric fields cut-off region 18；
As shown in figure 18, the doping content of N+ electric fields cut-off region 18 usually, is gone back more than the doping content of N-type drift region 1
Second interarea of semiconductor substrate can be carried out thinning, concrete thinning technical process is known to those skilled in the art,
Here is omitted.
Q, required collector electrode metal 20 is deposited on above-mentioned P+ collecting zones 19, the collector electrode metal 20 and P+ collecting zones
Ohmic contact.
As shown in figure 19, the collector terminal of device can be formed by collector electrode metal 20.
During break-over of device of the present invention, positioned at the N-type carrier accumulation layer 4 of the bottom of PXing Ti areas 5, due to depositing for Built-in potential
Circulation of the minority carrier to emitter stage can be being hindered, the accumulation of minority carrier can formed, conductivity modulation effect is strengthening；Together
When, the accumulation of nonactive cellular B areas minority carrier further enhances the conductivity modulation effect of device, therefore, it can significantly
IGBT device saturation voltage drop is reduced, conduction loss is reduced；When device is blocked, positioned at the presence of p-type floating region 3, to active cellular
A bodies area of area is shielded, therefore, it is possible to when N-type carrier 4 concentration of accumulation layer is adjusted, it is ensured that it is unaffected that device is pressure.
The presence in nonactive cellular B areas causes effective gate electrode area to reduce so that the electric capacity of gate electrode and transmitting interpolar,
And gate electrode is substantially reduced with the electric capacity of inter-collector, reduces switching loss, improves the switching speed of device；It is nonactive
Cellular B areas, the second emitter metal 11 and the nonactive Ohmic contact of cellular conductive polycrystalline silicon 23, and connect with the cathode terminal of diode
Connect, reduce the Voltage unbalance inside IGBT structure, it is thereby possible to reduce the electric current, oscillation during devices switch.
Claims (8)
1. a kind of insulated-gate bipolar transistor device with low conduction voltage drop, in the insulated gate bipolar transistor device
In the top plan view of part, including the active area on semiconductor substrate and terminal protection area, the active area is located at and partly leads
The center of structure base board, terminal protection area is located at the outer ring of active area, and around the encirclement active area；It is double in the insulated gate
On the section of bipolar transistor device, semiconductor substrate has the first interarea and the second interarea corresponding with the first interarea, institute
State and include between the first interarea and the second interarea the first conduction type drift region；It is characterized in that：
On the section of the insulated-gate bipolar transistor device, the cellular of the active area adopts groove structure, described to have
Source region cellular includes active cellular and nonactive cellular；The trench wall of active cellular and diapire growth have insulation gate oxidation
Layer, has in the active cellular groove of insulation gate oxide in the growth and fills active cellular conductive polycrystalline silicon, active cellular
The notch of groove is covered by the first insulating medium layer；The second conductivity type body region is provided between adjacent active cellular groove, and in institute
The bottom for stating the second conductivity type body region is provided with the first conduction type carrier accumulation layer；It is provided with the second conductivity type body region
First conduction type launch site and the second conduction type activity ohmic contact regions, the first conduction type launch site and active cellular
The lateral wall contact of groove, the second conduction type activity ohmic contact regions are located at the first conduction type transmitting interval, and and both sides
The first conduction type launch site contact；First conduction type launch site, the second conduction type activity ohmic contact regions and first
The first emitter metal Ohmic contact above interarea；Gate electrode metal above active cellular conductive polycrystalline silicon and the first interarea
Ohmic contact；
The trench wall of nonactive cellular and diapire growth have insulation gate oxide, have insulation gate oxide in the growth
Nonactive cellular conductive polycrystalline silicon is filled with nonactive cellular groove, in the both sides of the nonactive cellular groove the is equipped with
Two conduction type Wei Ti areas, in the second conduction type Wei Ti areas the nonactive ohmic contact regions of the second conduction type are provided with,
The nonactive ohmic contact regions of second conduction type contact with the lateral wall of nonactive cellular groove, the second conduction type non-live
Property ohmic contact regions and nonactive cellular conductive polycrystalline silicon with the first interarea on the second emitter metal Ohmic contact；The
Two emitter metals are dielectrically separated from the first emitter metal；
The second conduction type floating region is equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove, activity
The bottom land of the active cellular groove of the second conduction type floating region cladding of cellular beneath trenches, the of nonactive cellular beneath trenches
Two conduction type floating regions coat the bottom land of nonactive cellular groove.
2. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, is characterized in that：Institute
State the first emitter metal to be connected by diode with the second emitter metal, the anode tap of the first emitter metal and diode
Connection, the second emitter metal is connected with the cathode terminal of diode.
3. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 2, is characterized in that：Institute
State the first emitter metal to be connected with the second emitter metal by external diode, or by being arranged on the first interarea
Integrated diode is connected with the second emitter metal；Integrated diode is located on first interarea in terminal protection area, integrated
Formula diode includes diode P-type conduction region and the diode N-type conduction region with the diode P-type conduction area adjacency
Domain.
4. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, is characterized in that：Institute
Terminal protection area is stated including transition region, field limiting ring structure and cut-off ring structure, the transition region adjoins active area, cut-off ring knot
Structure is located at the outer ring in terminal protection area, and field limiting ring structure is located between transition region and cut-off ring structure.
5. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, is characterized in that：
Second interarea of the semiconductor substrate is provided with the second conduction type collecting zone, the second conduction type collecting zone and first
Conduction type drift interval is provided with the first conduction type electric field cut-off region, the second conduction type collecting zone and collector electrode metal ohm
Contact.
6. a kind of manufacture method of the insulated-gate bipolar transistor device with low conduction voltage drop, is characterized in that, the insulation
The manufacture method of grid bipolar transistor device comprises the steps：
（a）, the semiconductor substrate with two opposing main faces is provided, two opposing main faces include the first interarea and with the first master
The second corresponding interarea of face, includes the first conduction type drift region between the first interarea and the second interarea；
（b）, deposit on the first interarea of above-mentioned semiconductor substrate field oxide, the field oxide covers semiconductor substrate
First interarea；
（c）, optionally shelter and etch above-mentioned field oxide, to form ion implanting window, and using the ion implanting
Window carries out the injection of the second conductive type impurity, pushes away main knot, field limiting ring structure needed for being formed in semiconductor substrate after trap
And the second conduction type Wei Ti area；
（d）, after the field oxide removed on above-mentioned semiconductor substrate active area, and the field oxide needed for removing, first
Hard mask layer is deposited on interarea, the hard mask layer is covered on the first interarea of active area, and be covered in terminal protection area
On first interarea and field oxide；
（e）, optionally shelter and etch above-mentioned hard mask layer, to obtain required hard mask window, using the hard mask
Window is performed etching to semiconductor substrate, to form multiple grooves in the first conduction type drift region of semiconductor substrate；
Form second conductive type impurity of the first interarea top injection of the semiconductor substrate of groove, after pushing away trap, second needed for being formed
Conduction type floating region, the second conduction type floating region coats the bottom land of groove；
（f）, the hard mask layer removed on the above-mentioned interarea of semiconductor substrate first, and after hard mask layer is removed, in above-mentioned groove
Inwall and diapire growth insulation gate oxide, and growth have insulation gate oxide groove in fill conductive polycrystalline silicon；
（g）, on the first interarea of above-mentioned semiconductor substrate the first photoresist layer is coated, needed for carrying out to the first photoresist layer
Etching after, the first conductive type impurity is injected above the first interarea, with the first conduction type of semiconductor substrate drift
The first conduction type carrier accumulation layer needed for being formed in area；
（h）, remove above-mentioned first photoresist layer, and the second photoresist layer is coated on the first interarea of semiconductor substrate, right
After second photoresist layer is etched needed for carrying out, the second conductive type impurity is injected above the first interarea, with semiconductor substrate
The first conduction type drift region in formed the second conductivity type body region, second conductivity type body region be located at the first conductive-type
Directly over type carrier accumulation layer, the second conductivity type body region contacts with the first conduction type carrier accumulation layer；
（i）, remove above-mentioned second photoresist layer, and the 3rd photoresist layer is coated on the first interarea of semiconductor substrate, right
3rd photoresist layer is carried out after required etching, the first conductive type impurity is injected above the first interarea, with semiconductor-based
The first conduction type launch site and the first conduction type cut-off region are formed in plate；
（k）, the first insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, and to first insulating medium layer
Perform etching, and the first insulating medium layer top after etching carries out the second conductive type impurity injection, with semiconductor-based
The second conduction type ohmic contact regions needed for being formed in the active area of plate；
（l）, the second emitter metal is set on the first interarea of above-mentioned semiconductor substrate, the second emitter metal with it is corresponding
Conductive polycrystalline silicon Ohmic contact in second conduction type ohmic contact regions and respective groove, to form required nonactive unit
Born of the same parents；
（n）, the second insulating medium layer is deposited on the first interarea of above-mentioned semiconductor substrate, and to second insulating medium layer
The second required insulating medium layer contact hole is formed after etching；
（o）, on the first interarea of above-mentioned semiconductor substrate, deposited metal, to the metal level for obtaining etching after, formed institute
The first emitter metal, gate electrode metal and the cut-off ring metal for needing, the first emitter metal is launched with the first conduction type
Area and corresponding second conduction type ohmic contact regions Ohmic contact, to form required active cellular, the first conduction type
In drift region except with the conductive polycrystalline silicon of the second emitter metal Ohmic contact with gate electrode metal Ohmic contact, cut-off ring gold
Category and the first conduction type cut-off region Ohmic contact；
（p）, the first conduction type electric field cut-off region needed for the second interarea of above-mentioned semiconductor substrate is formed and second lead
Electric type collecting zone, the first conduction type electric field cut-off region is located at the first conduction type drift region and the second conduction type current collection
Interval, and the second conduction type collecting zone is adjacent with the first conduction type electric field cut-off region；
（q）, deposit on above-mentioned second conduction type collecting zone required collector electrode metal, the collector electrode metal is led with second
Electric type collecting zone Ohmic contact.
7. there is according to claim 6 the manufacture method of the insulated-gate bipolar transistor device of low conduction voltage drop, it is special
Levying is：The material of the semiconductor substrate includes silicon.
8. the manufacture method of the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 6, its
It is characterized in that：Step（g）In, when the first conduction type carrier accumulation layer is formed, on the first interarea of semiconductor substrate also
Form diode N-type conductive region；In step（h）In, when the second conductivity type body region is formed, the first of semiconductor substrate
Diode P-type conduction region is also formed on interarea, the diode P-type conduction region adjoins with diode N-type conductive region, with
Form integrated diode；Second emitter metal and diode N-type conductive region Ohmic contact, the first emitter metal and two
Pole pipe P-type conduction region Ohmic contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611089631.0A CN106653836B (en) | 2016-12-01 | 2016-12-01 | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611089631.0A CN106653836B (en) | 2016-12-01 | 2016-12-01 | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106653836A true CN106653836A (en) | 2017-05-10 |
| CN106653836B CN106653836B (en) | 2023-09-01 |
Family
ID=58813968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611089631.0A Active CN106653836B (en) | 2016-12-01 | 2016-12-01 | Insulated gate bipolar transistor device with low on-voltage drop and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106653836B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275381A (en) * | 2017-06-14 | 2017-10-20 | 四川大学 | A kind of dual carrier stores enhanced IGBT |
| CN107658343A (en) * | 2017-10-31 | 2018-02-02 | 无锡新洁能股份有限公司 | A kind of semiconductor structure and its manufacture method of optimised devices characteristic |
| CN108054206A (en) * | 2017-10-24 | 2018-05-18 | 全球能源互联网研究院 | A kind of power device terminal structure of transverse direction structure cell and preparation method thereof |
| CN108511512A (en) * | 2018-02-05 | 2018-09-07 | 东南大学 | A kind of power semiconductor and preparation method thereof with undaform field limiting ring structure |
| CN108899363A (en) * | 2018-08-29 | 2018-11-27 | 江苏中科君芯科技有限公司 | The trench gate IGBT device of conduction voltage drop and turn-off power loss can be reduced |
| CN108933078A (en) * | 2017-05-25 | 2018-12-04 | 中芯国际集成电路制造(上海)有限公司 | The forming method and structure of doped region and IGBT device |
| CN110137250A (en) * | 2019-04-12 | 2019-08-16 | 电子科技大学 | A kind of High Speed I GBT device with ultralow conduction voltage drop |
| CN110379852A (en) * | 2019-08-21 | 2019-10-25 | 江苏中科君芯科技有限公司 | The groove-shaped IGBT device of miller capacitance can be reduced |
| CN111834449A (en) * | 2020-07-27 | 2020-10-27 | 重庆邮电大学 | Quick turn-off RC-IGBT device with back double-MOS structure |
| CN111900089A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111900090A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN113659014A (en) * | 2021-10-20 | 2021-11-16 | 四川洪芯微科技有限公司 | Power diode with cathode short-circuit groove grid structure |
| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
| CN115394834A (en) * | 2022-07-29 | 2022-11-25 | 安世半导体科技(上海)有限公司 | IGBT cellular structure with control grid and carrier storage layer and manufacturing method thereof |
| CN116190227A (en) * | 2023-04-27 | 2023-05-30 | 北京贝茵凯微电子有限公司 | IGBT chip preparation method and IGBT chip |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280487A (en) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof |
| CN103985746A (en) * | 2014-06-05 | 2014-08-13 | 无锡新洁能股份有限公司 | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof |
| CN104576743A (en) * | 2015-01-28 | 2015-04-29 | 无锡新洁能股份有限公司 | Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device |
| CN104716192A (en) * | 2015-03-31 | 2015-06-17 | 无锡新洁能股份有限公司 | Power MOS device capable of achieving voltage resistance by charge coupling and preparation method thereof |
| CN105633139A (en) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | IGBT device with carrier storage structure and manufacturing method of IGBT device |
| CN206194743U (en) * | 2016-12-01 | 2017-05-24 | 无锡新洁能股份有限公司 | Insulated -gate bipolar transistor device with hang down and switch on pressure drop |
-
2016
- 2016-12-01 CN CN201611089631.0A patent/CN106653836B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102280487A (en) * | 2011-08-22 | 2011-12-14 | 无锡新洁能功率半导体有限公司 | Power MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) device of novel groove structure and manufacture method thereof |
| CN103985746A (en) * | 2014-06-05 | 2014-08-13 | 无锡新洁能股份有限公司 | Groove type IGBT (Insulated Gate Bipolar Transistor) device and manufacturing method thereof |
| CN104576743A (en) * | 2015-01-28 | 2015-04-29 | 无锡新洁能股份有限公司 | Deep-groove power MOS (metal oxide semiconductor) device with ultrahigh cellular density and manufacturing method of deep-groove power MOS device |
| CN104716192A (en) * | 2015-03-31 | 2015-06-17 | 无锡新洁能股份有限公司 | Power MOS device capable of achieving voltage resistance by charge coupling and preparation method thereof |
| CN105633139A (en) * | 2016-03-23 | 2016-06-01 | 无锡新洁能股份有限公司 | IGBT device with carrier storage structure and manufacturing method of IGBT device |
| CN206194743U (en) * | 2016-12-01 | 2017-05-24 | 无锡新洁能股份有限公司 | Insulated -gate bipolar transistor device with hang down and switch on pressure drop |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108933078B (en) * | 2017-05-25 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method and structure of doped region and IGBT device |
| CN108933078A (en) * | 2017-05-25 | 2018-12-04 | 中芯国际集成电路制造(上海)有限公司 | The forming method and structure of doped region and IGBT device |
| CN107275381B (en) * | 2017-06-14 | 2019-08-13 | 四川大学 | A kind of IGBT of dual carrier storage enhancing |
| CN107275381A (en) * | 2017-06-14 | 2017-10-20 | 四川大学 | A kind of dual carrier stores enhanced IGBT |
| CN108054206A (en) * | 2017-10-24 | 2018-05-18 | 全球能源互联网研究院 | A kind of power device terminal structure of transverse direction structure cell and preparation method thereof |
| CN107658343A (en) * | 2017-10-31 | 2018-02-02 | 无锡新洁能股份有限公司 | A kind of semiconductor structure and its manufacture method of optimised devices characteristic |
| CN107658343B (en) * | 2017-10-31 | 2024-03-12 | 无锡新洁能股份有限公司 | Semiconductor structure for optimizing device characteristics and manufacturing method thereof |
| CN108511512A (en) * | 2018-02-05 | 2018-09-07 | 东南大学 | A kind of power semiconductor and preparation method thereof with undaform field limiting ring structure |
| CN108899363A (en) * | 2018-08-29 | 2018-11-27 | 江苏中科君芯科技有限公司 | The trench gate IGBT device of conduction voltage drop and turn-off power loss can be reduced |
| CN108899363B (en) * | 2018-08-29 | 2023-08-15 | 江苏中科君芯科技有限公司 | Trench gate IGBT device capable of reducing on-voltage drop and turn-off loss |
| CN110137250A (en) * | 2019-04-12 | 2019-08-16 | 电子科技大学 | A kind of High Speed I GBT device with ultralow conduction voltage drop |
| CN110137250B (en) * | 2019-04-12 | 2020-12-29 | 电子科技大学 | High-speed IGBT device with ultralow conduction voltage drop |
| CN110379852A (en) * | 2019-08-21 | 2019-10-25 | 江苏中科君芯科技有限公司 | The groove-shaped IGBT device of miller capacitance can be reduced |
| CN110379852B (en) * | 2019-08-21 | 2022-10-11 | 江苏中科君芯科技有限公司 | Groove type IGBT device capable of reducing Miller capacitance |
| CN111834449A (en) * | 2020-07-27 | 2020-10-27 | 重庆邮电大学 | Quick turn-off RC-IGBT device with back double-MOS structure |
| CN111834449B (en) * | 2020-07-27 | 2024-04-16 | 重庆邮电大学 | Quick turn-off RC-IGBT device with back double MOS structure |
| CN111900090A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111900089B (en) * | 2020-08-26 | 2024-01-19 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111900090B (en) * | 2020-08-26 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN111900089A (en) * | 2020-08-26 | 2020-11-06 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing super junction device |
| CN113659014B (en) * | 2021-10-20 | 2022-01-18 | 四川洪芯微科技有限公司 | Power diode with cathode short-circuit groove grid structure |
| CN113659014A (en) * | 2021-10-20 | 2021-11-16 | 四川洪芯微科技有限公司 | Power diode with cathode short-circuit groove grid structure |
| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
| CN114927535B (en) * | 2022-05-20 | 2023-09-22 | 无锡鉴微华芯科技有限公司 | X-ray detector with double three-dimensional full-surrounding protection ring and preparation method thereof |
| CN115394834A (en) * | 2022-07-29 | 2022-11-25 | 安世半导体科技(上海)有限公司 | IGBT cellular structure with control grid and carrier storage layer and manufacturing method thereof |
| CN115394834B (en) * | 2022-07-29 | 2024-01-09 | 安世半导体科技(上海)有限公司 | IGBT cell structure with control grid and carrier storage layer and manufacturing method thereof |
| CN116190227A (en) * | 2023-04-27 | 2023-05-30 | 北京贝茵凯微电子有限公司 | IGBT chip preparation method and IGBT chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106653836B (en) | 2023-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106653836A (en) | Insulated gate bipolar transistor device with low conduction voltage drop, and manufacturing method for insulated gate bipolar transistor device | |
| CN107799582A (en) | A kind of trench gate electric charge memory type insulated gate bipolar transistor and its manufacture method | |
| CN107799587A (en) | A kind of reverse blocking IGBT and its manufacture method | |
| CN105932042A (en) | Double-split groove gate charge storage type IGBT and manufacturing method thereof | |
| CN105633139B (en) | IGBT device and its manufacturing method with carrier storage organization | |
| CN206022371U (en) | Igbt (IGBT) | |
| CN107403839A (en) | Suitable for the power semiconductor device structure and manufacture method of deep trench | |
| CN104332495B (en) | A kind of igbt and its manufacture method | |
| CN107731899A (en) | A kind of trench gate electric charge memory type IGBT device and its manufacture method with Pliers bit architectures | |
| CN105932055A (en) | Plane gate IGBT and manufacturing method therefor | |
| CN107611179A (en) | Reduce shield grid MOSFET structure of gate-source capacitance and preparation method thereof | |
| CN105448997B (en) | Improve the superjunction MOS device and its manufacturing method of reverse recovery characteristic and avalanche capacity | |
| CN104319287A (en) | Trench gate type semiconductor device structure and manufacturing method thereof | |
| CN206976354U (en) | Suitable for the power semiconductor device structure of deep trench | |
| CN104425579B (en) | Silicon-on-insulator reverse-conducting lateral insulated gate bipolar transistor and preparation method thereof | |
| CN115831758A (en) | Manufacturing method of silicon carbide UMOSFET integrated with Schottky | |
| CN110444586B (en) | Trench gate IGBT device with shunt area and preparation method | |
| CN205488135U (en) | IGBT device with charge carrier storage structure | |
| CN105789291A (en) | Double split trench gate charge storage type insulated gate bipolar transistor (IGBT) and manufacturing method thereof | |
| CN107634095A (en) | Trench semiconductor power device and preparation method thereof | |
| CN110473914A (en) | A kind of preparation method of SiC-MOS device | |
| CN114141621A (en) | Carrier storage groove gate bipolar transistor with split gate and preparation method thereof | |
| CN105409006A (en) | Semiconductor device | |
| CN106158927A (en) | A kind of super-junction semiconductor device optimizing switching characteristic and manufacture method | |
| CN109244128A (en) | A kind of semi-enclosed shield grid IEGT device architecture and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |