CN206194743U - Insulated -gate bipolar transistor device with hang down and switch on pressure drop - Google Patents

Abstract

The utility model relates to an insulated -gate bipolar transistor device with hang down and switch on pressure drop, it is including being located active area and the terminal protection zone on the semiconductor substrate on the cross -section of insulated -gate bipolar transistor device, the cellular of active area adopts the groove structure, active cellular includes active cellular and nonactive cellular, all be equipped with the 2nd conductivity type floating region at the tank bottom of the tank bottom of active cellular slot and nonactive cellular slot, the tank bottom of the active cellular slot of the 2nd conductivity type floating region cladding of active cellular slot below, the tank bottom of the nonactive cellular slot of the 2nd conductivity type floating region cladding of nonactive cellular slot below. The utility model discloses can guarantee under the overpressure resistant circumstances to have extremely low pressure drop and the extremely fast switch -off speed of switching on, and have lower current -voltage and vibrate, improve the reliability of work greatly.

Description

Insulated-gate bipolar transistor device with low conduction voltage drop

Technical field

The utility model is related to a kind of insulated-gate bipolar transistor device, especially a kind of with the exhausted of low conduction voltage drop Edge grid bipolar transistor device, belongs to the technical field of semiconductor devices.

Background technology

The full name of IGBT is Insulate Gate Bipolar Transistor, i.e. igbt.It is simultaneous Have the multiple advantages of MOSFET and GTR, greatly extend the application field of power semiconductor.Partly led as novel electric power The main representative of body device, IGBT is widely used in industry, information, new energy, medical science, traffic, military affairs and aviation field.IGBT It is one of currently the most important ones power device, due to high with input impedance, on-state voltage drop is low, and drive circuit is simple, peace for IGBT Full workspace is wide, the advantages of current handling capability is strong, the attention of people is increasingly caused in various power switch applications.It Motor control, IF switch power supply and inverter, robot, air-conditioning and the quick low-loss many fields of requirement have extensively Application.

Since IGBT inventions, people are devoted to improving the performance of IGBT always.By the development of twenties years, carry in succession Various IGBT device structures are gone out, device performance has been obtained steady lifting.By using dummy trench gate electrodes, industry Propose IEGT device architectures.IEGT device dummy trench gate electrodes cause that the spacing between trench gate increases, and reduce transmitting The extracting channel of extreme minority carrier, introduces the carrier enhancement effect of device emitter terminal, enhances the load of drift region Stream injection, this improves the conductance modulation of N-type drift region, improves the carrier concentration profile of whole N-type drift region, IGBT is set to obtain the compromise of low forward conduction voltage drop and the forward conduction voltage drop and turn-off power loss that improve.

However, for IEGT device architectures, 1）, due to the use of dummy trench gate electrodes, cause：Device grids electric capacity （Particularly grid-collector capacitance）Greatly, however the switching process of IGBT device is exactly the mistake rushed to grid capacitance, discharged Journey, grid capacitance more favourable opposition, discharge time grid capacitance more long, big（Particularly grid-collector capacitance）Reduce device Switching speed, increase the switching loss of device, have impact on the forward conduction voltage drop of device and the compromise characteristic of switching loss； 2）, due to the presence in floating body area, cause：Internal current potential is inconsistent in break-over of device turn off process, shows larger electricity Pressure, current oscillation, bring serious EMI problems, have a strong impact on system reliability.

In view of defect of the prior art above, a kind of new construction of effective raising IGBT performances and its manufacture method Proposition is extremely necessary.

The content of the invention

The purpose of this utility model is to overcome the deficiencies in the prior art, there is provided a kind of with the exhausted of low conduction voltage drop Edge grid bipolar transistor device, its compact conformation can be in the case where guarantee be pressure-resistant, with extremely low conduction voltage drop and pole Fast turn-off speed, and vibrated with relatively low Current Voltage, greatly improve the reliability of work.

According to the technical scheme that the utility model is provided, the insulated gate bipolar transistor with low conduction voltage drop Device, in the top plan view of the insulated-gate bipolar transistor device, including active area on semiconductor substrate with And terminal protection area, positioned at the center of semiconductor substrate, terminal protection area is located at the outer ring of active area, and ring to the active area Around the encirclement active area；On the section of the insulated-gate bipolar transistor device, semiconductor substrate has the first interarea And the second interarea corresponding with the first interarea, the first conduction type drift region is included between first interarea and the second interarea；

On the section of the insulated-gate bipolar transistor device, the active area cellular uses groove structure, described Active area cellular includes active cellular and nonactive cellular；Trench wall and the bottom wall growth of active cellular have insulation grid oxygen Change layer, have in the growth and active cellular conductive polycrystalline silicon is filled in the active cellular groove of insulation gate oxide, activity unit The notch of born of the same parents' groove is covered by the first insulating medium layer；It is provided with the second conductivity type body region between adjacent active cellular groove, and The bottom of second conductivity type body region is provided with the first conduction type carrier accumulation layer；Set in the second conductivity type body region There are the first conduction type launch site and the second conduction type activity ohmic contact regions, the first conduction type launch site and activity unit The lateral wall contact of born of the same parents' groove, the second conduction type activity ohmic contact regions are located at the first conduction type and launch interval, and with two The first conduction type launch site contact of side；First conduction type launch site, the second conduction type activity ohmic contact regions and the The first emitter metal Ohmic contact above one interarea；Gate electrode gold above active cellular conductive polycrystalline silicon and the first interarea Category Ohmic contact；

Trench wall and the bottom wall growth of nonactive cellular have insulation gate oxide, have insulation gate oxidation in the growth Nonactive cellular conductive polycrystalline silicon is filled with the nonactive cellular groove of layer, is all provided with the both sides of the nonactive cellular groove There are the second conduction type Wei Ti areas, the nonactive Ohmic contact of the second conduction type is provided with the second conduction type Wei Ti areas Area, the nonactive ohmic contact regions of the second conduction type contact with the lateral wall of nonactive cellular groove, the second conduction type Nonactive ohmic contact regions and nonactive cellular conductive polycrystalline silicon connect with the second emitter metal ohm on the first interarea Touch；Second emitter metal is dielectrically separated from the first emitter metal；

The second conduction type floating region is equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove, The bottom land of the active cellular groove of the second conduction type floating region cladding of active cellular beneath trenches, nonactive cellular beneath trenches The second conduction type floating region coat the bottom land of nonactive cellular groove.

First emitter metal is connected with the second emitter metal by diode, the first emitter metal and two poles The anode tap connection of pipe, the second emitter metal is connected with the cathode terminal of diode.

First emitter metal is connected by external diode with the second emitter metal, or by being arranged at Integrated diode on one interarea is connected with the second emitter metal；Integrated diode is located at first master in terminal protection area On face, integrated diode includes diode P-type conduction region and the diode with the diode P-type conduction area adjacency N-type conductive region.

The terminal protection area includes transition region, field limiting ring structure and cut-off ring structure, and the transition region adjoining is active Area, cut-off ring structure is located at the outer ring in terminal protection area, and field limiting ring structure is located between transition region and cut-off ring structure.

The second conduction type collecting zone, the second conduction type collection are provided with the second interarea of the semiconductor substrate Electric area is provided with the first conduction type electric field cut-off region, the second conduction type collecting zone and current collection with the first conduction type drift interval Pole metal ohmic contact.

In both " first conduction type " and " the second conduction type ", for N-type insulated gate bipolar transistor device Part, the first conduction type refers to N-type, and the second conduction type is p-type；For p-type insulated-gate bipolar transistor device, first is conductive The type type signified with the second conduction type is opposite with N-type semiconductor device.

Advantage of the present utility model：

1st, during break-over of device, positioned at the first conduction type carrier accumulation layer of the second conductivity type body region bottom, due to The presence of Built-in potential can hinder circulation of the minority carrier to emitter stage, can form the accumulation of minority carrier, and conductance is adjusted Effect enhancing processed；Meanwhile, the accumulation of nonactive cellular B areas minority carrier further enhances the conductivity modulation effect of device, Therefore, it can significantly reduce IGBT device saturation voltage drop, reduce conduction loss.

2nd, when device is blocked, positioned at the presence of the second conduction type floating region, active cellular region A bodies area is shielded, Therefore, it is possible to when the first conduction type carrier accumulation layer concentration is adjusted, it is ensured that it is unaffected that device is pressure-resistant.

3rd, the presence in nonactive cellular B areas causes that effective gate electrode area reduces so that gate electrode and the electricity for launching interpolar Hold and gate electrode is substantially reduced with the electric capacity of inter-collector, reduce switching loss, improve the switching speed of device.

4th, nonactive cellular B areas, the second emitter metal and nonactive cellular conductive polycrystalline silicon Ohmic contact, and with two poles The cathode terminal connection of pipe, reduces the Voltage unbalance inside IGBT structure, it is thereby possible to reduce the electricity during devices switch Stream, oscillation.

Brief description of the drawings

Fig. 1 is the sectional view of the utility model active area.

Fig. 2 is top view of the present utility model.

Fig. 3 is the sectional view of A1-A1 ' in the utility model Fig. 2.

Fig. 4 is the sectional view of B1-B1 ' in the utility model Fig. 2.

Fig. 5 is the sectional view of B2-B2 ' in the utility model Fig. 2.

Fig. 6 is the sectional view of C1-C1 ' in the utility model Fig. 2.

Fig. 7 ~ Figure 19 is the utility model specific implementation process step sectional view, wherein

Fig. 7 is the sectional view of the utility model semiconductor substrate.

Fig. 8 obtains the sectional view after field oxide for the utility model.

Fig. 9 obtains the sectional view behind PXing Weiti areas for the utility model.

Figure 10 obtains the sectional view after hard mask layer for the utility model.

Figure 11 obtains the sectional view of p-type floating region for the utility model.

Figure 12 is the sectional view after the utility model filling conductive polycrystalline silicon.

Figure 13 obtains the sectional view after N-type carrier accumulation layer for the utility model.

Figure 14 obtains the sectional view behind p-type ohmic contact regions for the utility model.

Figure 15 obtains the sectional view after the second emitter metal for the utility model.

Figure 16 obtains the sectional view after the second insulating medium layer for the utility model.

Figure 17 obtains the sectional view after the first emitter metal for the utility model.

Figure 18 obtains the sectional view after p-type collecting zone for the utility model.

Figure 19 obtains the sectional view after collector electrode metal for the utility model.

Description of reference numerals：1-N types drift region, 2-P Xing Weiti areas, 3-P types floating region, 4-N type carriers accumulation layer, 5- PXing Ti areas, 6- insulation gate oxide, 7- activity cellulars conductive polycrystalline silicon, 7-1- diode N-types conductive region, 7-2- diodes P Type conductive region, 8-N+ launch sites, 9-P types activity ohmic contact regions, the insulating medium layers of 10- first, the emitter stages of 11- second gold Category, the insulating medium layers of 12- second, the emitter metals of 13- first, 14- field oxides, 15-P types transition region, 16- gate electrodes gold Category, 17- cut-off rings metal, 18-N+ electric fields cut-off region, 19-P+ collecting zones, 20- collector electrode metals, 21-N+ cut-off regions, 22-P types The nonactive cellular conductive polycrystalline silicon of field limiting ring, 23-, 24- dielectric isolation layers, 25- activity cellulars draw conductive polycrystalline silicon, 26-P types Nonactive ohmic contact regions, 27- hard mask layers, 100- active areas and 200- terminal protections area.

Specific embodiment

With reference to specific drawings and Examples, the utility model is described in further detail.

As shown in Figure 1, Figure 2, shown in Fig. 3, Fig. 4, Fig. 5, Fig. 6 and Figure 19：In order in the case where guarantee is pressure-resistant, with pole Low conduction voltage drop and the turn-off speed being exceedingly fast, and vibrated with relatively low Current Voltage, the reliability of work is greatly improved, with As a example by N-type insulated-gate bipolar transistor device, the utility model is specifically included：In the insulated-gate bipolar transistor device Top plan view on, including the active area 100 on semiconductor substrate and terminal protection area 200, the active area 100 In the center of semiconductor substrate, terminal protection area 200 is located at the outer ring of active area 100, and around the encirclement active area 100；On the section of the insulated-gate bipolar transistor device, semiconductor substrate have the first interarea and with the first interarea Corresponding second interarea, includes N-type drift region 1 between first interarea and the second interarea；

On the section of the insulated-gate bipolar transistor device, the cellular of the active area 100 uses groove structure, institute Stating active area cellular includes activity cellular A and nonactive cellular B；Trench wall and the bottom wall growth of active cellular A have absolutely Edge gate oxide 6, has in the active cellular groove of insulation gate oxide 6 in the growth and fills active cellular conductive polycrystalline silicon 7, the notch of active cellular A grooves is covered by the first insulating medium layer 10；PXing Ti areas 5 are provided between adjacent active cellular groove, and N-type carrier accumulation layer 4 is provided with the bottom in the PXing Ti areas 5；N+ launch sites 8 and p-type activity Europe are provided with P bodies area 5 Nurse contact zone 9, N+ launch sites 8 contact with the lateral wall of active cellular groove, and p-type activity ohmic contact regions 9 are located at N+ launch sites 8 Between, and contacted with the N+ launch sites 8 of both sides；The first hair above the interarea of N+ launch sites 8, p-type activity ohmic contact regions 9 and first The Ohmic contact of emitter-base bandgap grading metal 13；The Ohmic contact of gate electrode metal 16 above the interarea of active cellular conductive polycrystalline silicon 7 and first；

Trench wall and the bottom wall growth of nonactive cellular have insulation gate oxide 6, have insulation grid oxygen in the growth Change and nonactive cellular conductive polycrystalline silicon 23 is filled with the nonactive cellular groove of layer 6, the two of the nonactive cellular groove Side is equipped with PXing Weiti areas 2, and the nonactive ohmic contact regions 26 of p-type are provided with the PXing Weiti areas 2, and the p-type is nonactive Ohmic contact regions 26 contact with the lateral wall of nonactive cellular groove, the nonactive ohmic contact regions 26 of p-type and nonactive cellular Conductive polycrystalline silicon 23 with the first interarea on the Ohmic contact of the second emitter metal 11；Second emitter metal 11 and the first hair Emitter-base bandgap grading metal 13 is dielectrically separated from；

P-type floating region 3, active cellular are equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove The p-type floating region 3 of beneath trenches coats the bottom land of active cellular groove, and the P types floating region 3 of nonactive cellular beneath trenches is wrapped Cover the bottom land of nonactive cellular groove.

Specifically, semiconductor substrate can select silicon substrate, can have to active area 100 by terminal protection area 200 Effect protection, the specific matching relationship between active area 100 and terminal protection area 200 is known to those skilled in the art, herein not Repeat again.In the utility model embodiment, the groove of active cellular A is same technique manufactures layer with the groove of nonactive cellular B, The groove of i.e. active cellular A is identical with the gash depth of nonactive cellular B, the insulation gate oxide 6 in active cellular A grooves with Insulation gate oxide 6 in nonactive cellular B grooves is same process layer, and the active cellular in active cellular A grooves is conductive more Crystal silicon 7 is same process layer with the nonactive cellular conductive polycrystalline silicon 23 in nonactive cellular B grooves.

In Fig. 3, A1-A1 ', along section view is carried out perpendicular to the direction of groove, is parallel to groove and first along activity in Fig. 4 The direction of born of the same parents' conductive polycrystalline silicon 7 carries out section view, is parallel to groove, and along the side of nonactive cellular conductive polycrystalline silicon 7 in Fig. 5 To carrying out section view.

The notch of active cellular A grooves is covered by the first insulating medium layer 10 so that the activity unit in active cellular A grooves It is dielectrically separated between the emitter metal 13 of born of the same parents' conductive polycrystalline silicon 7 and first and the second emitter metal 12, the first emitter metal 13 are isolated by N+ launch sites 8 and p-type activity ohmic contact regions 9 with PXing Ti areas 5, N+ launch sites 8 and activity cellular A grooves Lateral wall overlying contact, N-type carrier accumulation layer 4 is located at the lower section in PXing Ti areas 5, and usually, N-type carrier accumulation layer 4 is located at The top of active cellular A groove bottom lands, N-type carrier accumulation layer 4 is not contacted with p-type floating region 3, and PXing Ti areas 5 are carried by N-type Sub- accumulation layer 4 is flowed to isolate with N-type drift region 1.In break-over of device, hole accumulates in the bottom of N-type carrier accumulation layer 4, with N Type carrier accumulation layer 4 forms Built-in potential；The accumulation in hole reduces the resistivity of N-type drift region 1, is led so as to effectively reduction Logical pressure drop.

Conductive polycrystalline silicon with the direct Ohmic contact of the second emitter metal 11 forms nonactive cellular conductive polycrystalline silicon 23, PXing Weiti areas 2 are respectively formed in the both sides of nonactive cellular B grooves, PXing Weiti areas 2 are in contact with p-type floating region 3.P-type non-live Property ohmic contact regions 26 and nonactive cellular B grooves lateral wall top be connected.In the insulated-gate bipolar transistor device On section, the p-type floating region 3 of active cellular A groove bottom lands is separated from each other, the p-type floating region 3 of nonactive cellular B groove bottom lands Can contact with each other, it is also possible to be separated from each other.

In the utility model embodiment, the first emitter metal 13 is by the second insulating medium layer 12 and the second emitter stage gold Category 11 is dielectrically separated from, and the emitter terminal of insulated-gate bipolar transistor device can be formed by the first emitter metal 13, is led to Crossing gate electrode metal 16 can form the gate electrode end of insulated-gate bipolar transistor device.

In the utility model embodiment, during break-over of device, the minority carrier of nonactive cellular B forms accumulation, further The conductivity modulation effect of device is strengthened, therefore, it can significantly reduce IGBT device saturation voltage drop, reduce conduction loss；Non-live Property cellular B presence cause that effective gate electrode area reduces so that the electric capacity of the grid of device and transmitting interpolar and device Grid is substantially reduced with the electric capacity of inter-collector, reduces switching loss, improves the switching speed of device.During specific implementation, The quantity of the quantity of active cellular A and nonactive cellular B in active area 100, can be according to insulated-gate bipolar transistor device Specifically used requirement be adjusted.

Further, first emitter metal 13 is connected with the second emitter metal 11 by diode, the first hair Emitter-base bandgap grading metal 13 is connected with the anode tap of diode, and the second emitter metal 11 is connected with the cathode terminal of diode.

In the utility model embodiment, the first emitter metal 13 is connected by diode with the second emitter metal 11 Afterwards, the imbalance of device internal voltage can be reduced, so as to reduce the electric current and voltage oscillation during devices switch.It is specific real Shi Shi, first emitter metal 13 is connected by external diode with the second emitter metal, or by being arranged at Integrated diode on one interarea is connected with the second emitter metal 11；Integrated diode is located at terminal protection area 200 On first interarea, integrated diode include diode P-type conduction region 7-2 and with the diode P-type conduction region 7-2 Adjacent diode N-type conductive region 7-1.

Further, the terminal protection area 200 includes transition region C, field limiting ring structure D and cut-off ring structure E, described Transition region C abuts active area 100, and cut-off ring structure E is located at the outer ring in terminal protection area 200, and field limiting ring structure D is located at transition region Between C and cut-off ring structure E.

In the utility model embodiment, transition region C, field limiting ring structure D and cut-off ring structure E in a ring, in transition Include the p-type transition region 15 being arranged in N-type drift region 1, the p-type transition region 15 and the outmost turns groove of active area 100 in area C Side wall and the p-type floating region 3 of the channel bottom contact.On corresponding first interareas of transition region C, it is provided with and is dielectrically separated from Layer 24 and it is arranged at the active cellular of the dielectric isolation layer 24 and draws conductive polycrystalline silicon 25, active cellular draws conductive polycrystalline Silicon 25 is isolated by dielectric isolation layer 24 with p-type transition region 15, and it is living with active area 100 that active cellular draws conductive polycrystalline silicon 25 Property cellular conductive polycrystalline silicon 7 link into an integrated entity, active cellular conductive polycrystalline silicon 7 is drawn by active cellular and led in active area 100 Electric polysilicon 25 and the Ohmic contact of gate electrode metal 16.Active cellular is drawn conductive polycrystalline silicon 25 and passes through the first insulating medium layer 10 It is dielectrically separated from the second emitter metal 11.Gate electrode metal 16 passes through the second insulating medium layer 12 and the second emitter metal 11 It is dielectrically separated from.

In field limiting ring structure D, including be arranged at the p-type field limiting ring 22 in N-type drift region 1, the p-type field limiting ring 22 with P-type transition region 15 is same technique manufactures layer.The first insulating medium layer is additionally provided with the first interarea of the top of p-type field limiting ring 22 The structure type that 10 etc., field limiting ring structure D can be commonly used using the art, specially known to those skilled in the art, Here is omitted.

In cut-off ring structure E, including N+ cut-off rings 21, the cut-off ring metal on the N+ cut-offs interarea of ring 21 and first 17 Ohmic contacts, N+ cut-offs ring 21 and N+ launch sites 8 are same technique manufactures layer, the concrete structure of prosperous cut-off ring structure E and Effect is same as the prior art, and specially known to the machine commandant personnel, here is omitted.

Further, P+ collecting zones 19, the P+ collecting zones 19 and N are provided with the second interarea of the semiconductor substrate N+ electric fields cut-off region 18, P+ collecting zones 19 and the Ohmic contact of collector electrode metal 20 are provided between type drift region 1.The utility model is implemented In example, the doping concentration of N+ electric fields cut-off region 18 more than N-type drift region 1 doping concentration, P+ collecting zones 19 can be it is continuous, Can also be that when P+ collecting zones 19 are in discontinuous form, collector electrode metal 20 connects for 18 ohm with N+ electric fields cut-off region in discontinuous form Touch, the collector terminal of device can be formed by collector electrode metal 20.

As shown in Fig. 7 ~ Figure 19, the above-mentioned insulated-gate bipolar transistor device with low conduction voltage drop can be under The manufacture method stated is prepared, and specifically, the manufacture method of the insulated-gate bipolar transistor device comprises the following steps：

A, the semiconductor substrates with two opposing main faces are provided, two opposing main faces include the first interarea and with first The second corresponding interarea of interarea, includes N-type drift region 1 between the first interarea and the second interarea；

As shown in fig. 7, the material of the semiconductor substrate includes silicon, certainly, semiconductor substrate can also use this technology Other conventional materials of field, will not enumerate herein.

B, the deposit field oxide 14 on the first interarea of above-mentioned semiconductor substrate, the covering semiconductor of the field oxide 14 First interarea of substrate；

As shown in figure 8, field oxide 14 is silicon dioxide layer, the specific embodiment that deposit obtains field oxide 14 is this Known to technical field personnel, here is omitted.

C, optionally shelter and etch above-mentioned field oxide 14, to form ion implanting window, and utilize the ion Injection window carries out the injection of p type impurity, and required main knot, field limiting ring structure D and P is formed in semiconductor substrate after pushing away trap Xing Weiti areas 2；

As shown in figure 9, ion implanting window insertion field oxide 14, N can be injected using ion implanting window by p type impurity In type drift region 1, the specific embodiment that P types impurity injects and push away trap is known to those skilled in the art, herein not Repeat again.The master becomes the PN junction formed by the N-type drift region 1 of p-type transition region 15 and the lower section of the p-type transition region 15, P Xing Weiti areas 2 are located in active area 100, and main knot and field limiting ring structure D are respectively positioned in terminal protection area 200.

D, the field oxide 14 removed on above-mentioned semiconductor substrate active area 100, and in the field oxide 14 needed for removal Afterwards, hard mask layer 27 is deposited on the first interarea, the hard mask layer 27 is covered on the first interarea of active area 100, and is covered Cover on first interarea and field oxide 14 in terminal protection area 200；

As shown in Figure 10, the field oxide 14 on active area 100, the oxidation of removal field are removed using modes such as photoresist maskings Known to those skilled in the art, here is omitted for the detailed process of layer 14.Hard mask layer 14 is LPTEOS, thermal oxide Silica adds chemical vapor deposition silica or thermal silicon dioxide plus silicon nitride.Due to the field oxide on active area 100 14 all removals, the field oxide 14 in terminal protection area 200 is retained, therefore, hard mask layer 27 has been directly overlayed First interarea of source region 100, and be covered in terminal protection area 200 field oxide 14 and part terminal protection area 200 One interarea.

E, optionally shelter and etch above-mentioned hard mask layer 27, to obtain required hard mask window, using described hard Mask window is performed etching to semiconductor substrate, to form multiple grooves in the N-type drift region 1 of semiconductor substrate；Formed The first interarea top implanting p-type impurity of the semiconductor substrate of groove, after pushing away trap, the p-type floating region 3 needed for being formed, the p-type Floating region 3 coats the bottom land of groove；

As shown in figure 11, the technological means commonly used using the art, can etch hard mask layer 27 and obtain hard mask windows Mouthful, the hard mask window insertion hard mask layer 27, using hard mask window, anisotropic etching is carried out to N-type drift region 1, Can obtain some grooves, the groove is vertical to extension in N-type drift region 1 from the first interarea.After formation of the groove, by note Enter p type impurity, p-type floating region 3 can be obtained, the specific embodiment that p type impurity injects and push away trap is those skilled in the art Known, here is omitted.

F, the hard mask layer 27 removed on the above-mentioned interarea of semiconductor substrate first, and after hard mask layer 27 is removed, upper Inwall and bottom wall the growth insulation gate oxide 6 of groove are stated, and has filling in the groove of insulation gate oxide 6 conductive many in growth Crystal silicon；

Specifically, the technological means commonly used using the art, can realize the removal of hard mask layer 27, and insulate gate oxidation Layer 6 can be obtained by thermal oxide growth, after growth has insulation gate oxide 6, conductive polycrystalline be deposited by the first interarea Silicon, can realize being filled in conductive polycrystalline silicon in groove., it is necessary to respective regions on the first interarea are led after in the filling groove Electric etching polysilicon removal, to carry out follow-up technique.The technological means commonly used using the art is realized corresponding conductive The etching removal of polysilicon, specially known to those skilled in the art, here is omitted.

G, on the first interarea of above-mentioned semiconductor substrate the first photoresist layer is coated, institute is being carried out to the first photoresist layer After the etching for needing, N-type impurity is injected above the first interarea, with the N needed for being formed in the N-type drift region 1 of semiconductor substrate Type carrier accumulation layer 4；

Specifically, coat the first photoresist layer on the first interarea, and after being performed etching to the first photoresist layer, be easy into The injection of row N-type impurity, with the N-type carrier accumulation layer 4 needed for being formed in active area 100, as shown in figure 12, concrete technology Process is that here is omitted known to those skilled in the art.

Additionally, when the first emitter metal 13 is connected with the second emitter metal 11 using integrated diode, in shape During into N-type carrier accumulation layer 4, moreover it is possible to diode N-type conductive region 7-1, diode are formed on first interarea of transition region C N-type conductive region 7-1 can carry out N-type impurity injection and obtain by the conductive polycrystalline silicon on the interareas of transition region C first.

H, above-mentioned first photoresist layer of removal, and the second photoresist layer is coated on the first interarea of semiconductor substrate, After etching needed for being carried out to the second photoresist layer, the implanting p-type impurity above the first interarea floats with the N-type of semiconductor substrate Move and PXing Ti areas 5 are formed in area 1, the PXing Ti areas 5 are located at the surface of N-type carrier accumulation layer 4, NXing Ti areas 5 and N-type current-carrying Sub- accumulation layer is in contact；

As shown in figure 13, the technological means commonly used using the art, can remove the first photoresist layer, to the second light After photoresist layer etching, p type impurity can be convenient for, to obtain PXing Ti areas 5.Additionally, can also on first interarea of transition region C Diode P-type conduction region 7-2 is formed, diode P-type conduction region 7-2 is connected with diode N-type conductive region 71-, with shape Into the structure of diode.

I, above-mentioned second photoresist layer of removal, and the 3rd photoresist layer is coated on the first interarea of semiconductor substrate, After etching needed for being carried out to the 3rd photoresist layer, N-type impurity is injected above the first interarea, formed with semiconductor substrate N+ launch sites 8 and N+ cut-off regions 21；

Specifically, the technological means commonly used using the art, removes the second photoresist layer；In coating and photoetching the 3rd After photoresist layer, N-type impurity injection is carried out, obtain N+ launch sites 8 and N+ cut-off regions 21, N+ launch sites 8 are located at active area 100 It is interior.After N+ launch sites 8 and N+ cut-off regions 21 is obtained, the 3rd photoresist layer is removed.

K, the first insulating medium layer 10 is deposited on the first interarea of above-mentioned semiconductor substrate, and the described first insulation is situated between Matter layer 10 is performed etching, and the top of the first insulating medium layer 10 after etching carries out p type impurity injection, with semiconductor substrate Active area 100 in formed needed for p-type ohmic contact regions；

As shown in figure 14, after being performed etching to the first insulating medium layer 10, can cause in active area 100, the first insulation The notch of the covering part groove of dielectric layer 10, additionally, using the first insulating medium layer 10 after etching, can realize that p type impurity is noted Enter, obtain p-type ohmic contact regions, specifically, the p-type ohmic contact regions include that p-type activity ohmic contact regions 9 and p-type are non- Active ohmic contact regions 26, p-type active contact area 9 contacts with N+ launch sites 8, and the first of the top of p-type activity ohmic contact regions 9 is exhausted Edge dielectric layer 10 is etched.The both sides of the nonactive ohmic contact regions 26 of p-type are without N+ launch sites 8.

L, the second emitter metal 11 is set on the first interarea of above-mentioned semiconductor substrate, the second emitter metal 11 with Conductive polycrystalline silicon Ohmic contact in corresponding p-type ohmic contact regions and respective groove, to form required nonactive cellular B；

As shown in figure 15, because when being etched to the first insulating medium layer 10, the notch of part of trench is in open state, When the second emitter metal 11 is deposited, the second emitter metal 11 and the nonactive ohmic contact regions 26 of p-type and underface Conductive polycrystalline silicon Ohmic contact, after forming nonactive cellular B, the conductive polycrystalline silicon turns into nonactive cellular conductive polycrystalline silicon 23.When the second emitter metal 11 is obtained, the second emitter metal 11 can with diode N-type conductive region 7-1 ohm connect Touch.

N, the second insulating medium layer 12 is deposited on the first interarea of above-mentioned semiconductor substrate, and the described second insulation is situated between The second required insulating medium layer contact hole is formed after the etching of matter layer 12；

As shown in figure 16, after the second insulating medium layer 12 of deposit, the second insulating medium layer is formed in desired position region Contact hole, the position of the second insulating medium layer contact hole can be selected as needed, specially those skilled in the art institute Know, here is omitted.

O, on the first interarea of above-mentioned semiconductor substrate, deposited metal, to the metal level for obtaining etch after, formed Required the first emitter metal 13, gate electrode metal 16 and cut-off ring metal 17, the first emitter metal 13 are launched with N+ Area 8 and corresponding p-type ohmic contact regions Ohmic contact, are removed and second with being formed in required active cellular A, N-type drift region 1 The conductive polycrystalline silicon of the Ohmic contact of emitter metal 11 with the Ohmic contact of gate electrode metal 16, cut-off ring metal 17 ends with N+ The Ohmic contact of area 21；

As shown in figure 17, in deposited metal, and after etching, using the second above-mentioned insulating medium layer contact hole, can make The first emitter metal 13 is obtained with N+ launch sites 8 and p-type activity ohmic contact regions 9 Ohmic contact, cut-off ring metal 17 and N+ The Ohmic contact of cut-off region 21.In active area 100, the conductive polycrystalline silicon with the Ohmic contact of the second emitter metal 11 forms nonactive Cellular conductive polycrystalline silicon 23, the conductive polycrystalline silicon in remaining groove forms active cellular conductive polycrystalline silicon 7, and active cellular is conductive more Crystal silicon 7 is parallel with one another, and draws conductive polycrystalline silicon 25 and the Ohmic contact of gate electrode metal 16 by the active cellular in transition region, It is same process layer that active cellular draws conductive polycrystalline silicon 25 with active cellular conductive polycrystalline silicon 7, i.e. step f is obtained, specific system Standby process is that here is omitted known to those skilled in the art.

P, N+ electric fields cut-off region 18 and P+ collecting zones 19, N+ needed for the second interarea of above-mentioned semiconductor substrate is formed Electric field cut-off region 18 is located between N-type drift region 1 and P+ collecting zones 19, and P+ collecting zones 19 are abutted with N+ electric fields cut-off region 18；

As shown in figure 18, the doping concentration of N+ electric fields cut-off region 18 usually, is gone back more than the doping concentration of N-type drift region 1 Second interarea of semiconductor substrate can be carried out it is thinning, specific thinning technical process known to those skilled in the art, Here is omitted.

Q, required collector electrode metal 20 is deposited on above-mentioned P+ collecting zones 19, the collector electrode metal 20 and P+ collecting zones Ohmic contact.

As shown in figure 19, the collector terminal of device can be formed by collector electrode metal 20.

During the utility model break-over of device, positioned at the N-type carrier accumulation layer 4 of the bottom of PXing Ti areas 5, due to Built-in potential Presence can hinder circulation of the minority carrier to emitter stage, can form the accumulation of minority carrier, conductivity modulation effect increases By force；Meanwhile, the accumulation of nonactive cellular B areas minority carrier further enhances the conductivity modulation effect of device, therefore, can To significantly reduce IGBT device saturation voltage drop, conduction loss is reduced；When device is blocked, positioned at the presence of p-type floating region 3, to work Property cellular region A bodies area shielded, therefore, it is possible to adjust N-type carrier 4 concentration of accumulation layer when, it is ensured that device is pressure-resistant not to be received Influence.

The presence in nonactive cellular B areas causes that effective gate electrode area reduces so that the electric capacity of gate electrode and transmitting interpolar, And gate electrode is substantially reduced with the electric capacity of inter-collector, reduces switching loss, improves the switching speed of device；It is nonactive Cellular B areas, the second emitter metal 11 and the nonactive Ohmic contact of cellular conductive polycrystalline silicon 23, and connect with the cathode terminal of diode Connect, reduce the Voltage unbalance inside IGBT structure, it is thereby possible to reduce electric current, oscillation during devices switch.

Claims (5)

1. a kind of insulated-gate bipolar transistor device with low conduction voltage drop, in the insulated gate bipolar transistor device In the top plan view of part, including the active area on semiconductor substrate and terminal protection area, the active area is located at and partly leads The center of structure base board, terminal protection area is located at the outer ring of active area, and around the encirclement active area；It is double in the insulated gate On the section of bipolar transistor device, semiconductor substrate has the first interarea and the second interarea corresponding with the first interarea, institute Stating includes the first conduction type drift region between the first interarea and the second interarea；It is characterized in that：

On the section of the insulated-gate bipolar transistor device, the cellular of the active area uses groove structure, described to have Source region cellular includes active cellular and nonactive cellular；Trench wall and the bottom wall growth of active cellular have insulation gate oxidation Layer, has in the active cellular groove of insulation gate oxide in the growth and fills active cellular conductive polycrystalline silicon, active cellular The notch of groove is covered by the first insulating medium layer；The second conductivity type body region is provided between adjacent active cellular groove, and in institute The bottom for stating the second conductivity type body region is provided with the first conduction type carrier accumulation layer；It is provided with the second conductivity type body region First conduction type launch site and the second conduction type activity ohmic contact regions, the first conduction type launch site and active cellular The lateral wall contact of groove, the second conduction type activity ohmic contact regions are located at the first conduction type and launch interval, and and both sides The first conduction type launch site contact；First conduction type launch site, the second conduction type activity ohmic contact regions and first The first emitter metal Ohmic contact above interarea；Gate electrode metal above active cellular conductive polycrystalline silicon and the first interarea Ohmic contact；

Trench wall and the bottom wall growth of nonactive cellular have insulation gate oxide, have insulation gate oxide in the growth Nonactive cellular conductive polycrystalline silicon is filled with nonactive cellular groove, the is equipped with the both sides of the nonactive cellular groove Two conduction type Wei Ti areas, the nonactive ohmic contact regions of the second conduction type are provided with the second conduction type Wei Ti areas, The nonactive ohmic contact regions of second conduction type contact with the lateral wall of nonactive cellular groove, the second conduction type non-live Property ohmic contact regions and nonactive cellular conductive polycrystalline silicon with the first interarea on the second emitter metal Ohmic contact；The Two emitter metals are dielectrically separated from the first emitter metal；

The second conduction type floating region is equipped with the bottom land of active cellular groove and the bottom land of nonactive cellular groove, activity The bottom land of the active cellular groove of the second conduction type floating region cladding of cellular beneath trenches, the of nonactive cellular beneath trenches Two conduction type floating regions coat the bottom land of nonactive cellular groove.

2. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, it is characterized in that：Institute State the first emitter metal to be connected by diode with the second emitter metal, the anode tap of the first emitter metal and diode Connection, the second emitter metal is connected with the cathode terminal of diode.

3. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 2, it is characterized in that：Institute The first emitter metal is stated to be connected with the second emitter metal by external diode, or by being arranged on the first interarea Integrated diode is connected with the second emitter metal；Integrated diode is located on first interarea in terminal protection area, integrated Formula diode includes diode P-type conduction region and the diode N-type conduction region with the diode P-type conduction area adjacency Domain.

4. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, it is characterized in that：Institute Stating terminal protection area includes transition region, field limiting ring structure and cut-off ring structure, and the transition region abuts active area, ends ring knot Structure is located at the outer ring in terminal protection area, and field limiting ring structure is located between transition region and cut-off ring structure.

5. the insulated-gate bipolar transistor device with low conduction voltage drop according to claim 1, it is characterized in that： Second interarea of the semiconductor substrate is provided with the second conduction type collecting zone, the second conduction type collecting zone and first Conduction type drift interval is provided with the first conduction type electric field cut-off region, the second conduction type collecting zone and collector electrode metal ohm Contact.