CN108511512A - A kind of power semiconductor and preparation method thereof with undaform field limiting ring structure - Google Patents
A kind of power semiconductor and preparation method thereof with undaform field limiting ring structure Download PDFInfo
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- CN108511512A CN108511512A CN201810115022.0A CN201810115022A CN108511512A CN 108511512 A CN108511512 A CN 108511512A CN 201810115022 A CN201810115022 A CN 201810115022A CN 108511512 A CN108511512 A CN 108511512A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000002360 preparation method Methods 0.000 title claims description 10
- 230000001413 cellular effect Effects 0.000 claims abstract description 18
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 230000007704 transition Effects 0.000 claims abstract description 14
- 238000000407 epitaxy Methods 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 21
- 239000007924 injection Substances 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 18
- 239000012535 impurity Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000005224 laser annealing Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims 2
- 239000013049 sediment Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000001629 suppression Effects 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005339 levitation Methods 0.000 description 1
- 230000003137 locomotive effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
A kind of power semiconductor with undaform field limiting ring structure, including：P type substrate (1), N-type buffer layer (2) is equipped with above P type substrate (1), N-type buffer layer (2) is equipped with N-type epitaxy layer (3) and N-type epitaxy layer (3) is divided into cellular region, transition region and termination environment, gate trench (4 1) is equipped in cellular region, (4 2), it is equipped with gate trench (4 3) in transition region, (4 4), (4 5), in gate trench (4 1), it is equipped with the areas PXing Ti (6) between (4 2), heavily doped N-type emitter (7) is equipped in the areas PXing Ti (6), it is characterized in that, undaform is equipped in termination environment, overlapping shape ion diffusion region (10), ion implanted region (10 1) is equipped in undaform ion diffusion region (10), (10 2), (10 3).Device architecture of the present invention can suppression device shutdown the moment caused by electric field spike, to inhibit dynamic avalanche.
Description
Technical field
The invention mainly relates to power semiconductor device technology fields, and in particular to one kind carrying undaform field limiting ring structure
Power semiconductor and preparation method thereof, power semiconductor be mainly used for heavy-duty motor transmission, locomotive traction and
The fields such as high voltage power transmission.
Background technology
Power semiconductor is high with blocking voltage, conduction voltage drop is low, driving circuit is simple, the good and safe work of controllability
Make the advantages that area is big.Power semiconductor is widely used in various power converter systems, such as transmission system (high voltage direct current
Transmission and wireless power transmission), transportation system's (railway, magnetic-levitation train and aerospace) and industrial drives system (variable speed drives)
Deng.With the rapid development of industrial variable speed drives technology, more and more power semiconductors are by using motor-drive circuit
In.These power semiconductors needs realize HF switch under conditions of high pressure, high current, are often turned off in high current
When, i.e., when power semiconductor is converted from forward conduction state to reverse bias condition, dynamic avalanche is induced, device is caused to lose
Effect, influences the robustness of device.Therefore, the dynamic of device is improved on the basis of the voltage endurance capability of retainer member, low conduction voltage drop
State snowslide robustness is the important development direction of power semiconductor, is had great importance to the development of power device.
Invention content
The present invention in view of the above-mentioned problems, propose a kind of power semiconductor with undaform field limiting ring structure and its
Preparation method.The structure is carved when off by applying undaform field limiting ring reduction power semiconductor device structure due to hole electricity
In adfluxion and drastically raised surface field, to effectively inhibit dynamic avalanche phenomenon.
The present invention provides following structure technology scheme：
A kind of power semiconductor and preparation method thereof with undaform field limiting ring structure, including：P type substrate,
The P type substrate bottom is equipped with collector of the anode metal layer as device, and N-type buffer layer, N are equipped with above P type substrate
Type buffer layer is equipped with N-type epitaxy layer and the N-type epitaxy layer is divided into cellular region, transition region and termination environment, in N-type extension
Layer is equipped with field oxide, is set in cellular region there are two cellular region gate trench, sets that there are three transition region grids in transition region
Groove is equipped with the areas PXing Ti between two cellular region gate trench, heavily doped N-type emitter, cellular region is equipped in the areas PXing Ti
Gate trench and transition region gate trench sidewalls and bottom are equipped with gate oxide, are filled with as device gate inside gate oxide
The polysilicon of pole, which is characterized in that undaform, overlapping shape ion diffusion region are equipped in termination environment, in undaform ion diffusion region
Ion implanted region there are three inside setting.Preparation method is as follows：
The first step：Epitaxial growth heavily doped N-type buffer layer and shallow doped N-type epitaxial layer first, then grow field oxide；
Second step：Etching injection window, by holocrystalline circle injection form implanting p-type impurity, formed it is spaced from
Sub- injection region is generating undaform ion diffusion region by 1175 DEG C of annealing diffusions, and the wherein Implantation Energy of ion implanted region is situated between
Between 10~100keV, implantation dosage is between 1e12~1el4cm~2；
Third walks：Etching grid groove, grows grid oxic horizon, and subsequent depositing polysilicon forms grid；
4th step：Etches polycrystalline silicon, autoregistration holocrystalline, which justifies implanting p-type impurity and anneals, forms the areas PXing Ti, wherein p-type body
The Implantation Energy in area is between 10keV~120keV, and implantation dosage is between 1e11~4e14cm-2；
5th step：Etching injection window injects N-type impurity by the form of holocrystalline circle injection, and anneals and form heavy doping N
Type emitter region, wherein the Implantation Energy of N-type emitter region between 10keV~80keV, implantation dosage between 1e13~
Between 1e17cm-2；
6th step：It etches field oxide and forms contact hole, then metal layer deposit, photoetching, etching, form metal transmitting
Pole；
7th step：Pass through the form implanting p-type impurity of holocrystalline circle injection, laser annealing most end form in N-type buffer layer bottom
At P type substrate and as the collector of device.
Compared with prior art, the invention has the advantages that：
1, the present invention is effectively reduced by applying undaform field limiting ring structure, the structure in power semiconductor
Power semiconductor turns off the surface field at moment, and then inhibits dynamic avalanche.Reason is power semiconductor just
To turn-on instant, electronics and hole are involved in conduction, therefore be stored with largely can be with free-moving electricity for cellular region and termination environment
Big injection state is presented in son and hole.When power semiconductor turns off, raceway groove is closed, and electronic carrier rapidly disappears, work(
Remaining a large amount of holes in rate semiconductor devices epitaxial layer.In order to bear reverse biased, need that hole in the epitaxial layer will be stored
Carrier extracts away, and forms depletion layer.Figure 10 and Figure 11 is prototype structure and structure of the invention respectively in power semiconductor
Device turns off the hole mobile route at moment, it can be found that a large amount of holoe carriers flow through the areas PXing Ti of traditional structure from figure
With the undaform field limiting ring of the present invention proposed.When holoe carrier density can mutually compare with N-type epitaxy layer doping concentration
When quasi-, the electric-force gradient at the areas traditional structure PXing Ti will increased dramatically, and peak electric field drastically increases, and then cause dynamic and avenge
Collapsing causes device to burn, and the areas Zhong JiangPXing Ti of the present invention replace with undaform field limiting ring, which is spread by ion
Area is formed with ion implanted region, and forms the lateral concentration distribution of P+P-P+P-P+P-, when undaform field is flowed through in a large amount of hole
It can mutually be exhausted by the regions P- transoid, and with the regions P+ when limiting ring, wherein the regions P- are the lower buffering area of concentration, can allow consumption
Layer broadening is wider to the greatest extent, and can mutual assisted depletion, peak electric field is by original electricity under identical collector voltage
Field spike becomes three relatively low electric field spikes, i.e., leftmost three electric field spikes, as shown in figure 12, surface peak electricity
Field is reduced to the 150000V/cm of structure of the invention by the 300000V/cm of traditional structure, successfully inhibits dynamic avalanche.
2, the undaform field limiting ring structure designed by the present invention joins other every static dynamics of power semiconductor
Number does not have an impact.The advantages of in order to verify structure of the invention, the present invention pass through semiconductor devices simulation software Sentaurus
TCAD has carried out contrast simulation to structure, as shown in Figure 13, Figure 14.Figure 13 is that traditional structure is carried with one kind proposed by the present invention
The power semiconductor conduction voltage drop comparison diagram of undaform field limiting ring structure, it can be seen from the figure that under same current density
Structure of the invention shows identical conduction voltage drop with traditional structure.Figure 14 is that traditional structure is carried with one kind proposed by the present invention
The pressure-resistant comparison diagram of the power semiconductor of undaform field limiting ring structure, it can be seen from the figure that structure of the invention and tradition
Structure shows identical voltage endurance capability.
3, device structure design technique of the present invention remains conventional groove MOS type field-effect transistor
The design technology of structure, process compatible, feasibility are high.
Description of the drawings
Fig. 1 show traditional structure plane structure chart.
Fig. 2 show a kind of power semiconductor figure with Wave-shaped structural proposed by the present invention.
Fig. 3 show the processing step first step of structure of the invention, i.e. epitaxial growth heavily doped N-type buffer layer and shallow doping
N-type epitaxy layer, then annealing grow field oxide.
Fig. 4 show the processing step second step of structure of the invention, i.e. photoetching, injection boron ion forms ion implanted region,
And it anneals and forms ion diffusion region.
Fig. 5 show the processing step third step of structure of the invention, that is, deposits field oxide, photoetching, etching groove, deposit
Gate oxide, depositing polysilicon in groove.
Fig. 6 show the 4th step of processing step of structure of the invention, that is, returns and carve polysilicon and field oxide, photoetching, general note
Boron ion and anneal form the areas PXing Ti.
Fig. 7 show the 5th step of processing step of structure of the invention, i.e. photoetching, injection arsenic ion, and annealing is formed heavily doped
Miscellaneous N-type emitter region.
Fig. 8 show the 6th step of processing step of structure of the invention, that is, etches field oxide and form contact hole, then metal
Layer deposit, photoetching, etching, form metal emitting.
Fig. 9 show the 7th step of processing step of structure of the invention, i.e. device backside particulate implanting p-type impurity, forms p-type
Substrate, the device back side deposit collector electrode metal.
Figure 10 show traditional structure hole current path profile.
Figure 11 show a kind of power semiconductor hole electricity with undaform field limiting ring structure proposed by the present invention
Flow path figure.
Figure 12 show a kind of power semiconductor with undaform field limiting ring structure proposed by the present invention and tradition
Body structure surface electric field comparison diagram.
Figure 13 show a kind of power semiconductor with undaform field limiting ring structure proposed by the present invention and tradition
Structure conduction voltage drop comparison diagram.
Figure 14 show a kind of power semiconductor with undaform field limiting ring structure proposed by the present invention and tradition
Structure breakdown voltage (BV) comparison diagram.
Specific implementation mode
It elaborates with reference to the accompanying drawings of the specification to the present invention.
With reference to Fig. 2, elaborate to the present invention, a kind of power semiconductor with undaform field limiting ring structure and
Preparation method, including：P type substrate 1 is equipped with collector of the anode metal layer as device in 1 bottom of P type substrate,
N-type buffer layer 2 is equipped with above P type substrate 1, N-type buffer layer 2 is equipped with N-type epitaxy layer 3 and the N-type epitaxy layer 3 is divided
For cellular region, transition region and termination environment, it is equipped with field oxide 9 in N-type epitaxy layer 3, sets that there are two cellular regions in cellular region
Gate trench 4-1,4-2 are set there are three transition region gate trench 4-3,4-4,4-5 in transition region, in two cellular region grid ditches
It is equipped with the areas PXing Ti 6 between slot 4-1,4-2, heavily doped N-type emitter 7, cellular region gate trench and transition are equipped in the areas PXing Ti 6
Area's gate trench sidewalls and bottom are equipped with gate oxide 5, and the polysilicon 8 as device grids is filled with inside gate oxide 5,
It is characterized in that, being equipped with undaform, overlapping shape ion diffusion region 10 in termination environment, three are equipped in undaform ion diffusion region 10
A ion implanted region 10-1,10-2,10-3.
The power semiconductor for carrying undaform field limiting ring structure as described above is prepared, is as follows：
The first step：Epitaxial growth heavily doped N-type buffer layer 2 and shallow doped N-type epitaxial layer 3 first, then grow field oxidation
Layer 9；
Second step：Etching injection window, by holocrystalline circle injection form implanting p-type impurity, formed it is spaced from
Sub- injection region 10-1,10-2,10-3 are generating undaform ion diffusion region 10, intermediate ion note by 1175 DEG C of annealing diffusions
Enter the Implantation Energy of area 10-1,10-2,10-3 between 10~100keV, implantation dosage between 1e12~1e14cm-2 it
Between；
Third walks：Etching grid groove 4-1,4-2,4-3,4-4,4-5 grow grid oxic horizon 5, subsequent depositing polysilicon
8 form grid；
4th step：Etches polycrystalline silicon 8, autoregistration holocrystalline, which justifies implanting p-type impurity and anneals, forms the areas PXing Ti 6, wherein p-type
The Implantation Energy in body area 6 is between 10keV~120keV, and implantation dosage is between 1e11~4e14cm-2；
5th step：Etching injection window injects N-type impurity by the form of holocrystalline circle injection, and anneals and form heavy doping N
Type emitter region 7, wherein the Implantation Energy of N-type emitter region 7 between 10keV~80keV, implantation dosage between 1e13~
Between 1e17cm-2；
6th step：It etches field oxide 9 and forms contact hole, then metal layer deposit, photoetching, etching, form metal transmitting
Pole；
7th step：Pass through the form implanting p-type impurity of holocrystalline circle injection, laser annealing most end form in 2 bottom of N-type buffer layer
At P type substrate 1 and as the collector of device.
Claims (4)
1. a kind of power semiconductor and preparation method thereof with undaform field limiting ring structure, including：P type substrate (1),
Described P type substrate (1) bottom is equipped with collector of the anode metal layer as device, slow equipped with N-type above P type substrate (1)
Layer (2) is rushed, N-type buffer layer (2) is equipped with N-type epitaxy layer (3) and the N-type epitaxy layer (3) is divided into cellular region, transition region
And termination environment, it is equipped with field oxide (9) in N-type epitaxy layer (3), is set in cellular region there are two cellular region gate trench (4-
1), (4-2) is set there are three transition region gate trench (4-3), (4-4), (4-5) in transition region, in two cellular region gate trench
The areas PXing Ti (6) are equipped between (4-1), (4-2), heavily doped N-type emitter (7), cellular region grid ditch are equipped in the areas PXing Ti (6)
Slot and transition region gate trench sidewalls and bottom are equipped with gate oxide (5), are filled with as device gate inside gate oxide (5)
The polysilicon (8) of pole, which is characterized in that undaform, overlapping shape ion diffusion region (10) are equipped in termination environment, in undaform ion
Ion implanted region (10-1), (10-2), (10-3) there are three being set in diffusion region (10).
2. a kind of power semiconductor with undaform field limiting ring structure according to claim 1, which is characterized in that
Three ion implanted regions (10-1), (10-2), (10-3) doping concentration are higher than ion diffusion region (10), and ion implanted region (10-
1), (10-2), (10-3) are spaced, and ion implanted region number can be determined according to the reliability requirement of practical devices.
3. a kind of preparation method of power semiconductor with undaform field limiting ring structure according to claim 1,
Ion implanted region (10-1), (10-2), (10-3) boron impurity concentration range between 2.3e17~3.7e17cm-2Between, ion
The concentration range of diffusion region (10) boron impurity is injected between 3e16~9e16cm-2Between.
4. the power semiconductor and preparation method thereof of undaform field limiting ring structure is carried described in a kind of claim 1, it is special
Sign is, comprises the steps of：
The first step：Epitaxial growth heavily doped N-type buffer layer (2) and shallow doped N-type epitaxial layer (3) first, then grow field oxidation
Layer (9)；
Second step：Etching injection window forms spaced ion note by the form implanting p-type impurity of holocrystalline circle injection
Enter area (10-1), (10-2), (10-3), undaform ion diffusion region (10) are being generated by 1175 DEG C of annealing diffusions, wherein from
Sub- injection region (10-1), (10-2), (10-3) Implantation Energy between 10~100keV, implantation dosage between 1e12~
1e14cm-2Between；
Third walks：Etching grid groove (4-1), (4-2), (4-3), (4-4), (4-5), growth grid oxic horizon (5) then form sediment
Product polysilicon (8) forms grid；
4th step：Etches polycrystalline silicon (8), autoregistration holocrystalline, which justifies implanting p-type impurity and anneals, forms the areas PXing Ti (6), wherein p-type
The Implantation Energy in body area (6) is between 10keV~120keV, and implantation dosage is between 1e11~4e14cm-2Between；
5th step：Etching injection window injects N-type impurity by the form of holocrystalline circle injection, and anneals and form heavily doped N-type hair
Penetrate area (7), wherein the Implantation Energy of N-type emitter region (7) between 10keV~80keV, implantation dosage between 1e13~
1e17cm-2Between；
6th step：It etches field oxide (9) and forms contact hole, then metal layer deposit, photoetching, etching, form metal emitting；
7th step：In N-type buffer layer (2) bottom by the form implanting p-type impurity of holocrystalline circle injection, laser annealing ultimately forms
P type substrate (1) and the collector as device.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109473471A (en) * | 2018-12-26 | 2019-03-15 | 上海昱率科技有限公司 | Power device and its manufacturing method |
| CN113257895A (en) * | 2021-07-14 | 2021-08-13 | 江苏应能微电子有限公司 | Semiconductor field effect transistor device |
| CN113314613A (en) * | 2021-05-31 | 2021-08-27 | 电子科技大学 | Silicon carbide MOSFET device with avalanche charge transition buffer layer and preparation method |
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