CN109473471A - Power device and its manufacturing method - Google Patents
Power device and its manufacturing method Download PDFInfo
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- CN109473471A CN109473471A CN201811606653.9A CN201811606653A CN109473471A CN 109473471 A CN109473471 A CN 109473471A CN 201811606653 A CN201811606653 A CN 201811606653A CN 109473471 A CN109473471 A CN 109473471A
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 230000001413 cellular effect Effects 0.000 claims abstract description 31
- 125000006850 spacer group Chemical group 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000009826 distribution Methods 0.000 claims abstract description 7
- 238000002347 injection Methods 0.000 claims description 24
- 239000007924 injection Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000002513 implantation Methods 0.000 description 12
- 230000007704 transition Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
A kind of power device, comprising: substrate；The epitaxial layer of first conduction type, is set to the substrate, and the epitaxial layer includes cellular region and termination environment；First body area of multiple second conduction types, is set in the cellular region of the epitaxial layer；Second body area of multiple second conduction types, is set in the termination environment of the epitaxial layer；Wherein, multiple spacer regions between the multiple second body area are the second conduction type, and the second body area of the multiple second conduction type and the spacer region of multiple second conduction types constitute the adjustable whole pressure ring of doping concentration distribution.
Description
Technical field
The present invention relates to semiconductor fields, and in particular, to a kind of power device and its manufacturing method.
Background technique
The cellular region (active area) of power semiconductor is made of the cellular of multiple repeated arrangements, in the shape exhausted
Under state, it is equal everywhere that the electric field of cellular region is distributed in Withstand voltage layer, therefore will not occur to concentrate because of electric field in cellular region and lead
The breakdown of cause.But the boundary in cellular region, device would generally be influenced by knot curvature effect and cause electric field attached in knot
Nearly aggregation, punctures device easily, so needing special terminal structure to improve knot curvature effect to device pressure resistance
It influences.
Currently, the terminal technology of many of traditional high voltage power device improves the pressure resistance of device terminal: for example, field
Limit ring, field plate techniques, JTE (junction terminal extension) etc..But traditional terminal structure still remains height
Pressure resistance and pressure-resistant stability problem.
Summary of the invention
In view of this, the purpose of the disclosure be at least partly to provide it is a kind of with the power device for improving performance and its
Manufacturing method and electronic equipment including this power device.
According to one aspect of the disclosure, present disclose provides a kind of power devices, comprising: substrate；First conduction type
Epitaxial layer, be set to the substrate, the epitaxial layer includes cellular region and termination environment；The of multiple second conduction types
Integrated area is set in the cellular region of the epitaxial layer；Second body area of multiple second conduction types, is set to the epitaxial layer
Termination environment in；Wherein, multiple spacer regions between the multiple second body area are the second conduction type, and the multiple second leads
Second body area of electric type and the spacer region of multiple second conduction types constitute the adjustable whole pressure ring of doping concentration distribution.
Wherein, the spacing between the injection window in the second adjacent body area is less than the junction depth in second body area.
Wherein, the spacing between the injection window in the second adjacent body area is equal.
Wherein, the spacing between the injection window in the second adjacent body area is variation.
Wherein, the doping concentration in second body area is higher than the doping concentration of the spacer region.
Wherein, the doping concentration in second body area is lower than the doping concentration in first body area.
Wherein, the junction depth in second body area is greater than the junction depth in first body area.
Wherein, the source region for further including the first conduction type being formed in first body area and formation are in the substrate
The first conduction type drain region.
According to another aspect of the disclosure, present disclose provides a kind of methods for manufacturing power device, wherein includes:
It is epitaxially grown on the substrate epitaxial layer, the epitaxial layer includes cellular region and termination environment；Ion implanting is carried out above epitaxial layer
To form multiple second bodies area；Trap is picked to form whole pressure ring to multiple second bodies area；Field oxidation is grown on epitaxial layer
Then layer is masked etching to remove the field oxide above cellular region；It carries out ion implanting and to pick trap multiple to be formed
First body area.
Wherein, the method also includes: gate oxide is grown above the cellular region of epitaxial layer, then deposit and etch it is more
Crystal silicon is to form polysilicon gate；Source region is formed in first body area, by each first body area and source region metal
Layer connection, to form source electrode；The substrate bottom is carried out back thinning and metal layer on back makes, to form drain electrode.
Wherein, carry out ion implanting to form multiple second body areas when, by the injection window in the second adjacent body area it
Between spacing be set smaller than the junction depth in second body area.
According to another aspect of the disclosure, present disclose provides a kind of electronic equipment, including at least partly by as above
The integrated circuit that power device described in any one of described scheme is formed.
Thus the power device of the disclosure, which is formed, has the multiple second bodies area for forming whole pressure ring and therebetween
The terminal structure of multiple spacer regions, the terminal pressure-resistance structure injected using multiple body areas, by the injection window that multiple body areas are arranged
The implantation dosage and spacing of mouth push away trap by high temperature and concentration gradient alternately whole pressure ring may be implemented in horizontal proliferation,
Multiple peak surface electric fields are provided under condition of high voltage, to improve resistance to pressure and pressure-resistant stability.For example, spacing is along transverse direction
Pressure-resistant direction incremental variations then form the distribution that doping concentration is successively decreased, to improve the pressure resistance of device in whole pressure ring
Effect improves the pressure-resistant stability of device, in addition, the disclosure additionally provides a kind of power device of the manufacture with multiple protection rings
The method of part.This method and current mainstream power device technique platform are all compatible, without increasing additional production cost, are easy to real
It is existing.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 is the schematic diagram of the power device with whole pressure ring terminal structure according to an embodiment of the present disclosure；
Fig. 2 to Fig. 8 is the manufacture power device with whole pressure ring terminal structure according to an embodiment of the present disclosure
The cross section block diagram in each stage；
Fig. 9 is the process of the manufacture power device with whole pressure ring terminal structure according to an embodiment of the present disclosure
Figure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
Power device according to the embodiment of the present disclosure may include cellular region and termination environment formed on a substrate.Cellular region
Active area as device includes grid, the first body area, the source region in first body area and drain region.Termination environment packet
Include multiple second bodies area and the spacer region between the second adjacent body area.Substrate is the first conduction type, such as N-type.
First body area, the second body area and spacer region are the second conduction type, such as p-type.Wherein, the doping concentration in the first body area is lower than the
The doping concentration in integrated area, spacer region is lower than the second body area.The junction depth in the second body area is greater than the junction depth in the first body area.Each second
Spacing (that is, width of spacer region) between the injection window in body area can be set to the junction depth less than the second body area.Thus
Trap technique (for example, thermal anneal process) is picked using after ion implanting, so that the spacer region in finally formed device structure
Conduction type (for example, the two can be the second conduction type) identical as the conduction type in the second body area and doping concentration it is low
Doping concentration in the second body area.
Fig. 1 shows showing for the power device 100 with whole pressure ring terminal structure according to an embodiment of the present disclosure
It is intended to.As shown in Figure 1, power device may include the epitaxial layer 2 formed on substrate 1, epitaxial layer can be divided into cellular
Area 3 and termination environment 4 form multiple first bodies area 5 in cellular region 3, form multiple second bodies area 6 in the termination region.Each phase
Spacer region 7 is respectively formed between two adjacent the second body areas 6, the width of spacer region 7 is (that is, between two adjacent individual areas
Away from) less than the junction depth in the second body area 6.The width of each spacer region 7 can be it is identical, be also possible to variation, that is, Ge Gexiang
Spacing between two adjacent the second body areas 6 can be at equal intervals, be also possible to become spacing.Substrate 1 and epitaxial layer 2 are the
One conduction type.First body area 5, the second body area 6 and spacer region 7 are the second conduction type, and doping concentration tapers off distribution,
That is, the doping concentration in the first body area 5 is greater than the doping concentration in the second body area 6, the doping concentration in the second body area 6 is greater than spacer region 7
Doping concentration.The the second body area 6 and spacer region 7 being located in termination environment 4 as a result, form the whole pressure ring with graded transition junction.
Comprising the whole pressure-resistant ring structure of this of multiple second bodies area and spacer region relative to traditional single track pressure resistance ring structure
Improve pressure-resistant efficiency.This is because the doping concentration of traditional single track pressure resistance ring structure is to be uniformly distributed along pressure-resistant direction,
When bearing high pressure, pressure ring all exhausts, and surface electric field distribution is that only peak value occur at both ends, is formed between epitaxial layer prominent
Become knot, pressure-resistant is inefficient.Comprising the whole pressure-resistant ring structure of this of multiple second bodies area and spacer region relative to traditional tool
There is the multiple tracks ring structure of multiple second bodies area (that is, the part for being separated with epitaxial layer 2 between the second adjacent body area), can protect
Under the premise of demonstrate,proving pressure-resistant efficiency, chip area is saved.This is because traditional multiple tracks ring structure, pushing away trap is still later multiple tracks
Ring, and be floating potential ring, when bearing high pressure, its pressure ring is half spent condition, and the induction of each current potential ring is different
Voltage, multiple peak values can be introduced in surface field.But since the spacer region between adjacent ring (for example, second body area) needs
If wider, it is therefore desirable to big chip area.
As shown in Figure 1, power device 100 further includes the source region 8 and body contact zone for the heavy doping being formed in the first body area
9, source region 8 is the first conduction type, and body contact zone 9 is the second conduction type.The heavy doping that body contact zone 9 is used as the first body area connects
Touch area.The power device of Fig. 1 is also equipped with gate oxide 10, grid polycrystalline silicon 11 and field oxide 12,10 He of gate oxide simultaneously
Grid polycrystalline silicon 11 is located at the gate structure that power device is formed in cellular region 3, field oxide 12 be located in termination environment 4 and
Cover multiple second bodies area 6 and multiple spacer regions 7.Insulating layer 10 and metal electrode 11 are additionally provided in cellular region.Metal electricity
Pole 11 and source region 8 and body contact zone 9 are connected to form the source configuration of power device.The first conduction type is formed in substrate 1
Drain region, then substrate bottom is carried out back thinning and metal layer on back production, to form the drain electrode of power device.
As shown in Figure 1, transition region is additionally provided at position adjacent with cellular region in termination environment 4, the transition region packet
Include with and the identical junction depth in the first body area first part and second part with junction depth identical as the second body area.
Fig. 2 to Fig. 8 is the manufacture power device with whole pressure ring terminal structure according to an embodiment of the present disclosure
The cross section block diagram in each stage.
As shown in Fig. 2, providing substrate 1, substrate 1 for example can be silicon substrate, be epitaxially-formed epitaxial layer on substrate 1
2, both substrate 1 and epitaxial layer 2 can be the first conduction type, such as N-type.
As shown in figure 3, setting injection window, carries out ion implanting to form multiple second bodies area 6, so above epitaxial layer
Carrying out picking trap (for example, thermal annealing) afterwards redistributes the ion of injection.The ion implanting is the second conduction type
Ion implanting, i.e., so that the conduction type in the second body area 6 is the second conduction type, such as p-type.Wherein, the setting of injection window exists
In termination environment.Spacing between injection window can be at equal intervals.In a further embodiment, the spacing between window is injected
It is also possible to become spacing, such as on laterally pressure-resistant direction is incremental variations.After carrying out picking trap, the second of formation
Body area 6 has certain junction depth, then the spacing injected between window can be set smaller than the second body area in advance in injection
Junction depth.And implantation dosage is adjusted, after completing to pick trap, to realize the spacer region 7 between the individual area 6 of adjacent two
Transoid, that is, the conduction type of spacer region 7 is changed into the second conduction type by the first conduction type, such as is changed into p-type by N-type.
Wherein, multiple injection window implantation dosages can be consistent, and be also possible to change on laterally pressure-resistant direction,
E.g. successively decrease variation.It is possible thereby to adjust the doping concentration distribution of the whole pressure ring eventually formed as needed.It is not examining
In the case where considering particular demands, the implantation dosage of multiple injection windows can be consistent, and to avoid reticle is increased, save work
Skill cost.Certainly, under particular demands, the implantation dosage of adjustable multiple injection windows, so that the note of each injection window
Enter that dosage is inconsistent, variation of e.g. successively decreasing.
As shown in figure 4, growing field oxide 10 on epitaxial layer 2, it is masked etching then to remove 3 top of cellular region
Field oxide 10.Thus expose the upper surface of the cellular region 3 of epitaxial layer 2.
As shown in figure 5, growing gate oxide 11 above the cellular region of epitaxial layer 23, then depositing polysilicon material is gone forward side by side
Row mask etching, to retain multiple polysilicon structures 12 spaced apart.Polysilicon structure 12 is used as the grid of power device.
As shown in fig. 6, carrying out ion implanting and picking trap to form the first body area 5.Spaced apart multiple can be formed
Integrated area 5, and the position in each first body area 5 corresponds respectively to the aperture position between each adjacent polysilicon structure 12.
The thin gate oxide 11 of the ion penetration of second conduction type injects in epitaxial layer 2, then carries out picking trap (for example, thermal annealing)
To form corresponding multiple first bodies area 5, can be less than by adjustment implantation dosage and Implantation Energy, the junction depth in the first body area 5
The junction depth in the second body area is formed before.
In addition, as shown in fig. 6, at position adjacent with cellular region 3 in termination environment 4, an adjacent first body area and
One the second body area is connected to form transition region 13, and transition region 13 includes having junction depth identical as the first body area as a result,
First part and second part with junction depth identical as the second body area.
As shown in fig. 7, etching away the gate oxide part at the aperture position between adjacent polysilicon structure, then exist
Ion implanting and thermal annealing are carried out in first body area 5 to form source region 8 and body contact zone 9.Both source region 8 and body contact zone 9 are all
It is heavy doping.Wherein, source region 8 is the first conduction type, such as N-type, and body contact zone 9 is the second conduction type, such as p-type.
Body contact zone 9 is used as the contact zone of the first body area 5 and transition region 13.
As shown in figure 8, body contact zone 9 and source region 8 is connected with metal layer 14, constitute transistor source；Substrate is carried out
Thinning back side and metal layer 15 make, and constitute transistor drain.Metal layer 15 covers entire substrate back.It is possible thereby to form tool
There is the power device of whole pressure ring.
Fig. 9 is the process of the manufacture power device with whole pressure ring terminal structure according to an embodiment of the present disclosure
Figure.Wherein, following steps are specifically described:
Step S110: being epitaxially grown on the substrate epitaxial layer, and the epitaxial layer includes cellular region and termination environment；
Step S120: ion implanting is carried out above epitaxial layer to form multiple second bodies area；
Step S130: trap is picked to form whole pressure ring to multiple second bodies area；
Step S140: growing field oxide on epitaxial layer, is masked etching then to remove the field above cellular region
Oxide layer；
Step S150: growing gate oxide above the cellular region of epitaxial layer, and then deposition and etches polycrystalline silicon are to form
Polysilicon gate；
Step S160: it carries out ion implanting and picks trap to form multiple first bodies area.
Step S170: forming source region in first body area, and each first body area and source region metal layer are connected
It connects, to form source electrode；
Step S180: carrying out back thinning the substrate bottom and metal layer on back production, to form drain electrode.
In above-mentioned steps, specific adjustment and setting can be done for certain steps therein.For example, in step S120
In, it carries out being pre-designed the factors such as spacing, implantation dosage and the Implantation Energy of injection window when the second body area ion implanting, make
The spacing that window must be injected is less than the junction depth in finally formed second body area, and then in S130 during picking trap, so that phase
Spacer region between the second adjacent body area is by transoid, so that the conduction type of the second body area and its spacer region becomes identical,
It such as is the second conduction type (for example, p-type).The second body as a result, in finally formed power device, positioned at termination environment
Area and its spacer region form whole pressure ring due to having identical conduction type.For example, in step S120 and step S160
Ion implanting in, different ion implantation dosage and Implantation Energy are separately designed, so that in finally formed first body area
Doping concentration is greater than the doping concentration in the second body area.And in the ion implanting of step S120, due to forming multiple injection windows
Mouthful to form multiple second bodies area, therefore, it can be directed to the different identical implantation dosages of injection window design, so that multiple the
The doping concentration in two-body area is identical.In a further embodiment, the different injection of different injection window designs can also be directed to
Dosage, for example, the mode successively decreased on laterally pressure-resistant direction designs implantation dosage, so that the doping concentration in multiple second bodies area exists
Laterally successively decrease on pressure resistance direction.
As a result, in power device according to an embodiment of the present disclosure, due to being formed in the termination region by multiple second
The whole pressure ring that body area and its multiple spacer regions are constituted improves resistance to pressure and pressure-resistant stability.Due to according to the disclosure
Embodiment power device in the multiple spacer regions for being used to form whole pressure ring width it is smaller, therefore according to the disclosure
Embodiment power device under the premise of guaranteeing high voltage performance, reduce the area occupied of termination environment, and then reduce
The area occupied of entire power device, reduces process costs.Meanwhile manufacturing power device according to an embodiment of the present disclosure
Method and current mainstream power device technique platform are all compatible, thus technique manufacture view do not increase yet additional technique at
This.
Although it have been described that example embodiment, it should be apparent to those skilled in the art that not
In the case where the spirit and scope for being detached from present inventive concept, it can make various changes and modifications.It will thus be appreciated that above-mentioned
Example embodiment is not limiting, but illustrative.
Claims (12)
1. a kind of power device, comprising:
Substrate；
The epitaxial layer of first conduction type, is set to the substrate, and the epitaxial layer includes cellular region and termination environment；
First body area of multiple second conduction types, is set in the cellular region of the epitaxial layer；
Second body area of multiple second conduction types, is set in the termination environment of the epitaxial layer；
Wherein, multiple spacer regions between the multiple second body area are the second conduction type, the multiple second conduction type
The second body area and the spacer regions of multiple second conduction types constitute the adjustable whole pressure ring of doping concentration distribution.
2. power device as described in claim 1, wherein the spacing between the injection window in the second adjacent body area is less than institute
State the junction depth in the second body area.
3. power device as described in claim 1, wherein the spacing between the injection window in the second adjacent body area is equal
's.
4. power device as described in claim 1, wherein the spacing between the injection window in the second adjacent body area is variation
's.
5. power device as described in claim 1, wherein the doping concentration in second body area is higher than mixing for the spacer region
Miscellaneous concentration.
6. power device as described in claim 1, wherein the doping concentration in second body area is lower than first body area
Doping concentration.
7. power device as described in claim 1, wherein the junction depth in second body area is greater than the knot in first body area
It is deep.
8. power device as claimed in claim 1, wherein further include the first conductive-type being formed in first body area
The source region of type and the drain region for forming the first conduction type in the substrate.
9. a kind of method for manufacturing power device, wherein include:
It is epitaxially grown on the substrate epitaxial layer, the epitaxial layer includes cellular region and termination environment；
Ion implanting is carried out above epitaxial layer to form multiple second bodies area；
Trap is picked to form whole pressure ring to multiple second bodies area；
Field oxide is grown on epitaxial layer, is masked etching then to remove the field oxide above cellular region；
It carries out ion implanting and picks trap to form multiple first bodies area.
10. method as claimed in claim 9, wherein further include:
Gate oxide is grown above the cellular region of epitaxial layer, then deposition and etches polycrystalline silicon are to form polysilicon gate；
Source region is formed in first body area, each first body area is connected with source region with metal layer, to form source electrode；
The substrate bottom is carried out back thinning and metal layer on back makes, to form drain electrode.
11. method as claimed in claim 9, wherein, will be adjacent when carrying out ion implanting to form multiple second body areas
Spacing between the injection window in the second body area is set smaller than the junction depth in second body area.
12. a kind of electronic equipment, including at least partly by power device shape as claimed in any of claims 1 to 8 in one of claims
At integrated circuit.
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