CN207353256U

CN207353256U - Semiconductor devices

Info

Publication number: CN207353256U
Application number: CN201720925164.4U
Authority: CN
Inventors: 单亚东; 谢刚; 张伟; 李枝; 李一枝
Original assignee: Guangzhou Micro Integrated Technology (shenzhen) Co Ltd
Current assignee: Guangzhou Micro Integrated Technology (shenzhen) Co Ltd
Priority date: 2017-07-27
Filing date: 2017-07-27
Publication date: 2018-05-11
Anticipated expiration: 2027-07-27

Abstract

The utility model discloses a kind of semiconductor devices, the problem of to solve in the case where not improving semiconductor devices electric leakage, reduce the conduction voltage drop of semiconductor devices.The semiconductor devices has a groove structure, and the bulk silicon region in the groove structure between arbitrary neighborhood groove forms JFET regions；The JFET regions have ion source doping.

Description

Semiconductor devices

Technical field

Semiconductor technology is the utility model is related to, more particularly to a kind of semiconductor devices.

Background technology

Schottky diode is a kind of monopole charge carrier device using electronics as carrier, because it is with relatively low conducting pressure Drop and faster switching frequency are widely used in Switching Power Supply and other are required in high-speed power switchgear.

Existing TMBS (trench gate Schottky diode) device is widely used, and improves schottky device characteristic, especially Improve since the potential barrier of Schottky itself reduces effect so that Schottky can produce larger leakage current in high pressure.It is but existing The body silicon resistivity of high pressure trench gate Schottky diode is very big, device is pressure-resistant it is higher, it is necessary to body silicon resistivity it is bigger, so So that device forward conduction voltage drop is larger.How so that Schottky diode obtains high voltage and with relatively low positive pressure The problem of drop is current urgent need to resolve.

The content of the invention

In order to overcome drawbacks described above, the technical problem to be solved by the present invention is to provide a kind of semiconductor devices, to The problem of solving in the case where not improving semiconductor devices electric leakage, reducing the conduction voltage drop of semiconductor devices.

In order to solve the above technical problems, a kind of semiconductor devices in the utility model, has groove structure, the groove Bulk silicon region in structure between arbitrary neighborhood groove forms JFET regions；The JFET regions have ion source doping.

Alternatively, the semiconductor devices includes N layers of the doping of epitaxial layer and growth on said epitaxial layer there；The groove Structure setting is in the epitaxial layer and N layers of the doping.

Alternatively, the JFET regions are respectively provided with the ion source doping of Gaussian Profile in machine and transverse direction；The doping N The doping concentration of layer is more than the doping concentration of the epitaxial layer；The ion gun includes n-type doping source and p-type doped source.

Alternatively, growth has gate oxide on each groove of the groove structure and/or the doping N layers.

Alternatively, the thickness of the gate oxide is determined by the default pressure voltage of the semiconductor devices.

Specifically, it is provided with polysilicon layer on the gate oxide of each groove.

Specifically, the groove structure forms have chance with region and terminal area.

Specifically, the region of having chance with is additionally provided with passivation layer.

Specifically, the material of the passivation layer is one of the following or combines：Silicon nitride and silica.

Specifically, the semiconductor devices further includes metal layer.

The utility model has the beneficial effect that：

Semiconductor devices in the utility model, can effectively reduce by half in the case where not improving semiconductor devices electric leakage The conduction voltage drop of conductor device.

Brief description of the drawings

Fig. 1-Fig. 8 is the structure diagram in each stage in the manufacturing process of semiconductor devices in the utility model；

Fig. 9 is the flow chart of the manufacture method of semiconductor devices in the utility model；

Figure 10 is that the horizontal dopant profiles schematic diagram of N layers 5 is adulterated in the utility model；

Figure 11 is conventional semiconductor devices in the utility model embodiment, the semiconductor devices of global ion implanting, this reality With the electrology characteristic schematic diagram of semiconductor devices in new embodiment.

Embodiment

In order to solve in the case where not improving semiconductor devices electric leakage, the conduction voltage drop for reducing semiconductor devices is asked Topic, the utility model provides a kind of semiconductor devices, below in conjunction with attached drawing and embodiment, to the utility model into advancing one Step describes in detail.It should be appreciated that specific embodiment described herein does not limit this practicality only to explain the utility model It is new.

As shown in figures 1-8, the utility model embodiment provides a kind of semiconductor devices, and the semiconductor devices has groove Structure, the bulk silicon region in the groove structure between arbitrary neighborhood groove form JFET regions；The JFET regions have ion Source doping.

Alternatively, the semiconductor devices includes the doping N layers 5 of epitaxial layer and growth on the epitaxial layer 2；The ditch Slot structure is arranged on the epitaxial layer 2 and the doping N layers 5.

The JFET regions are respectively provided with the ion source doping of Gaussian Profile in machine and transverse direction；N layers of the doping is mixed Miscellaneous concentration is more than the doping concentration of the epitaxial layer；The ion gun includes n-type doping source and p-type doped source.

Further, growth has gate oxide 6 on each groove of the groove structure and/or the doping N layers.

Wherein, the thickness of the gate oxide 6 is determined by the default pressure voltage of the semiconductor devices.

Specifically, it is provided with polysilicon layer 7 on the gate oxide 6 of each groove.

Alternatively, the groove structure forms have chance with region 10 and terminal area 11.

Wherein, the region 10 of having chance with is additionally provided with passivation layer.

Wherein, the material of the passivation layer is one of the following or combines：Silicon nitride and silica.

Alternatively, the semiconductor devices further includes metal layer 9.

Semiconductor devices effectively reduces by half in the case where not improving semiconductor devices electric leakage in the utility model embodiment The conduction voltage drop of conductor device.

Further illustrate the manufacture method and principle of the utility model.

As shown in figure 9, in the utility model semiconductor devices manufacture method, the described method includes：

S101, injects ion gun in the default injection zone of semiconductor substrate；

S102, by thermal diffusion, makes the ion gun enter default JFET regions；

S103, etches groove structure on the semiconductor substrate for completing thermal diffusion, forms semiconductor devices.

The utility model embodiment injects ion gun by the default injection zone in semiconductor substrate；By thermal diffusion, The ion gun is set to enter default JFET regions；Groove structure is etched on the semiconductor substrate for completing thermal diffusion, so that The semiconductor devices of formation reduces the conduction voltage drop of semiconductor devices in the case where not improving semiconductor devices electric leakage.

Wherein semiconductor substrate is specially the basic material for manufacturing semiconductor devices.

That is, the utility model embodiment uses local ion implantation technique, it is with silicon contact area nonmetallic Trench region uses ion implantation technique, allows impurity to enter JFET areas by thermal diffusion, reaches and adjusts JFET areas resistance Purpose, and then reduce the conduction voltage drop of device.

For example, trench gate Schottky diode, during forward conduction, the whole body silicon in MESA regions is involved in the defeated of electric current Send, and high concentration ion injection technique is used in JFET areas, the conducting resistance in this region can be significantly reduced, and then reduce device The conduction voltage drop of part.

On the basis of above-described embodiment, it is further proposed that the variant embodiment of above-described embodiment, needs what is illustrated herein It is, in order to make description brief, the only description and the difference of above-described embodiment in each variant embodiment.

Used in the utility model embodiment and be used to distinguish the prefixes such as " first ", " second " of component only for favourable In the explanation of the utility model, itself there is no specific meaning.

Alternatively, the default injection zone in semiconductor substrate injects ion gun, including：

As shown in Figure 1, in 2 growth regulation of epitaxial layer, one oxide layer 1 of the semiconductor substrate；

As shown in Fig. 2, according to the injection zone, photoetching is carried out in first oxide layer 1, forms barrier layer 20；

According to the barrier layer, ion gun is injected in the injection zone.

Further, it is described by thermal diffusion, the ion gun is entered default JFET regions, including：

As shown in figure 3, carrying out thermal annealing knot to the semiconductor substrate for injecting ion gun, the is grown during knot Dioxide layer 4, and doping N layers 5 are formed between second oxide layer 4 and the epitaxial layer 2 so that the ion gun into Enter the JFET regions.

Wherein, described N layers of doped source that Gaussian Profile is respectively provided with vertical and horizontal of doping；The doping of N layers of the doping Concentration is more than the doping concentration of the epitaxial layer；The ion gun includes n-type doping source and p-type doped source；The ion gun Implantation Energy is between 30KEV-120KEV, and the implantation dosage of the ion gun is 10¹¹~10¹³cm^-2Between；Second oxygen The thickness for changing layer is more than the thickness of first oxide layer.

Alternatively, the injection zone includes at least one ion implanting window；

Further, it is described to etch groove structure on the semiconductor substrate for completing thermal diffusion, including：

Determine center and the window area of each ion implanting window；

According to the center of each ion implanting window and window area, etched on the semiconductor substrate for completing thermal diffusion Groove structure；Bulk silicon region in the groove structure between arbitrary neighborhood groove forms the JFET regions.

Further, the center and window area according to each ion implanting window, completes the half of thermal diffusion Groove structure is etched on conductor substrate, including：

For each ion implanting window：

Center using the center of the ion implanting window as the trench etch window of respective groove；

According to the window area of the ion implanting window, the window area of the trench etch window of respective groove is determined；

According to the center of the trench etch window and window area, lost on the semiconductor substrate for completing thermal diffusion Carve respective groove.

Wherein, wherein the width of the window area of trench etch window be more than the ion implanting window window area width Degree.

Illustrate the utility model embodiment.

The utility model embodiment provides a kind of production method of alternatively low pressure drop trench gate Schottky diode, bag Include：

Step 1, the oxide layer 1 of one layer of 500A or so is grown on semiconductor substrate epitaxial layer 2, as the slow of ion implanting Layer is rushed, as shown in Figure 1.

Step 2, it is right on the semiconductor base surface first time photoetching, barrier layer of the photoresist 20 as ion implanting For N-type Schottky, ion gun can be PH₃, A_sH₃Deng ion implantation energy is between 30KEV-120KEV, ion implanting Dosage 10¹¹~10¹³cm^-2Between, as shown in Figure 2.

Step 3, then carry out thermal annealing to push away, grow a thickness oxide layer 4 during knot at the same time, as shown in Figure 3.Low Being formed on the epitaxial layer 2 of doping has medium-doped N layers 5, and the longitudinal dopant profiles of its medium-doped N layers 5 are in Gaussian Profile, due to Using local ion implantation technology, 5 horizontal dopant concentration peak vertex of doping N layers appears in ion implanting window centre position, There is unimplanted region middle part in peak value bottom.

Step 4, the photoetching of first time groove structure is carried out on the semiconductor substrate, etching is used as using thick oxide layer 4 Barrier layer, the groove structure etched is as shown in figure 4, the semiconductor trench etching window, as shown in figure 5, and ion implanting Window center position overlaps, and etching groove window width is more than ion implanting window width, the semiconductor substrate gash depth It is not necessarily intended to be more than highly doped N layers 5.

Step 5, gate oxide 6 is grown on the semiconductor substrate, gate oxide thickness is determined by device is pressure-resistant, then Polycrystalline silicon deposit is carried out, is anti-carved, is formed as shown in fig. 6, having in groove and anti-carves rear remaining polysilicon layer 7.

Passivation layer 8 is deposited on the semiconductor structure, which can be silicon nitride or silica, Then hole photoetching, etches active region 12, as shown in fig. 7, still having passivation layer 8 to cover on terminal area 11.

The splash-proofing sputtering metal layer 9 on the semiconductor structure, then photoetching, etching, the semiconductor device features eventually formed As shown in Figure 8.

Wherein, it is as shown in Figure 10 that the horizontal dopant profiles of N layers 5 are adulterated in step 3.

The utility model embodiment method is first to carry out one layer of ion implanting on surface before wafer groove etching technics.

Ion implanting barrier layer of the photoresist as non-implanted region is used in the utility model embodiment.

The utility model embodiment intermediate ion source can be n-type doping source PH₃、A_sH₃Or p-type doped source BF₃、 BCl₃Deng ion implantation energy is between 30KEV-120KEV, ion implantation dosage 10¹¹~10¹³cm^-2Between.

Etching groove window center position and the center weight of ion implanting photoetching window in the utility model embodiment Close, etching groove window is more than ion implanting window, can effectively ensure that ion implanting surface is etched away.

The utility model embodiment mainly chip have chance with area carry out ion implanting, epitaxial layer N- areas surface formed one Layer vertical and horizontal all have the N-type region domain of the medium-doped of Gaussian Profile doping, while by etching groove window center position Overlapped with ion implanting window center position, can etch away ion implanted regions part when carrying out etching groove, thus can Because of ion implanting silicon face caused by lattice damage remove completely.

By taking 100V trench gate Schottky diodes as an example, noted by device simulation software emulation conventional device, global ion Enter device, the electrology characteristic of the utility model local ion-implanted device, global ion implantation dosage is 10¹³cm^-2, inject energy 80KEV is measured, the utility model embodiment local ion implantation dosage is 2.5*10¹³cm^-2, Implantation Energy 80KEV.Figure 11 is three Kind device VF characteristic curves are new using global ion-implanted device and this practicality as can be seen from the figure compared to conventional device The device that type proposes has a relatively low forward voltage drop, while the local ion implantation technique of the utility model embodiment proposition can be with Effectively reduce device creepage.

Above-described embodiment, the purpose of this utility model, technical solution and beneficial effect have been carried out into One step describes in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit Determine the scope of protection of the utility model, where within the spirit and principles of the present invention, any modification for being made, equally replace Change, improve, should be included within the scope of protection of this utility model.

Claims

1. a kind of semiconductor devices, it is characterised in that the semiconductor devices has a groove structure, any in the groove structure Bulk silicon region between adjacent trenches forms JFET regions；The JFET regions have ion source doping.

2. semiconductor devices as claimed in claim 1, it is characterised in that the semiconductor devices includes epitaxial layer and is grown in N layers of doping on the epitaxial layer；The groove structure is arranged on the epitaxial layer and N layers of the doping.

3. semiconductor devices as claimed in claim 2, it is characterised in that the JFET regions are respectively provided with machine and transverse direction The ion source doping of Gaussian Profile；The doping concentration of N layers of the doping is more than the doping concentration of the epitaxial layer；The ion gun Including n-type doping source and p-type doped source.

4. semiconductor devices as claimed in claim 2, it is characterised in that each groove of the groove structure and/or described Growth has gate oxide on doping N layers.

5. semiconductor devices as claimed in claim 4, it is characterised in that the thickness of the gate oxide is by the semiconductor device The default pressure voltage of part determines.

6. semiconductor devices as claimed in claim 5, it is characterised in that be provided with polysilicon on the gate oxide of each groove Layer.

7. semiconductor devices as claimed in claim 6, it is characterised in that the groove structure forms have chance with region and termination environment Domain.

8. semiconductor devices as claimed in claim 7, it is characterised in that the region of having chance with is additionally provided with passivation layer.

9. the semiconductor devices as described in any one in claim 7-8, it is characterised in that the semiconductor devices further includes Metal layer.