CN105280723A - 4H-SiC floating junction barrier Schottky diode and preparation method thereof - Google Patents
4H-SiC floating junction barrier Schottky diode and preparation method thereof Download PDFInfo
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- 238000007667 floating Methods 0.000 title claims abstract description 81
- 230000004888 barrier function Effects 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000008569 process Effects 0.000 claims abstract description 7
- 238000000137 annealing Methods 0.000 claims description 15
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 12
- 238000004062 sedimentation Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 8
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 7
- 239000012159 carrier gas Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 claims description 7
- 239000007924 injection Substances 0.000 claims description 7
- 239000001294 propane Substances 0.000 claims description 7
- 229910000077 silane Inorganic materials 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 230000007547 defect Effects 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000001459 lithography Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 3
- 238000001657 homoepitaxy Methods 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
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- 241001661355 Synapsis Species 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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Abstract
The invention discloses a 4H-SiC floating junction barrier Schottky diode and a preparation method thereof. The 4H-SiC floating junction barrier Schottky diode comprises: a 4H-SiC substrate; a first 4H-SiC epitaxial layer positioned on the substrate, wherein floating junction layers are formed on the first 4H-SiC epitaxial layer; a second 4H-SiC epitaxial layer positioned on the first 4H-SiC epitaxial layer and the floating junction layers; junction barrier zones, terminal expansion parts and field limiting rings that are all disposed on the second 4H-SiC epitaxial layer; SiO2 layers over the terminal expansion parts and the field limiting rings and field plates over part of the SiO2 layers, wherein the middle of each field plate is equipped with a Schottky contact window; and a Schottky contact cathode positioned on the back side of the substrate and an anode positioned in the Schottky contact windows. The problem of high reverse leakage current of the 4H-SiC floating junction barrier Schottky diode is overcome. Meanwhile, a conventional method employing a high temperature ion implantation process to form a floating junction structure is replaced by an etching epitaxial process, so performance degradation of a device due to crystal lattice damage generated by ion implantation is solved, and then the performance of the device is effectively improved.
Description
Technical field
The present invention relates to semiconductor power technical field of electronic devices, particularly relate to a kind of 4H-SiC floating knot junction barrier schottky diode and preparation method thereof.
Background technology
First SiC Schottky barrier diode substitutes Si device at electric and electronic technical field as wide bandgap semiconductor power electronic device.The sharpest edges of SiC Schottky barrier diode in power electronics are almost desirable reverse recovery characteristic.At present, commercial SiC Schottky barrier diode has been applied in the fields such as high frequency switch power, power factor correction and motor driving.When being combined with current best power MOSFET, switching frequency can reach 400kHz, and is expected to realize higher than 1MHz.Many companies use SiC Schottky barrier diode to replace Si fast recovery diode in its IGBT frequency conversion or inverter, and the cost that its overall benefit causes considerably beyond the price variance between SiC and Si device increases.
But although the research of SiC-SBD has achieved the achievement of attracting attention very much at present, its performance has also had larger distance from the limit of SiC material itself.In recent years, the SiC film that the SiC crystal utilizing physical vapor transport (PVT) to grow and chemical vapour deposition technique (CVD) grow achieves surprising progress, but still containing defects such as a large amount of microtubule, dislocation and faults in crystal, these defects seriously hinder the performance of SiC high voltage power device.Meanwhile, from commercialization angle, although SiC power device market is very large, SiC success squeezes into power device market, finally still depends on its cost performance.Though achieved 6 inches of 4H-SiC substrate preparations at present, the exploitation of expanding technology experienced by the long period.Therefore, when cannot be reduced costs by raising crystal mass and increase SiC substrate size in a short time, only have by improving device architecture, the lead time of materials and devices is shortened in the research of the aspects such as optimum structural parameter, improves rate of finished products and reduce chip area to be only the correct direction reducing SiC power device price at present.
A large amount of Si base device research shows, adopts new construction effectively can improve the performance of semiconductor power device.2000, University of Electronic Science and Technology of China Chen Xing assist in education is awarded and is proposed to introduce transoid island (Opposite-dopedisland) structure at first in power device Withstand voltage layer and solve relation between power device conducting resistance and puncture voltage, by resolving conducting resistance and puncture voltage, obtain both calculated values.The research that SiC floats junction structure power device concentrates on Toshiba.2006, scaling theory is utilized to be optimized device architecture in the article " OptimizationofaSiCSuper-SBDBasedonScalingPropertiesofPow erDevices " that T.Hatakeyama delivers at it, and float junction Schottky barrier diode with the standby 4H-SiC of Toshiba cooperation, obtain Baliga quality factor (BFOM) maximum at that time.This person by optimum structural parameter and comparison terminal structure, obtains 2.57m Ω .cm in report in 2007
2on-state ratio resistance and the blocking voltage of 2.7KV, quality factor reach 11354MW/cm
2, close to 4H-SiC unipolar device theoretical limit.
But, from floating junction structure operation principle, when the 4H-SiC after optimization floats junction Schottky barrier diode reverse voltage; after depletion region expands to floating knot by Schottky contacts; be similar to guard ring principle, first drift region break-through, voltage only increases in second drift region.Now, schottky junctions synapsis electric field strength is very large, close to critical breakdown electric field.Larger electric field strength makes potential barrier reduce clearly, and reverse leakage current is very large.Meanwhile, floating knot layer adopts ion implantation to complete, and the High temperature ion of macro-energy and dosage can cause damage to SiC crystal, although high annealing can repair lattice damage, will inevitably have an impact, particularly reverse leakage current to device property.
Therefore, for above-mentioned technical problem, be necessary to provide a kind of 4H-SiC floating knot junction barrier schottky diode and preparation method thereof.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of 4H-SiC floating knot junction barrier schottky diode and preparation method thereof, this device architecture and technological process meet while floating junction structure improves puncture voltage and on-state ratio resistance, and reverse leakage current reduces obviously, effectively improves device performance.
To achieve these goals, the technical scheme that provides of the embodiment of the present invention is as follows:
4H-SiC floats a preparation method for knot junction barrier schottky diode, said method comprising the steps of:
S1, provide 4H-SiC substrate;
S2, employing low pressure hot wall chemical vapor sedimentation are at Grown the one 4H-SiC epitaxial loayer;
S3, deposition certain thickness SiO
2mask also makes etching window by lithography, and etches a 4H-SiC epitaxial loayer according to etching window, forms floating tie region;
S4, employing low pressure hot wall chemical vapor sedimentation carry out 4H-SiC isoepitaxial growth, form floating knot layer in floating tie region;
S5, employing chemical mechanical polishing method are by 4H-SiC and SiO of outer for floating tie region isoepitaxial growth
2mask is removed;
S6, employing low pressure hot wall chemical vapor sedimentation growth the 2nd 4H-SiC epitaxial loayer on a 4H-SiC epitaxial loayer and floating knot layer;
S7, on the 2nd 4H-SiC epitaxial loayer, ion implantation is adopted to form junction barrier district, knot termination extension and field limiting ring;
S8, utilize the certain thickness SiO of CVD (Chemical Vapor Deposition) method deposit
2and photoetching forms field plate, in the middle of field plate, form Schottky contacts window;
S9, at substrate back depositing metal and annealing forms the negative electrode of ohmic contact, photoetching Schottky contacts window deposit form the anode of Schottky contacts.
As a further improvement on the present invention, described floating knot floor comprises the floating knot floor active area be positioned at below junction barrier district and the floating knot floor termination environment be positioned at below knot termination extension and field limiting ring.
As a further improvement on the present invention, described floating knot layer is the floating knot of strip or the floating knot of point-like in floating knot layer active area.
As a further improvement on the present invention, in described step S2 and S6, the growth conditions of a 4H-SiC epitaxial loayer and the 2nd 4H-SiC epitaxial loayer is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source, N at 1600 DEG C
2as donor dopant, doping content N
d=2.5 × 10
16/ cm
-3.
As a further improvement on the present invention, the thickness of a described 4H-SiC epitaxial loayer is greater than the thickness of the 2nd 4H-SiC epitaxial loayer.
As a further improvement on the present invention, in described step S4, the growth conditions of 4H-SiC homoepitaxy is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source at 1600 DEG C, and trimethyl aluminium is acceptor dopants, doping content N
a=1 × 10
18/ cm
-3.
As a further improvement on the present invention, described step S7 intermediate ion injects and adopts Al
+ion repeatedly injects by different-energy and metering, and implantation temperature is 500 DEG C.
As a further improvement on the present invention, described step S7 intermediate ion also comprises after injecting: high annealing removes the defect also activation injection ion that energetic ion injection process produces, and annealing conditions is the lower 1600 DEG C of annealing of Ar atmosphere 10 minutes.
As a further improvement on the present invention, in described step S9, annealing conditions is that at 1000 DEG C, nitrogen environment is annealed 3 minutes.
Correspondingly, the invention also discloses a kind of 4H-SiC floating knot junction barrier schottky diode, described 4H-SiC floating knot junction barrier schottky diode comprises:
4H-SiC substrate;
Be positioned at the 4H-SiC epitaxial loayer on substrate, above a 4H-SiC epitaxial loayer, be formed with floating knot layer;
Be positioned at the 2nd 4H-SiC epitaxial loayer on a 4H-SiC epitaxial loayer and floating knot layer;
Be positioned at the junction barrier district on the 2nd 4H-SiC epitaxial loayer, knot termination extension and field limiting ring;
Be positioned at the SiO above knot termination extension and field limiting ring
2layer and be positioned at part SiO
2field plate on layer, forms Schottky contacts window in the middle of field plate;
Be positioned at the negative electrode of the ohmic contact of substrate back and be positioned at the anode of Schottky contacts window Schottky contacts.
The present invention has following beneficial effect:
To float in knot and junction barrier structure introducing 4H-SiC Schottky barrier diode, and propose 4H-SiC floating knot junction barrier schottky diode, improve 4H-SiC and float the large problem of junction Schottky barrier diode reverse leakage current;
Meanwhile, consider technological feasibility, the method that conventional high-temperature ion implantation technology is formed floating junction structure by the present invention changes into etching epitaxy technique, solves the problem that ion implantation generation lattice damage causes device performance to decline, effectively improves device performance.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation that in the embodiment of the invention, 4H-SiC floats knot junction barrier schottky diode;
Fig. 2 a, 2b are respectively strip in the present invention and float knot and point-like floats the structural representation of knot;
Fig. 3 a ~ 3i is preparation technology's schematic diagram that in the embodiment of the invention, 4H-SiC floats knot junction barrier schottky diode.
Embodiment
Technical scheme in the present invention is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
Shown in ginseng Fig. 1, in an embodiment of the present invention, 4H-SiC floating knot junction barrier schottky diode comprises:
4H-SiC substrate 10, substrate 10 is n
+type;
4H-SiC epitaxial loayer the 20, one 4H-SiC epitaxial loayer 20 be positioned on substrate is n-type epitaxial loayer, is formed with floating knot layer 30 above a 4H-SiC epitaxial loayer, comprises the floating knot (buried regions) of some p-types in floating knot layer 30;
The 2nd 4H-SiC epitaxial loayer the 40, two 4H-SiC epitaxial loayer 40 be positioned on a 4H-SiC epitaxial loayer 20 and floating knot layer 30 is n-type epitaxial loayer;
Be positioned at the junction barrier district 51 on the 2nd 4H-SiC epitaxial loayer 40, knot termination extension 52 and field limiting ring 53;
Be positioned at the SiO above knot termination extension 52 and field limiting ring 53
2layer 60 and be positioned at part SiO
2field plate 70 on layer, forms Schottky contacts window in the middle of field plate;
Be positioned at the negative electrode 81 of the ohmic contact at substrate 10 back side and be positioned at the anode 82 of Schottky contacts window Schottky contacts.
In the present invention, floating junction structure (FJ) is according to charge compensation principle design, by embedding the floating knot (buried regions) of p-type in 4H-SiCn type epitaxial loayer, drift region is divided into upper and lower two parts, as Fig. 1.Owing to embedded in the floating knot of p-type, when reverse voltage increases, depletion region is expanded to floating knot by Schottky contacts, and when first drift region exhausts completely, depletion region is tied to extended cathode, until lower part drift region also exhausts completely by floating.Compared with forming a triangle electric field with Conventional Schottky barrier diode drift region, two parts up and down of floating junction structure drift region form respectively two leg-of-mutton electric fields, as shown on the right of Fig. 1.Therefore, form a triangle Electric Field Distribution compared to traditional schottky barrier diode, floating junction structure can increase drift doping concentration and keep withstand voltage constant to reduce on-state ratio resistance, and device quality factor increases obviously.
From floating junction structure operation principle, when the requirement on devices depletion region after optimization expands to floating knot by Schottky contacts, schottky junctions synapsis electric field strength is close to SiC critical breakdown electric field, and device withstand voltage is maximum.Larger electric field strength makes potential barrier reduce clearly, and reverse leakage current is very large.Consider this point, the present invention proposes to adopt junction barrier schottky diode (JBS) structure to carry out shielded surfaces electric field, and restriction Schottky barrier reduces, and reduces reverse leakage current.
Floating knot floor 20 comprises the floating knot floor active area be positioned at below junction barrier district 51 and the floating knot floor termination environment be positioned at below knot termination extension 52 and field limiting ring 53.Floating knot layer is the floating knot of strip or the floating knot of point-like in floating knot layer active area, is respectively strip and floats and to tie or point-like floats the structural representation of knot shown in ginseng Fig. 2 a, 2b.
Because the diffusion coefficient of impurity in SiC is very low, want to reach desirable diffusion coefficient (10
-13cm
2.s
-1often need above) high temperature of more than 2000 DEG C, high temperature furnace is difficult to reach.At present, SiC doping only has the situ doping of employing epitaxial process or ion implantation doping two kinds of methods.4H-SiC floats in junction Schottky barrier diode, and floating knot adopts high temperature tension to be formed usually.But ion implantation will inevitably produce lattice damage and floating knot layer is positioned in the middle part of drift region, can have an impact to device electrology characteristic.
Based on above reason, ginseng Fig. 3 shown in, in the above-mentioned embodiment of the present invention 4H-SiC float knot junction barrier schottky diode preparation method specifically comprise the following steps:
S1, provide 4H-SiC substrate 10, shown in ginseng Fig. 3 a, substrate 10 thickness 360 μm, substrate doping 1 × 10
19cm
-3, 8 °, (0001) face partially.
S2, employing low pressure hot wall chemical vapor sedimentation (LP-CVD) are looked unfamiliar at the Si of substrate 10 and are grown a 4H-SiC epitaxial loayer 20, shown in ginseng Fig. 3 b.
In present embodiment, growth conditions is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source, N at 1600 DEG C
2as donor dopant, doping content N
d=2.5 × 10
16/ cm
-3, growth thickness 6 μm.
Shown in S3, ginseng Fig. 3 c, deposition certain thickness SiO
2mask also makes etching window by lithography, and etches a 4H-SiC epitaxial loayer according to etching window, forms floating tie region.
First certain thickness SiO is deposited
2mask also makes etching window by lithography, then adopts ICP etching technics to etch a 4H-SiC epitaxial loayer, etches floating tie region, etching depth 1 μm.ICP etch technological condition is: IPC coil power 1000W, source power 200W, reacting gas SF
6and O
2, flow is respectively 40sccm and 10sccm.
4H-SiC isoepitaxial growth is carried out in S4, employing low pressure hot wall chemical vapor sedimentation (LP-CVD), forms floating knot layer 30 in floating tie region, shown in ginseng Fig. 3 d.
In present embodiment, growth conditions is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source at 1600 DEG C, and trimethyl aluminium is acceptor dopants, doping content N
a=1 × 10
18/ cm
-3, growth thickness 1 μm.
Shown in S5, ginseng Fig. 3 e, adopt chemical mechanical polishing method (CMP) by 4H-SiC and SiO of outer for floating knot layer isoepitaxial growth
2mask is removed.
S6, employing low pressure hot wall chemical vapor sedimentation (LP-CVD) growth the 2nd 4H-SiC epitaxial loayer 40 on a 4H-SiC epitaxial loayer and floating knot layer, joins shown in Fig. 3 f.
In present embodiment, growth conditions is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source, N at 1600 DEG C
2as donor dopant, doping content N
d=2.5 × 10
16/ cm
-3, growth thickness 5 μm.
S7, on the 2nd 4H-SiC epitaxial loayer 40, ion implantation is adopted to form junction barrier district (JBS) 51, knot termination extension (JTE) 52 and field limiting ring (FLR) 53, shown in ginseng Fig. 3 g.
Ion implantation adopts Al
+ion, implantation temperature 500 DEG C.In order to form the box distribution of implanted dopant, adopt the injection of four different-energies and metering.
After ion implantation, high annealing removes the defect activation injection ion that produce in energetic ion injection process, and annealing conditions is: the lower 1600 DEG C of annealing of Ar atmosphere 10 minutes.
S8, utilize the certain thickness SiO of CVD (Chemical Vapor Deposition) method deposit
2layer 60 also photoetching forms field plate 70, shown in ginseng Fig. 3 h, wherein forms Schottky contacts window in the middle of field plate.
S9, at substrate back depositing metal Ni and annealing forms the negative electrode 81 of ohmic contact, photoetching Schottky contacts window depositing metal Ni form the anode 82 of Schottky contacts, shown in ginseng Fig. 3 i.
Above-mentioned preparation method adopts etching epitaxy technique to realize floating knot layer, avoids the lattice damage adopting ion implantation to produce, ensure that the electrology characteristic of device.
In Schottky barrier diode design, MPS (MergedpnjunctionSBD) structure can shield schottky junctions synapsis electric field strength equally, reduces reverse leakage current.But MPS structure working principle is identical with JBS, just MPS structure is applicable to high tension apparatus, there is conductivity modulation effect.The present invention also goes in MPS structure.
As can be seen from the above technical solutions, the present invention has following beneficial effect:
To float in knot and junction barrier structure introducing 4H-SiC Schottky barrier diode, and propose 4H-SiC floating knot junction barrier schottky diode, improve 4H-SiC and float the large problem of junction Schottky barrier diode reverse leakage current;
Meanwhile, consider technological feasibility, the method that conventional high-temperature ion implantation technology is formed floating junction structure by the present invention changes into etching epitaxy technique, solves the problem that ion implantation generation lattice damage causes device performance to decline, effectively improves device performance.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (10)
1. 4H-SiC floats a preparation method for knot junction barrier schottky diode, it is characterized in that, said method comprising the steps of:
S1, provide 4H-SiC substrate;
S2, employing low pressure hot wall chemical vapor sedimentation are at Grown the one 4H-SiC epitaxial loayer;
S3, deposition certain thickness SiO
2mask also makes etching window by lithography, and etches a 4H-SiC epitaxial loayer according to etching window, forms floating tie region;
S4, employing low pressure hot wall chemical vapor sedimentation carry out 4H-SiC isoepitaxial growth, form floating knot layer in floating tie region;
S5, employing chemical mechanical polishing method are by 4H-SiC and SiO of outer for floating tie region isoepitaxial growth
2mask is removed;
S6, employing low pressure hot wall chemical vapor sedimentation growth the 2nd 4H-SiC epitaxial loayer on a 4H-SiC epitaxial loayer and floating knot layer;
S7, on the 2nd 4H-SiC epitaxial loayer, ion implantation is adopted to form junction barrier district, knot termination extension and field limiting ring;
S8, utilize the certain thickness SiO of CVD (Chemical Vapor Deposition) method deposit
2and photoetching forms field plate, in the middle of field plate, form Schottky contacts window;
S9, at substrate back depositing metal and annealing forms the negative electrode of ohmic contact, photoetching Schottky contacts window deposit form the anode of Schottky contacts.
2. preparation method according to claim 1, is characterized in that, described floating knot floor comprises the floating knot floor active area be positioned at below junction barrier district and the floating knot floor termination environment be positioned at below knot termination extension and field limiting ring.
3. preparation method according to claim 2, is characterized in that, described floating knot layer is the floating knot of strip or the floating knot of point-like in floating knot layer active area.
4. preparation method according to claim 1, is characterized in that, in described step S2 and S6, the growth conditions of a 4H-SiC epitaxial loayer and the 2nd 4H-SiC epitaxial loayer is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source, N at 1600 DEG C
2as donor dopant, doping content N
d=2.5 × 10
16/ cm
-3.
5. preparation method according to claim 4, is characterized in that, the thickness of a described 4H-SiC epitaxial loayer is greater than the thickness of the 2nd 4H-SiC epitaxial loayer.
6. preparation method according to claim 1, is characterized in that, in described step S4, the growth conditions of 4H-SiC homoepitaxy is: high-purity H
2as carrier gas, silane and propane carry out isoepitaxial growth as Si and C source at 1600 DEG C, and trimethyl aluminium is acceptor dopants, doping content N
a=1 × 10
18/ cm
-3.
7. preparation method according to claim 1, is characterized in that, described step S7 intermediate ion injects and adopts Al
+ion repeatedly injects by different-energy and metering, and implantation temperature is 500 DEG C.
8. preparation method according to claim 7, it is characterized in that, described step S7 intermediate ion also comprises after injecting: high annealing removes the defect also activation injection ion that energetic ion injection process produces, and annealing conditions is the lower 1600 DEG C of annealing of Ar atmosphere 10 minutes.
9. preparation method according to claim 1, is characterized in that, in described step S9, annealing conditions is that at 1000 DEG C, nitrogen environment is annealed 3 minutes.
10. application rights requires the 4H-SiC floating knot junction barrier schottky diode that any one of 1 ~ 9, preparation method prepares, and it is characterized in that, described 4H-SiC floating knot junction barrier schottky diode comprises:
4H-SiC substrate;
Be positioned at the 4H-SiC epitaxial loayer on substrate, above a 4H-SiC epitaxial loayer, be formed with floating knot layer;
Be positioned at the 2nd 4H-SiC epitaxial loayer on a 4H-SiC epitaxial loayer and floating knot layer;
Be positioned at the junction barrier district on the 2nd 4H-SiC epitaxial loayer, knot termination extension and field limiting ring;
Be positioned at the SiO above knot termination extension and field limiting ring
2layer and be positioned at part SiO
2field plate on layer, forms Schottky contacts window in the middle of field plate;
Be positioned at the negative electrode of the ohmic contact of substrate back and be positioned at the anode of Schottky contacts window Schottky contacts.
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