CN107275391B - Composite terminal structure for silicon carbide semiconductor power device and preparation method - Google Patents
Composite terminal structure for silicon carbide semiconductor power device and preparation method Download PDFInfo
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- 239000002131 composite material Substances 0.000 title claims abstract description 56
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 54
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims description 11
- 239000010410 layer Substances 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005215 recombination Methods 0.000 claims description 4
- 230000006798 recombination Effects 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 230000000903 blocking effect Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000011259 mixed solution Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
- H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
A composite terminal structure for silicon carbide semiconductor power device and its preparation method, under the condition of not changing the terminal area, has improved the tolerance range to ion implantation concentration error of the terminal; the influence of the diffusion of the injected ions on the device terminal is avoided to the greatest extent, the area of the device terminal is reduced, and the yield of the device is improved. The composite terminal structure includes: a first junction termination extension; a second junction termination extension; a field limiting ring; a first overlap region formed by an overlap portion of the first junction termination extension and the second junction termination extension; and a second overlap region formed by an overlap portion of the field limiting ring and the second junction termination extension.
Description
Technical Field
The invention relates to the field of preparation of silicon carbide semiconductor power devices, in particular to a composite terminal structure for a high-voltage silicon carbide semiconductor power device and a preparation method thereof.
Background
Silicon carbide is an emerging third generation semiconductor material with excellent physical and electrical properties. Has wide application prospect in the fields of charging devices, rail transit, smart grids, green energy sources and the like.
Since the semiconductor device has a limited size, a junction termination structure for protecting the device is usually provided at the junction edge of the power device in order to alleviate the problem of breakdown of the device due to concentration of electric field at the edge of the device. Common termination structures mainly include field plates, field limiting rings, junction Termination Extensions (JTE), and the like, and these termination structures have been widely used in various semiconductor power devices.
For a common silicon carbide power device, the blocking voltage requirement can be met by using only a single terminal structure. However, for devices with higher requirements on consistency and reliability, larger terminal area and multiple photolithography and ion implantation processes are required, and the silicon carbide power device with a single terminal structure is more and more disadvantageous due to the problems of material cost and yield caused by the terminal structure: the terminal of the high-voltage silicon carbide device occupies too large area of a wafer, the process times are more, and the yield and the repeatability are lower; silicon carbide single termination may have a significant degradation in termination performance due to diffusion of implanted ions during annealing.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a composite termination structure for a silicon carbide semiconductor power device and a method of manufacturing the same. The composite terminal structure of the silicon carbide semiconductor power device with small occupied area, high yield and high repeatability is formed by using the photoetching times and the ion implantation times as few as possible.
The composite termination structure can be implemented in silicon carbide JBS diode devices, PIN diode devices, MOSFET devices, IGBT devices, etc., but is not limited to these power devices.
The invention provides a composite terminal structure for a silicon carbide semiconductor power device, which is characterized by comprising the following components: a first junction termination extension; a second junction termination extension; a field limiting ring; a first overlap region formed by an overlap portion of the first junction termination extension and the second junction termination extension; and a second overlap region formed by an overlap portion of the field limiting ring and the second junction termination extension.
The composite terminal structure for the silicon carbide semiconductor power device, provided by the invention, is characterized in that the width of the first junction terminal expansion is shorter than that of the second junction terminal expansion, and the depth of the first junction terminal expansion is deeper than that of the second junction terminal expansion.
The composite terminal structure for the silicon carbide semiconductor power device, provided by the invention, is characterized in that the field limiting ring and the first junction terminal extension are formed simultaneously, and the field limiting ring and the first junction terminal extension have the same doping concentration and depth.
According to the composite terminal structure for the silicon carbide semiconductor power device, the width of the first superposition area is the same as that of the first junction terminal extension, and the doping concentration of the first superposition area is equal to the sum of the doping concentrations of the first junction terminal extension and the second junction terminal extension; the width of the second recombination region is the same as the width of the field limiting ring, and the doping concentration of the second recombination region is equal to the sum of the doping concentration of the second junction termination extension and the field limiting ring.
The composite terminal structure for the silicon carbide semiconductor power device is characterized in that the composite terminal structure and the main junction are formed on an epitaxial wafer, and the composite terminal structure is directly connected with the main junction and has the same doping type as the main junction.
The composite terminal structure for the silicon carbide semiconductor power device, provided by the invention, has the advantages that the depth of the first junction terminal expansion and the depth of the field limiting ring are larger than that of the main junction, and the depth of the second junction terminal expansion is smaller than that of the main junction.
The invention also provides a preparation method of the composite terminal structure for the silicon carbide semiconductor power device, which is characterized by comprising the following steps: depositing a protective layer; first terminal ion implantation; a second terminal ion implantation; the passivation layer is oxidized and deposited.
According to the preparation method of the composite terminal structure for the silicon carbide semiconductor power device, through the first terminal ion implantation, a first junction terminal extension and a field limiting ring are formed at the same time, and the field limiting ring and the first junction terminal extension have the same doping concentration and depth.
According to the preparation method of the composite terminal structure for the silicon carbide semiconductor power device, the second terminal ion implantation is adopted to form the second junction terminal extension, the width of the first junction terminal extension is shorter than that of the second junction terminal extension, and the depth of the first junction terminal extension is deeper than that of the second junction terminal extension.
According to the preparation method of the composite terminal structure for the silicon carbide semiconductor power device, the second junction terminal extension is formed through the first terminal ion implantation.
According to the preparation method of the composite terminal structure for the silicon carbide semiconductor power device, through the second terminal ion implantation, a first junction terminal extension and a field limiting ring are formed at the same time, the field limiting ring and the first junction terminal extension have the same doping concentration and depth, the width of the first junction terminal extension is shorter than that of the second junction terminal extension, and the depth of the first junction terminal extension is deeper than that of the second junction terminal extension.
According to the preparation method of the composite terminal structure for the silicon carbide semiconductor power device, the overlapping part of the first junction terminal extension and the second junction terminal extension is formed into a first overlapping region, the width of the first overlapping region is identical to the width of the first junction terminal extension, the doping concentration of the first overlapping region is equal to the sum of the doping concentrations of the first junction terminal extension and the second junction terminal extension, the overlapping part of the field limiting ring and the second junction terminal extension is formed into a second overlapping region, the width of the second overlapping region is identical to the width of the field limiting ring, and the doping concentration of the second overlapping region is equal to the sum of the doping concentrations of the second junction terminal extension and the field limiting ring.
According to the composite terminal structure for the silicon carbide semiconductor power device and the preparation method thereof, the following beneficial technical effects are generated: under the condition of not changing the area of the terminal, the tolerance range of the ion implantation concentration error of the terminal is improved; the influence of the diffusion of the injected ions on the device terminal is avoided to the greatest extent, the area of the device terminal is reduced, and the yield of the device is improved. And forming a composite terminal structure suitable for the silicon carbide power device with the voltage of more than 600V by using the photoetching times and the ion implantation times as few as possible. The composite terminal structure is suitable for high-voltage silicon carbide power devices, such as silicon carbide Schottky diodes, silicon carbide MOSFETs, silicon carbide PiN diodes, silicon carbide IGBT and the like.
Drawings
The invention is described below with reference to the accompanying drawings in combination with examples. In the drawings:
FIG. 1 illustrates a composite termination structure for a high voltage silicon carbide power device in accordance with an embodiment of the present invention;
FIG. 2 (a) illustrates a termination structure of a conventional double JTE structure;
FIG. 2 (b) illustrates the relationship between device blocking voltage and doping concentration under ideal conditions when a conventional double JTE structure is applied to a 10 kV-magnitude SiC IGBT device;
FIG. 2 (c) illustrates the relationship between blocking voltage and doping concentration if implant ion diffusion occurs when a conventional double JTE structure is applied to a 10 kV-magnitude SiC IGBT device;
FIG. 3 (a) illustrates the relationship between blocking voltage and doping concentration of a device when the composite termination structure of the embodiment of the invention is applied to a 10 kV-magnitude SiC IGBT device;
FIG. 3 (b) illustrates the electric field intensity distribution at the bottom of the device terminal when the composite terminal structure of the embodiment of the invention is applied to a 10 kV-magnitude SiC IGBT device and 12kV voltage is blocked;
fig. 4 is a flow chart of the preparation of a composite terminal structure according to an embodiment of the present invention.
FIG. 5 illustrates process steps of a preparation flow of a composite terminal structure according to an embodiment of the present invention;
fig. 6 illustrates the process steps of the preparation flow of the composite terminal structure according to an embodiment of the present invention.
Detailed Description
In order to further explain the technical content of the present invention, the following detailed description will be given with reference to the embodiments and the accompanying drawings.
Fig. 1 illustrates a composite termination structure for a high voltage silicon carbide power device in accordance with an embodiment of the present invention. As shown in fig. 1, the composite termination structure includes a first junction termination extension 103, a second junction termination extension 104, a number of field limiting rings 105 formed simultaneously with the first junction termination extension 103, a first overlap region 106, and a second overlap region 107.
A composite termination structure and a main junction 102 are formed on epitaxial wafer 101, the composite termination structure being directly connected to main junction 102 and having the same doping type as main junction 102. The main junction 102 may be a P-type implant of JBS diode, a P-type implant of PIN diode, or a well of MOSFET and IGBT.
Referring to fig. 1, a first junction termination extension 103 is formed adjacent to the main junction 102, and a second junction termination extension 104 is formed outside the first junction termination extension 103 and the field limiting ring 105. Wherein the first junction termination extension 103 is shorter in width and deeper in depth and the second junction termination extension 104 is longer in width and shallower in depth. The field stop ring 105 is formed on the epitaxial wafer 101 simultaneously with the first junction termination extension 103, so that the field stop ring 105 has the same doping concentration and depth as the first junction termination extension 103. The depth of the first junction termination extension 103 and the field stop ring 105 is greater than the depth of the main junction 102.
The overlapping portion of the first junction terminal extension 103 and the second junction terminal extension 104 is a first overlapping region 106, the width of the first overlapping region 106 is the same as the width of the first junction terminal extension 103, and the doping concentration of the first overlapping region 106 is approximately equal to the sum of the doping concentrations of the first junction terminal extension 103 and the second junction terminal extension 104. The overlapping portion of the field limiting ring 105 and the second junction termination extension 104 is a second overlapping region 107, the width of the second overlapping region 107 is the same as the width of the field limiting ring 105, and the doping concentration of the second overlapping region 107 is approximately equal to the sum of the doping concentrations of the second junction termination extension 104 and the field limiting ring 105. Overlying the composite termination structure is a passivation layer 108 formed by thermal oxidation and PECVD.
The function of the field limiting ring 105 is to increase the tolerance of the ion implantation doping concentration without increasing the composite termination area. The field limiting rings 105 have a ring width of 3 μm, a first ring to first junction termination extension 103 distance of 3 μm, a second ring to first ring distance of 4 μm, a third ring to second ring distance of 5 μm, and so on, but the number, size, and spacing of the rings is not limited.
The width of the first junction termination extension 103 is about 60 um for a 600V voltage class device and about 250 um for a 20kV voltage class device.
The implantation energy of the second junction termination extension 104 is less than the main junction 102 and thus less deep than the main junction 102. The width of the second junction termination extension 104 is also different for devices of different voltage levels. The width of the second junction termination extension 104 is about 60 um for a 600V voltage class device and about 400 um for a 20kV voltage class device.
The technical effects that the composite terminal structure of the present invention can achieve are illustrated by comparing the composite terminal structure of the present invention with the existing terminal structure.
Fig. 2 (a) illustrates a conventional dual JTE terminal structure. As shown in fig. 2 (a), the conventional dual JTE terminal structure consists in part of adjacent first and second junction terminal extensions 203, 204, and a passivation layer 205. FIG. 2 (b) illustrates the blocking voltage of the device corresponding to different JTE doping when a conventional double JTE termination structure is applied to a silicon carbide 10 kV-magnitude P-channel IGBT; fig. 2 (c) illustrates the blocking voltage of the device after diffusion of the implanted ions has occurred, corresponding to different JTE doping.
As can be seen from the results of fig. 2 (b) and fig. 2 (c), although the conventional double JTE terminal structure can perform an effective termination function in an ideal case, the effect of the conventional double JTE terminal structure is greatly reduced after the implanted ions are diffused, resulting in difficulty in meeting the design requirements of the actual blocking voltage of the device.
Fig. 3 (a) illustrates the blocking voltage of the device corresponding to different JTE doping after the composite termination structure of the present invention is employed. In the composite terminal structure, as the first junction terminal extension and the second junction terminal extension are overlapped, the diffusion of the implanted ions in the SiC material has little influence on the device performance, and meanwhile, the structure improves the tolerance of the doping concentration of the composite terminal to a certain extent.
Fig. 3 (b) illustrates the electric field strength at the bottom of the composite termination when the device blocks 12kV voltage. As can be seen from fig. 3 (b), the additional field limiting ring acts to reduce the fringe electric field of the first junction termination extension, increasing the possible doping range of the first junction termination extension.
From the comparison, the composite terminal structure suitable for the high-voltage silicon carbide power device, which is designed by the invention, improves the tolerance range of the terminal ion implantation concentration error under the condition of not changing the terminal area; the influence of the diffusion of the injected ions on the terminal of the device is avoided to the greatest extent, the terminal area of the device is reduced, and the yield of the device is improved.
In view of comprehensive consideration of device performance, process cost, yield and the like, a method for preparing a composite terminal structure is described in detail below by taking a composite terminal structure realized in a 10 kV-level silicon carbide P-channel IGBT device as an example in combination with the accompanying drawings. Fig. 4 is a flow chart of the preparation of a composite terminal structure according to an embodiment of the present invention.
As shown in fig. 4, first, in step S401, a protective layer is deposited. Fig. 5 and 6 illustrate process steps of a preparation flow of a composite terminal structure according to an embodiment of the present invention. Referring to fig. 5, a main junction 102 is formed on an epitaxial wafer 101 using a standard IGBT manufacturing process prior to depositing a protective layer. Because the embodiment is a P-channel IGBT device, the main junction 102 is an N-type doped IGBT well region, the depth is 0.6um, and the junction doping is 1E18cm -3 . Then, a silicon dioxide protective layer is deposited on the SiC surface by PECVD with the thickness of 100nm. The silicon dioxide protective layer has the functions of avoiding forming a low-doped high-resistance region on the surface of SiC after ion implantation and protecting the surface of the SiC material in the ion implantation process.
Next, in step S402, a first termination ion implantation is performed. The first junction termination extension 103 and field stop ring 105 are formed by a first termination ion implantation.
Specifically, after the wafer surface is glued and baked, the first terminal photolithography mask is used for photolithography. After development, ni with a thickness of 300nm was evaporated and stripped off as a mask for ion implantation.
And then carrying out first terminal ion implantation by using a high-energy ion implanter, wherein the doping is distributed in a box shape. The first junction termination extension 103 and the field stop ring 105 are formed by a first termination ion implantation, the first junction termination extension 103 having a width of 130 μm and a depth of 0.65 μm, the doping concentration being about 1/15 of the concentration of the main junction 102. The doping concentration of the first junction termination extension 103 in this embodiment is 7E16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the Field of technologyThe confinement rings 5 consist of three rings with a width of 3 μm, spacing between the rings of 3 μm, 4 μm, 5 μm, the doping concentration and depth of the field confinement rings 5 being the same as the first junction termination extension 103.
Next, in step S403, a second termination ion implantation is performed. A second junction termination extension 104 is formed by a second termination ion implantation.
Specifically, after step S402 is completed, the metal and silicon dioxide remaining on the surface of the SiC material in step S401 are removed by using HNO3, HCl 3:1 mixed solution, concentrated sulfuric acid hydrogen peroxide 3:1 mixed solution, and BOE solution, and 100nm silicon dioxide is deposited again after the wafer is cleaned.
As shown in fig. 5, after the wafer surface is glued and baked, a second end-of-line reticle is used for photolithography. After development, ni with a thickness of 300nm was evaporated and stripped off as a mask for ion implantation. And then carrying out second terminal ion implantation by using a high-energy ion implanter, wherein the doping is distributed in a box shape. The second junction termination extension 104 is formed by a second termination ion implantation, the second junction termination extension 104 having a width of 200 μm and a depth of 0.4 μm and a doping concentration of about 1/8 of the main junction concentration. In the present embodiment, the doping concentration is 1.2E17cm -3 。
The overlapping portion of the first junction termination extension 103 and the second junction termination extension 104 is formed as a first overlapping region 106, the width of the first overlapping region 106 is the same as the width of the first junction termination extension 103, and the doping concentration of the first overlapping region 106 is approximately equal to the sum of the doping concentrations of the first junction termination extension 103 and the second junction termination extension 104. The overlapping portion of the field stop ring 105 and the second junction termination extension 104 is formed as a second overlapping region 107, the width of the second overlapping region 107 is the same as the width of the field stop ring 105, and the doping concentration of the second overlapping region 107 is approximately equal to the sum of the doping concentrations of the second junction termination extension 104 and the field stop ring 105.
Next, in step S404, the passivation layer is oxidized and deposited.
Specifically, after step S403 is completed, HNO is reused 3 And removing the metal and silicon dioxide remained on the surface of the SiC material in the step S402 by using the HCl 3:1 mixed solution, the concentrated sulfuric acid hydrogen peroxide 3:1 mixed solution and the BOE solution.
The entire SiC surface was then placed in an oxidation oven for dry oxygen oxidation at 1250 ℃ and wet oxygen oxidation at 950 ℃ followed by Ar in situ annealing and NO annealing. This forms an oxide layer of about 50nm on the device surface. During subsequent gate oxide etching, gate electrode etching, ohmic contact preparation, etc., the oxide layer above the termination region is carefully maintained throughout until about 1.2 μm of SiO is deposited at the surface by PECVD 2 Passivation layer and etching forms passivation layer 108.
The above embodiment describes forming the first junction termination extension 103 and the field stop ring 105 by the first termination ion implantation and forming the second junction termination extension 104 by the second termination ion implantation, but the two steps may be reversed, that is, the second junction termination extension 104 may be formed by the first termination ion implantation and the first junction termination extension 103 and the field stop ring 105 may be formed by the second termination ion implantation.
The foregoing describes preferred embodiments of the invention, but the spirit and scope of the invention is not limited to the specific disclosure herein. Those skilled in the art can devise many more embodiments and applications that, by way of their teachings, are still within the spirit and scope of this invention. The spirit and scope of the present invention are not limited by the specific embodiments, but by the appended claims.
Claims (6)
1. A composite termination structure for a silicon carbide semiconductor power device, comprising:
a first junction termination extension;
a second junction termination extension;
a field limiting ring;
a first overlap region formed by an overlap portion of the first junction termination extension and the second junction termination extension; and
a second overlap region formed by an overlap portion of the field limiting ring and the second junction termination extension;
the first junction termination extension has a width shorter than a width of the second junction termination extension, and the first junction termination extension has a depth deeper than a depth of the second junction termination extension;
the field limiting ring and the first junction terminal extension are formed simultaneously, and the field limiting ring and the first junction terminal extension have the same doping concentration and depth;
the width of the first superposition area is the same as the width of the first junction terminal extension, and the doping concentration of the first superposition area is equal to the sum of the doping concentrations of the first junction terminal extension and the second junction terminal extension; the width of the second recombination region is the same as the width of the field limiting ring, and the doping concentration of the second recombination region is equal to the sum of the doping concentration of the second junction termination extension and the field limiting ring.
2. The composite termination structure for a silicon carbide semiconductor power device as claimed in claim 1, wherein,
the composite terminal structure and the main junction are formed on the epitaxial wafer, and the composite terminal structure is directly connected with the main junction and has the same doping type as the main junction.
3. The composite termination structure for a silicon carbide semiconductor power device as claimed in claim 2, wherein,
the depth of the first junction terminal extension and the depth of the field limiting ring are larger than the depth of the main junction, and the depth of the second junction terminal extension is smaller than the depth of the main junction.
4. The preparation method of the composite terminal structure for the silicon carbide semiconductor power device is characterized by comprising the following steps of:
depositing a protective layer;
first terminal ion implantation;
a second terminal ion implantation;
oxidizing and depositing a passivation layer;
simultaneously forming a first junction terminal extension and a field limiting ring through first terminal ion implantation, wherein the field limiting ring and the first junction terminal extension have the same doping concentration and depth;
forming a second junction termination extension by a second termination ion implantation, the first junction termination extension having a width shorter than a width of the second junction termination extension, the first junction termination extension having a depth deeper than a depth of the second junction termination extension;
the overlapping portion of the first junction terminal extension and the second junction terminal extension is formed as a first overlapping region, the width of the first overlapping region is the same as the width of the first junction terminal extension, the doping concentration of the first overlapping region is equal to the sum of the doping concentrations of the first junction terminal extension and the second junction terminal extension, the overlapping portion of the field limiting ring and the second junction terminal extension is formed as a second overlapping region, the width of the second overlapping region is the same as the width of the field limiting ring, and the doping concentration of the second overlapping region is equal to the sum of the doping concentrations of the second junction terminal extension and the field limiting ring.
5. The method for fabricating a composite termination structure for a silicon carbide semiconductor power device as claimed in claim 4, wherein,
alternatively, a second junction termination extension is formed by a first termination ion implantation.
6. The method for fabricating a composite termination structure for a silicon carbide semiconductor power device as claimed in claim 5, wherein,
and simultaneously forming a first junction terminal extension and a field limiting ring through a second terminal ion implantation, wherein the field limiting ring and the first junction terminal extension have the same doping concentration and depth, the width of the first junction terminal extension is shorter than that of the second junction terminal extension, and the depth of the first junction terminal extension is deeper than that of the second junction terminal extension.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2958452A1 (en) * | 2010-03-30 | 2011-10-07 | Alstom Transport Sa | Semiconductor device i.e. high voltage power component, has rings arranged adjacent to surface of substrate, where cumulative dose of impurities in rings is lower than or equal to cumulative dose of impurities in epitaxial layer |
| CN102479807A (en) * | 2010-11-26 | 2012-05-30 | 三菱电机株式会社 | Silicon carbide semiconductor device and manufacturing method therefor |
| CN105304688A (en) * | 2015-11-04 | 2016-02-03 | 中国工程物理研究院电子工程研究所 | Junction termination structure for silicon carbide power device and fabrication method |
| CN106098751A (en) * | 2016-07-14 | 2016-11-09 | 电子科技大学 | A kind of power semiconductor terminal structure |
| WO2016194216A1 (en) * | 2015-06-05 | 2016-12-08 | 株式会社日立製作所 | Semiconductor device, method for manufacturing same, and power module |
| CN106252385A (en) * | 2015-06-05 | 2016-12-21 | 黄智方 | Semiconductor structure |
| CN207009439U (en) * | 2017-07-07 | 2018-02-13 | 泰科天润半导体科技（北京）有限公司 | Composite terminal structure for SiC semiconductor power device |
-
2017
- 2017-07-07 CN CN201710551757.3A patent/CN107275391B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2958452A1 (en) * | 2010-03-30 | 2011-10-07 | Alstom Transport Sa | Semiconductor device i.e. high voltage power component, has rings arranged adjacent to surface of substrate, where cumulative dose of impurities in rings is lower than or equal to cumulative dose of impurities in epitaxial layer |
| CN102479807A (en) * | 2010-11-26 | 2012-05-30 | 三菱电机株式会社 | Silicon carbide semiconductor device and manufacturing method therefor |
| WO2016194216A1 (en) * | 2015-06-05 | 2016-12-08 | 株式会社日立製作所 | Semiconductor device, method for manufacturing same, and power module |
| CN106252385A (en) * | 2015-06-05 | 2016-12-21 | 黄智方 | Semiconductor structure |
| CN105304688A (en) * | 2015-11-04 | 2016-02-03 | 中国工程物理研究院电子工程研究所 | Junction termination structure for silicon carbide power device and fabrication method |
| CN106098751A (en) * | 2016-07-14 | 2016-11-09 | 电子科技大学 | A kind of power semiconductor terminal structure |
| CN207009439U (en) * | 2017-07-07 | 2018-02-13 | 泰科天润半导体科技（北京）有限公司 | Composite terminal structure for SiC semiconductor power device |
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