CN116936620A - Preparation method of silicon carbide trench gate MOSFET - Google Patents

Preparation method of silicon carbide trench gate MOSFET Download PDF

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Publication number
CN116936620A
CN116936620A CN202311182072.8A CN202311182072A CN116936620A CN 116936620 A CN116936620 A CN 116936620A CN 202311182072 A CN202311182072 A CN 202311182072A CN 116936620 A CN116936620 A CN 116936620A
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silicon carbide
mosfet
well
gate
type
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胡舜涛
刘桂新
李防化
顾海彬
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Lingrui Semiconductor Shanghai Co ltd
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Lingrui Semiconductor Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

The invention belongs to the technical field of semiconductors, and discloses a preparation method of a silicon carbide trench gate MOSFET. The invention takes the P-type epitaxy as the P-well of the MOSFET, omits high-temperature aluminum injection of the P-well of the traditional method, and saves the high-temperature ion injection productivity. The P-type epitaxy is used as a deep P well for protecting gate oxide at the bottom of the groove, and the depth of the deep P well is determined by the thickness of the P-type epitaxy, so that the limit of the capability of the traditional high-temperature high-energy injection equipment is broken through. The thickness of the epitaxy is increased, so that the depth of the deep P well is increased, the electric field intensity at the bottom of the groove is effectively reduced, the gate oxide at the bottom of the groove is protected, and the reliability of the gate oxide is improved.

Description

Preparation method of silicon carbide trench gate MOSFET
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a silicon carbide trench gate MOSFET.
Background
Silicon carbide (SiC) based wide bandgap semiconductors are becoming increasingly popular in the marketplace due to their low on-loss, excellent high temperature resistance and high thermal conductivity characteristics. In addition, silicon carbide also has unique electrical properties such as high critical field, high bulk mobility, high saturation velocity and the like, and particularly has high critical field characteristics, so that compared with a conventional silicon device under the same voltage, the silicon carbide power device can have higher doping concentration and thinner drift layer thickness, thereby realizing lower on-resistance. The Metal-Oxide-semiconductor field effect transistor (MOSFET) has lower switching loss and higher operating frequency, and is very suitable for the application demands of power electronics.
However, in the conventional silicon carbide trench gate MOSFET fabrication process, the formation of the P-well of the MOSFET requires high temperature implantation of P-type (aluminum ions). Meanwhile, in order to reduce the electric field of the gate oxide layer at the bottom of the trench gate, a deep P-well is formed at 0.4-1 μm below the bottom of the trench gate, and high energy (mev) and high temperature P-type (aluminum ion) implantation are required. The two steps of process steps require the silicon carbide wafer to be heated to the high temperature of about 500 ℃ for the injection equipment, so that the high-temperature high-energy injection equipment can only rely on import at present, meanwhile, the productivity of the equipment is reduced, the energy consumption is higher, the production cost is higher, and further popularization of the silicon carbide device in power electronics is prevented. Meanwhile, in the process of forming the deep P well, the high-energy ion implantation can only reach 2-3MeV at present, and the depth of the deep P well is limited by the energy of the ion implanter equipment.
In the conventional process of injecting P-type aluminum ions at high temperature, various defects can be generated on the silicon carbide wafer substrate, so that high-voltage leakage of the silicon carbide is increased, and the defects can reduce channel electron mobility of the MOSFET. In a P well formed by high-temperature ion implantation of a traditional silicon carbide MOSFET, the channel electron mobility is 20cm 2 And/v.s, is 2.5% of the bulk mobility.
Therefore, how to provide a method for manufacturing a silicon carbide trench gate MOSFET is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In order to overcome the defects and shortcomings in the prior art, the invention provides a preparation method of a silicon carbide trench gate MOSFET, wherein a P-type epitaxy is used as a P-well of the MOSFET, so that high-temperature aluminum injection of the P-well in the traditional method is omitted, and the high-temperature ion injection productivity is saved; the P-type epitaxial layer has no defect generated by high-temperature high-energy injection, MOSFET (metal-oxide-semiconductor field effect transistor) has small electric leakage, large channel mobility of electrons and increased quality reliability; the process steps are simplified, and the process cost is saved.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
a preparation method of a silicon carbide trench gate MOSFET comprises the following steps:
(1) Growing a layer of N-type epitaxy on the N-type substrate to serve as a voltage-resistant drift region; growing a layer of P-type epitaxy on the N-type epitaxy, and taking the P-type epitaxy as a P well and a deep P well of the MOSFET;
(2) Photoetching to form an active region; ion implantation of N+ type in the active region to dope as N+ source;
(3) Depositing dielectric as a mask, photoetching and etching the mask; implanting aluminum ions to form P+ as contact doping of the P well and forming a body diode;
(4) Depositing a dielectric layer on the film to serve as a trench etching mask layer; etching the silicon carbide layer to form a groove;
(5) Nitrogen ions are injected into the bottom of the groove for many times at normal temperature, and an N-type doped region is formed at the bottom of the groove to form an electronic path of the MOSFET;
(6) High-temperature annealing, and activating doping ions;
(7) Growing a gate oxide layer at a high temperature to serve as a gate dielectric of the MOSFET;
(8) Depositing a polysilicon gate, photoetching and etching polysilicon to serve as a gate electrode of the MOSFET;
(9) Depositing a dielectric layer as a dielectric layer between the grid electrode and the source electrode;
(10) Photoetching and etching the dielectric layer in the step (9) to serve as a source metal contact hole of the silicon carbide trench gate MOSFET;
(11) And depositing metal to serve as source metal of the silicon carbide trench gate MOSFET to obtain the silicon carbide trench gate MOSFET.
Preferably, the thickness of the P-type epitaxy in the step (1) is 0.5-2 μm, and the concentration is 2×10 16 ~ 1×10 18 cm -3 。
The beneficial effects of the technical scheme are as follows: the P-type epitaxy serves as a P-well of the MOSFET and a deep P-well for protecting gate oxide at the bottom of the trench, and the formed P/N junction needs to have a certain distance at the bottom of the trench, so that the strong electric field in the silicon carbide falls to a safe value before reaching the bottom of the trench. If the P-type epitaxial thickness is too small, the electric field in the silicon carbide is too large at the bottom of the trench, and the reliability of gate oxide is reduced. Through the growth of the P-type epitaxy, the P-well of the MOSFET and the deep P-well at the bottom of the groove are completed at one time, the working procedures are saved, and particularly, the high-temperature high-energy injection working procedure which has strict requirements on injection equipment is omitted.
Preferably, the depth of the n+ type in the step (2) is 0.2-0.8 μm.
The beneficial effects of the technical scheme are as follows: the carpet type implantation in the active area and the active area AA photoetching are combined into one step, so that the steps of photoetching, mask deposition, mask etching and the like of N+ type implantation in the traditional process are omitted.
Preferably, the number of times of implanting nitrogen ions in the step (5) is 3 to 6, and the dose of each implantation is 1×10 13 ~3×10 13 cm -3 。
The beneficial effects of the technical scheme are as follows: and implanting nitrogen ions to enable the P-type epitaxy inversion to be N-type, and forming an electron channel with the JFET region of the conventional planar MOSFET.
Preferably, the temperature of the high-temperature annealing in the step (6) is 1600-1850 ℃.
Compared with the prior art, the invention provides a preparation method of the silicon carbide trench gate MOSFET, which has the following beneficial effects:
(1) The invention takes the P-type epitaxy as the P-well of the MOSFET, omits high-temperature aluminum injection of the P-well of the traditional method, and saves the high-temperature ion injection productivity.
(2) The P-type epitaxy is used as a deep P well for protecting gate oxide at the bottom of the groove, and the depth of the deep P well is determined by the thickness of the P-type epitaxy, so that the limit of the capability of the traditional high-temperature high-energy injection equipment is broken through. The thickness of the epitaxy is increased, so that the depth of the deep P well is increased, the electric field intensity at the bottom of the groove is effectively reduced, the gate oxide at the bottom of the groove is protected, and the reliability of the gate oxide is improved.
(3) The strong electric field is positioned at the bottom of the P-type epitaxy, so that the bottom of the trench gate shields the strong electric field, and the problem of gate oxide reliability which plagues the MOSFET is effectively solved.
(4) The P-type epitaxial layer has no defect generated by high-temperature high-energy injection, the metal oxide semiconductor field effect transistor has small leakage, the quality reliability is improved, the channel electron mobility is increased, and the conduction loss is reduced.
(5) The production process of the MOSFET is simplified, the two steps of high-temperature injection to form the P well and high-temperature high-energy particle injection to form the deep P well are omitted, and a plurality of corresponding process steps of photoetching, anti-blocking masks and the like are omitted, so that the steps are simplified, the productivity is improved, and the cost is saved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of the formation of an N-type drift region epitaxy and a P-type epitaxy through step (1) of the present invention.
Fig. 2 is a schematic diagram of the present invention after step (2) of ion implantation of n+ type into the active region to form n+ source doping.
Fig. 3 is a schematic diagram of the present invention after step (3), the p+ is implanted after photolithography as a contact doping for the P-well, and a body diode is formed.
FIG. 4 is a schematic diagram of the trench formation in step (4) of the present invention.
Fig. 5 is a schematic diagram of the electronic path of the MOSFET of the present invention after step (5).
Fig. 6 is a schematic diagram of the present invention after step (7) to grow a gate oxide layer in the trench.
Fig. 7 is a schematic diagram of the present invention after step (8) of depositing a polysilicon gate, photolithography, and etching polysilicon as the gate electrode of the MOSFET.
Fig. 8 is a schematic diagram of the present invention after step (10) of photolithography and etching of the dielectric layer as the source metal contact hole of the silicon carbide trench gate MOSFET.
Fig. 9 is a schematic structural diagram of the final silicon carbide trench-gate MOSFET after step (11) according to the present invention.
Fig. 10 is a reverse withstand voltage curve of the silicon carbide trench gate MOSFET of example 1.
Fig. 11 is a forward output characteristic of the silicon carbide trench gate MOSFET of example 1.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
A preparation method of a silicon carbide trench gate MOSFET comprises the following steps:
(1) Growing a layer of N-type epitaxy on the N-type substrate to serve as a voltage-resistant drift region; growing a layer of P-type epitaxy on the N-type epitaxy, and taking the P-type epitaxy as a P well and a deep P well of the MOSFET;
(2) Photoetching to form an active region; ion implantation of N+ type in the active region to dope as N+ source;
(3) Depositing dielectric as a mask, photoetching and etching the mask; implanting aluminum ions to form P+ as contact doping of the P well and forming a body diode;
(4) Depositing a dielectric layer on the film to serve as a trench etching mask layer; etching the silicon carbide layer to form a groove;
(5) Nitrogen ions are injected into the bottom of the groove for many times at normal temperature, and an N-type doped region is formed at the bottom of the groove to form an electronic path of the MOSFET;
(6) High-temperature annealing, and activating doping ions;
(7) Growing a gate oxide layer at a high temperature to serve as a gate dielectric of the MOSFET;
(8) Depositing a polysilicon gate, photoetching and etching polysilicon to serve as a gate electrode of the MOSFET;
(9) Depositing a dielectric layer as a dielectric layer between the grid electrode and the source electrode;
(10) Photoetching and etching the dielectric layer in the step (9) to serve as a source metal contact hole of the silicon carbide trench gate MOSFET;
(11) And depositing metal to serve as source metal of the silicon carbide trench gate MOSFET to obtain the silicon carbide trench gate MOSFET.
Preferably, the thickness of the P-type epitaxy in step (1) is 1.4 μm and the concentration is 2×10 17 cm -3 。
Preferably, the depth of the n+ type in step (2) is 0.3 μm.
Preferably, the number of times of implanting nitrogen ions in the step (5) is 6, and the dose of each implantation is 1×10 13 ~3×10 13 cm -3 。
Preferably, the temperature of the high temperature annealing in step (6) is 1800 ℃.
Fig. 10 is a reverse withstand voltage curve of the silicon carbide trench gate MOSFET of example 1. Compared with the traditional planar silicon carbide MOSFET, the voltage withstand voltage of the invention reaches 1900V, and 100V-150V is improved.
Fig. 11 is a forward output characteristic of the silicon carbide trench gate MOSFET of example 1. The forward on-resistance of the 10 mm square device is reduced to 16 milliohms, which is 40% lower than the conventional planar silicon carbide MOSFET loss.
For a silicon carbide trench gate MOSFET of the traditional technology, the capacity of one high-temperature ion implanter is about 400 pieces/month, which is one half of that of a silicon carbide plane MOSFET. The invention omits the traditional process of forming the P well and the deep P well by high-temperature aluminum ion implantation, saves 30% of wafer processing cost, and increases the productivity by up to 40%.
Meanwhile, the P-type epitaxial structure replaces a P-well formed by injecting high-temperature aluminum ions, so that the channel electron mobility of the silicon carbide trench gate MOSFET can be theoretically improved by 30% -200%.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the solution disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. The preparation method of the silicon carbide trench gate MOSFET is characterized by comprising the following steps of:
(1) Growing a layer of N-type epitaxy on the N-type substrate to serve as a voltage-resistant drift region; growing a layer of P-type epitaxy on the N-type epitaxy, and taking the P-type epitaxy as a P well and a deep P well of the MOSFET;
(2) Photoetching to form an active region; ion implantation of N+ type in the active region to dope as N+ source;
(3) Depositing dielectric as a mask, photoetching and etching the mask; implanting aluminum ions to form P+ as contact doping of the P well and forming a body diode;
(4) Depositing a dielectric layer on the film to serve as a trench etching mask layer; etching the silicon carbide layer to form a groove;
(5) Nitrogen ions are injected into the bottom of the groove for many times at normal temperature, and an N-type doped region is formed at the bottom of the groove to form an electronic path of the MOSFET;
(6) High-temperature annealing, and activating doping ions;
(7) Growing a gate oxide layer at a high temperature to serve as a gate dielectric of the MOSFET;
(8) Depositing a polysilicon gate, photoetching and etching polysilicon to serve as a gate electrode of the MOSFET;
(9) Depositing a dielectric layer as a dielectric layer between the grid electrode and the source electrode;
(10) Photoetching and etching the dielectric layer in the step (9) to serve as a source metal contact hole of the silicon carbide trench gate MOSFET;
(11) And depositing metal to serve as source metal of the silicon carbide trench gate MOSFET to obtain the silicon carbide trench gate MOSFET.
2. The method for fabricating a silicon carbide trench-gate MOSFET according to claim 1, wherein the thickness of the P-type epitaxy in step (1) is 0.5-2 μm, and the concentration is 1×10 15 ~1×10 18 cm -3 。
3. The method for manufacturing a silicon carbide trench-gate MOSFET according to claim 1, wherein the depth of the N+ type in the step (2) is 0.2-0.8 μm.
4. The method of claim 1, wherein the number of nitrogen ions implanted in step (5) is 3-6, and the dose of each implantation is 1×10 13 ~3×10 13 cm -3 。
5. The method for manufacturing a silicon carbide trench-gate MOSFET according to claim 1, wherein the high-temperature annealing in step (6) is performed at a temperature of 1600-1850 ℃.
CN202311182072.8A 2023-09-14 2023-09-14 Preparation method of silicon carbide trench gate MOSFET Pending CN116936620A (en)

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US20010003367A1 (en) * 1998-06-12 2001-06-14 Fwu-Iuan Hshieh Trenched dmos device with low gate charges
JP2004342863A (en) * 2003-05-16 2004-12-02 Shindengen Electric Mfg Co Ltd Semiconductor device
US20140217422A1 (en) * 2012-03-30 2014-08-07 Hitachi, Ltd. Field effect silicon carbide transistor
CN105474403A (en) * 2013-08-08 2016-04-06 富士电机株式会社 High-withstand-voltage semiconductor device, and production method therefor
US20180204905A1 (en) * 2017-01-16 2018-07-19 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US20190027598A1 (en) * 2016-02-05 2019-01-24 Denso Corporation Semiconductor device and circuit having the same
CN113178384A (en) * 2021-06-30 2021-07-27 中芯集成电路制造(绍兴)有限公司 SiC-based ohmic contact structure and method for manufacturing same
US20210296447A1 (en) * 2020-03-19 2021-09-23 Kabushiki Kaisha Toshiba Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator
US20230130726A1 (en) * 2021-10-25 2023-04-27 Zju-hangzhou Global Scientific And Technological Innovation Center Silicon Carbide Trench Gate MOSFET and Method for Manufacturing Thereof

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010003367A1 (en) * 1998-06-12 2001-06-14 Fwu-Iuan Hshieh Trenched dmos device with low gate charges
JP2004342863A (en) * 2003-05-16 2004-12-02 Shindengen Electric Mfg Co Ltd Semiconductor device
US20140217422A1 (en) * 2012-03-30 2014-08-07 Hitachi, Ltd. Field effect silicon carbide transistor
CN105474403A (en) * 2013-08-08 2016-04-06 富士电机株式会社 High-withstand-voltage semiconductor device, and production method therefor
US20190027598A1 (en) * 2016-02-05 2019-01-24 Denso Corporation Semiconductor device and circuit having the same
US20180204905A1 (en) * 2017-01-16 2018-07-19 Fuji Electric Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US20210296447A1 (en) * 2020-03-19 2021-09-23 Kabushiki Kaisha Toshiba Semiconductor device, method of manufacturing semiconductor device, inverter circuit, drive device, vehicle, and elevator
CN113178384A (en) * 2021-06-30 2021-07-27 中芯集成电路制造(绍兴)有限公司 SiC-based ohmic contact structure and method for manufacturing same
US20230130726A1 (en) * 2021-10-25 2023-04-27 Zju-hangzhou Global Scientific And Technological Innovation Center Silicon Carbide Trench Gate MOSFET and Method for Manufacturing Thereof

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