CN112349771A - Buried layer type terminal structure of silicon carbide device and preparation method thereof - Google Patents

Buried layer type terminal structure of silicon carbide device and preparation method thereof Download PDF

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CN112349771A
CN112349771A CN202011059252.3A CN202011059252A CN112349771A CN 112349771 A CN112349771 A CN 112349771A CN 202011059252 A CN202011059252 A CN 202011059252A CN 112349771 A CN112349771 A CN 112349771A
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buried
dose
ion implantation
implantation
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王俊
俞恒裕
梁世维
刘航志
江希
彭子舜
岳伟
杨余
张倩
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Hunan University
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Abstract

The invention discloses a buried layer type terminal structure of a silicon carbide device, which comprises a device cell and a buried layer type multi-modulation-ring terminal, wherein the device cell comprises: an N + SiC substrate; a P buffer layer on the N + SiC substrate; a P-drift region on the P buffer layer; the N base region is positioned on the P-drift region, ion implantation is carried out on the N base region to form a gate electrode region, and the P + anode region is positioned on the N base region; the depth d between the embedded multi-modulation-ring terminal and the upper surface of the P-drift region is not less than 0.3 um. The invention also discloses a preparation method of the buried layer type terminal structure of the silicon carbide device. The invention can effectively relieve SiO on the upper surface of the drift region2The influence of fixed charges in the SiC interface region on the terminal structure can fully exert the effect of the terminal structure, relieve the electric field concentration at the main junction and improve the voltage endurance capability of the device.

Description

Buried layer type terminal structure of silicon carbide device and preparation method thereof
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a buried layer type terminal structure of a silicon carbide device and a preparation method thereof.
Background
With the continuous development of power electronic technology, the status of power semiconductor devices as core components is continuously highlighted, and the power semiconductor devices are widely applied to motor driving, new energy power generation, smart grids, new energy automobiles and the like. The voltage resistance of the semiconductor power device is extremely important, and the blocking capability of the device can be fully improved by optimally designing the terminal structure of the power semiconductor device from the aspect of device design.
In the actual PN junction process, since the diffusion of the dopant ions is isotropic, the impurity ions are diffused not only in the longitudinal direction but also in the lateral direction. Therefore, a spherical junction is formed below the diffusion window, and the curvature of the spherical junction has a great influence on the breakdown characteristic of the PN junction. In the voltage-resistant stage of the device, the electric field intensity along with the distance change is more concentrated at the junction surface bending part, and when the ideal voltage resistance is not achieved, the electric field at the junction surface bending part reaches the breakdown electric field of the semiconductor material. The purpose of the terminal structure of the power semiconductor device is to relieve the electric field intensity at the edge of a cell, so that a depletion region is expanded to the outside, and the electric field concentration at a main junction is greatly reduced. Currently, commonly used terminals include: the field plate structure, the equidistant or variable-pitch field limiting ring structure, the field limiting ring combined with the field plate, the junction terminal extending terminal structure and the like.
At present, all terminal structures are affected by fixed charges in a silicon dioxide oxide layer on the surface of a terminal, and the distribution of electric fields in the terminal structures is changed due to the existence of the fixed charges, so that the performance of the optimized terminal structure at the early stage is greatly reduced, and the phenomenon is more serious on a silicon carbide device. Therefore, a terminal structure of a silicon carbide device and a preparation method thereof are urgently needed, and on the basis of realization of the current domestic process, the terminal structure of the silicon carbide device gives full play to the material advantages of the silicon carbide as much as possible, improves the voltage resistance of the device, and has higher tolerance on surface oxide layer charges.
Disclosure of Invention
The invention aims to solve the problems, and provides a buried layer type terminal structure of a silicon carbide device and a preparation method thereof, which can avoid the influence of surface charges, can greatly improve the performance of a terminal by combining the conventional terminal structure, is compatible with the conventional manufacturing process and reduces the manufacturing cost.
In order to realize the purpose, the invention adopts the technical scheme that:
a buried layer type terminal structure of a silicon carbide device comprises a device cell and a buried layer type terminal, wherein the device cell comprises: an N + SiC substrate; a P buffer layer on the N + SiC substrate; a P-drift region on the P buffer layer; the N base region is positioned on the P-drift region, ion implantation is carried out on the N base region to form a gate electrode region, and the P + anode region is positioned on the N base region; the depth d between the buried layer type terminal and the upper surface of the P-drift region is not less than 0.3 um.
Furthermore, the buried layer type terminal comprises a mesa etching terminal extension structure and a buried layer type junction terminal extension structure formed by an ion implantation process.
Furthermore, the depth d of the extending structure of the buried junction terminal from the upper surface of the P-drift region is not less than 0.3 um.
Further, the buried junction termination extension structure comprises a JTE1 dose region and a JTE2 dose region, wherein the JTE2 dose region is partially overlapped on the JTE1 dose region to form a buried multi-ring modulation JTE or a buried three-region JTE; and the JTE2 dose regions are completely overlapped to form a buried layer type field limiting ring JTE or a buried layer type guard ring auxiliary JTE on the JTE1 dose region.
Furthermore, the mesa etching terminal extension structure comprises an etching mesa formed in the N base region and an etching plane etched from the N base region to the P-drift region.
A method for preparing a buried layer type terminal structure of a silicon carbide device,
(1) cleaning the silicon carbide epitaxial wafer;
(2) depositing a SiO2 oxide layer on the epitaxial wafer, and etching to form an anode table top;
(3) etching a gate electrode mesa;
(4) performing ion implantation in the gate region to form a high-concentration region for forming ohmic contact, and performing high-temperature annealing treatment to activate ions;
(5) preparing a buried layer type terminal;
i) etching the mesa from the N base region to the P-drift region to finally form a mesa etching terminal extension structure (8);
ii) carrying out first ion implantation on the P-drift region, wherein the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, and the distance d between the ion implantation depth and the upper surface is not less than 0.3 um;
iii) carrying out second ion implantation on the P-drift region, wherein the second ion implantation depth is consistent with the first ion implantation depth, and finally forming a buried junction terminal extension structure;
iV) annealing process treatment;
(6) passivating the upper surface of the epitaxial wafer to form two oxide layers;
(7) etching an anode contact area, sputtering metal on the surface of the anode contact area, and annealing to form P + ohmic contact and ohmic contact of an N + gate area;
(8) then passivation and etching are carried out to form a contact window sputtering aluminum metal; and then forming a cathode ohmic contact on the lower surface of the epitaxial wafer.
Further, in the step 3, the gate electrode mesa is repeatedly etched, and the etching depth is determined through the probe.
Further, step 4 is to implant nitrogen ions into the gate region to form a high concentration region for forming ohmic contacts, and then to activate the nitrogen ions by high temperature annealing.
Furthermore, the buried-layer type junction terminal extension structure adopts two-step ion implantation, and the dosage of the first step ion implantation is 4e12cm-2-1.8e13cm-2The second step implantation dose is 2e12cm-2-9e12cm-2The energy and the dose of the four times of implantation in the first step of ion implantation are sequentially decreased progressively, and the energy and the dose of the four times of implantation in the second step of ion implantation are sequentially decreased progressively.
Furthermore, the ion implantation part in the first step is a JTE1 dose region, the ion implantation part in the second step is a JTE2 dose region, and the overlapping part of the JTE2 dose region and the JTE1 dose region forms a JTE1+ JTE2 dose staggered region.
The invention has the beneficial effects that:
the invention pushes the existing terminal structure formed by an ion implantation mode to a position with a certain distance from the lower surface of the drift region to form a buried layer structure, thereby completely avoiding the influence of fixed charges in the upper surface region of the drift region on the terminal structure, fully playing the effect of the terminal structure, relieving the electric field concentration at the main junction and improving the voltage endurance capability of the device. The method has no special process requirement, does not increase the difficulty of the process, and can well improve the reliability and stability of the device.
Drawings
FIG. 1 is a schematic diagram of a buried multi-ring modulated JTE structure according to the present invention;
FIG. 2 is a process diagram of the present invention for preparing buried multi-ring modulated JTE
FIG. 3 is a diagram of the electric field distribution of the buried multi-ring modulated JTE of the present invention;
FIG. 4 is a diagram of electrostatic potential distribution of buried multi-ring modulated JTE according to the present invention;
FIG. 5 shows the JTE of different SiO for buried multi-ring modulation of the present invention2Electric field distribution diagram under the influence of fixed charges on the/SiC interface;
FIG. 6 shows the difference between the present invention and conventional JTE on SiO2A schematic diagram of blocking voltage resistance under fixed charges of a/SiC interface;
FIG. 7 is a schematic diagram of a buried-layer type three-region JTE structure according to the present invention;
FIG. 8 is a schematic diagram of a buried guard ring-assisted JTE structure according to the present invention;
fig. 9 is a schematic structural diagram of a buried layer type field limiting ring JTE according to the present invention.
Detailed Description
The following detailed description of the present invention is given for the purpose of better understanding technical solutions of the present invention by those skilled in the art, and the present description is only exemplary and explanatory and should not be construed as limiting the scope of the present invention in any way.
Example 1
As shown in fig. 1, a buried layer type terminal structure of a silicon carbide device includes a device cell and a buried layer type terminal, the device cell includes: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.3 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.3um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 partially overlaps the JTE1 dose region 92 to form a buried multi-ring modulated JTE.
As shown in fig. 2, a method for preparing a buried terminal structure of a silicon carbide device,
a method for preparing a buried layer type terminal structure of a silicon carbide device,
(1) cleaning the silicon carbide epitaxial wafer;
(2) depositing a SiO2 oxide layer on the epitaxial wafer, and etching to form an anode table top;
(3) etching a gate electrode mesa;
(4) performing ion implantation in the gate region to form a high-concentration region for forming ohmic contact, and performing high-temperature annealing treatment to activate ions;
(5) preparing a buried layer type terminal;
i) etching the mesa from the N base region to the P-drift region to finally form a mesa etching terminal extension structure 8;
ii) carrying out first ion implantation on the P-drift region, wherein the ion region is divided into four times of different implantation energies and implantation doses to form a uniformly distributed region, and the distance d =0.3um between the ion implantation depth and the upper surface;
iii) carrying out second ion implantation on the P-drift region, wherein the second ion implantation depth is consistent with the first ion implantation depth, and finally forming a buried junction terminal extension structure 9, the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, the first implantation dose is twice of the second implantation dose, and the implantation energies are consistent;
iV) annealing process treatment;
(6) passivating the upper surface of the epitaxial wafer to form two oxide layers;
(7) etching an anode contact area, sputtering metal on the surface of the anode contact area, and annealing to form P + ohmic contact and ohmic contact of an N + gate area;
(8) then passivation and etching are carried out to form a contact window sputtering aluminum metal; and then forming a cathode ohmic contact on the lower surface of the epitaxial wafer.
In this embodiment, the gate mesa is repeatedly etched in step 3, and the etching depth is determined by the probe; and 4, performing nitrogen ion implantation in the gate electrode region to form a high-concentration region so as to form ohmic contact, and then activating nitrogen ions by high-temperature annealing.
In this embodiment, the first step of ion implantation is a JTE1 dose region 92, the second step of ion implantation is a JTE2 dose region 93, the overlap of the JTE2 dose region 93 and the JTE1 dose region 92 forms a JTE1+ JTE2 dose interleaved region 91, wherein the JTE1 dose region 92 is connected to the mesa etch termination extension structure 8, a plurality of JTE1+ JTE2 dose interleaved regions 91 are disposed alternately in the JTE1 dose region 92, and the JTE2 dose region 93 is connected to the JTE1 dose region 92 to form a buried multi-ring modulation JTE.
In this embodiment, the buried multi-modulation loop junction termination extension structure adopts two-step ion implantation, and the first step ion implantation dosage is 4e12cm-2The second step implantation dose is 2e12cm-2The energy and the dose of the four times of implantation in the first step of ion implantation are sequentially decreased progressively, and the energy and the dose of the four times of implantation in the second step of ion implantation are sequentially decreased progressively.
As shown in fig. 3 and 4, the electrostatic potential distribution and the electric field distribution in the blocking state decrease uniformly and slowly with the increasing depth, the electric field distribution tends to be gentle when the depth is 0.3um, the maximum electric field is about 1.6MV/cm, the voltage endurance of the terminal is improved, and the stability and the reliability of the terminal are higher.
Example 2
A buried layer type terminal structure of a silicon carbide device comprises a device cell and a buried layer type terminal, wherein the device cell comprises: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.5 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.5um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 partially overlaps the JTE1 dose region 92 to form a buried multi-ring modulated JTE.
A method for preparing a buried layer type terminal structure of a silicon carbide device,
(1) cleaning the silicon carbide epitaxial wafer;
(2) depositing a SiO2 oxide layer on the epitaxial wafer, and etching to form an anode table top;
(3) etching a gate electrode mesa;
(4) performing ion implantation in the gate region to form a high-concentration region for forming ohmic contact, and performing high-temperature annealing treatment to activate ions;
(5) preparing a buried layer type terminal;
i) etching the mesa from the N base region to the P-drift region to finally form a mesa etching terminal extension structure 8;
ii) carrying out first ion implantation on the P-drift region, wherein the ion region is divided into four times of different implantation energies and implantation doses to form a uniformly distributed region, and the distance d =0.5um between the ion implantation depth and the upper surface;
iii) carrying out second ion implantation on the P-drift region, wherein the second ion implantation depth is consistent with the first ion implantation depth, and finally forming a buried junction terminal extension structure 9, the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, the first implantation dose is twice of the second implantation dose, and the implantation energies are consistent;
iV) annealing process treatment;
(6) passivating the upper surface of the epitaxial wafer to form two oxide layers;
(7) etching an anode contact area, sputtering metal on the surface of the anode contact area, and annealing to form P + ohmic contact and ohmic contact of an N + gate area;
(8) then passivation and etching are carried out to form a contact window sputtering aluminum metal; and then forming a cathode ohmic contact on the lower surface of the epitaxial wafer.
In this embodiment, the gate mesa is repeatedly etched in step 3, and the etching depth is determined by the probe; and 4, performing nitrogen ion implantation in the gate electrode region to form a high-concentration region so as to form ohmic contact, and then activating nitrogen ions by high-temperature annealing.
In this embodiment, the first step of ion implantation is a JTE1 dose region 92, the second step of ion implantation is a JTE2 dose region 93, the overlap of the JTE2 dose region 93 and the JTE1 dose region 92 forms a JTE1+ JTE2 dose interleaved region 91, wherein the JTE1 dose region 92 is connected to the mesa etch termination extension structure 8, a plurality of JTE1+ JTE2 dose interleaved regions 91 are disposed alternately in the JTE1 dose region 92, and the JTE2 dose region 93 is connected to the JTE1 dose region 92 to form a buried multi-ring modulation JTE.
As shown in fig. 3 and 4, the electrostatic potential distribution and the electric field distribution in the blocking state decrease uniformly and slowly with the increasing depth, the electric field distribution tends to be gentle when the depth is 0.3um, and the maximum electric field is about 1.6MV/cm when the depth is 0.5um, so that the voltage withstanding capability of the terminal is improved, and the stability and the reliability of the terminal are higher.
Example 3
A buried layer type terminal structure of a silicon carbide device comprises a device cell and a buried layer type terminal, wherein the device cell comprises: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.8 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.8um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 partially overlaps the JTE1 dose region 92 to form a buried multi-ring modulated JTE.
A method for preparing a buried layer type terminal structure of a silicon carbide device,
(1) cleaning the silicon carbide epitaxial wafer;
(2) depositing a SiO2 oxide layer on the epitaxial wafer, and etching to form an anode table top;
(3) etching a gate electrode mesa;
(4) performing ion implantation in the gate region to form a high-concentration region for forming ohmic contact, and performing high-temperature annealing treatment to activate ions;
(5) preparing a buried layer type terminal;
i) etching the mesa from the N base region to the P-drift region to finally form a mesa etching terminal extension structure 8;
ii) carrying out first ion implantation on the P-drift region, wherein the ion region is divided into four times of different implantation energies and implantation doses to form a uniformly distributed region, and the distance d =0.8um between the ion implantation depth and the upper surface;
iii) carrying out second ion implantation on the P-drift region, wherein the second ion implantation depth is consistent with the first ion implantation depth, and finally forming a buried junction terminal extension structure 9, the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, the first implantation dose is twice of the second implantation dose, and the implantation energies are consistent;
iV) annealing process treatment;
(6) passivating the upper surface of the epitaxial wafer to form two oxide layers;
(7) etching an anode contact area, sputtering metal on the surface of the anode contact area, and annealing to form P + ohmic contact and ohmic contact of an N + gate area;
(8) then passivation and etching are carried out to form a contact window sputtering aluminum metal; and then forming a cathode ohmic contact on the lower surface of the epitaxial wafer.
In this embodiment, the gate mesa is repeatedly etched in step 3, and the etching depth is determined by the probe; and 4, performing nitrogen ion implantation in the gate electrode region to form a high-concentration region so as to form ohmic contact, and then activating nitrogen ions by high-temperature annealing.
In this embodiment, the first step of ion implantation is a JTE1 dose region 92, the second step of ion implantation is a JTE2 dose region 93, the overlap of the JTE2 dose region 93 and the JTE1 dose region 92 forms a JTE1+ JTE2 dose interleaved region 91, wherein the JTE1 dose region 92 is connected to the mesa etch termination extension structure 8, a plurality of JTE1+ JTE2 dose interleaved regions 91 are disposed alternately in the JTE1 dose region 92, and the JTE2 dose region 93 is connected to the JTE1 dose region 92 to form a buried multi-ring modulation JTE.
As shown in fig. 3 and 4, the electrostatic potential distribution and the electric field distribution in the blocking state decrease uniformly and slowly with the increasing depth, the electric field distribution tends to be gentle when the depth is 0.3um, and the maximum electric field is about 1.6MV/cm when the depth is 0.8um, so that the voltage withstanding capability of the terminal is improved, and the stability and the reliability of the terminal are higher.
As shown in fig. 5, under the condition of different interface fixed charges, the electric field distribution at 4500V blocking voltage shows that the buried layer type terminal improves the stability of the terminal, and the peak electric field is greatly improved.
As shown in fig. 6, the maximum breakdown voltage at different interface fixed charge densities gradually decreases as the fixed charges increase, but the buried terminal structure has better stability and reliability compared with the conventional structure. The magnitude of the reduction of the maximum breakdown voltage is relatively small and the maximum breakdown voltage is significantly increased.
Example 4
As shown in fig. 7, a buried layer type terminal structure of a silicon carbide device includes a device cell and a buried layer type terminal, the device cell includes: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.6 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.6um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 partially overlaps the JTE1 dose region 92 to form a buried triple region JTE.
In the buried layer type tri-region JTE manufacturing step 5, the first step of ion implantation is referred to as JTE1 dose region 92, and the second step of ion implantation is referred to as JTE2 dose region 93, wherein the overlap of JTE2 dose region 93 and JTE1 dose region 92 forms JTE1+ JTE2 dose interleaved region 91.
As shown in fig. 7, the final structure is: JTE1+ JTE2 dose interleaved regions 91 are connected to junction termination extension structures 8 formed by a bevel etch process, JTE1 dose regions 92 are connected to JTE1+ JTE2 dose interleaved regions 91, and JTE2 dose regions 93 are connected to JTE1 dose regions 92.
As shown in fig. 6, the maximum breakdown voltage at different interface fixed charge densities gradually decreases as the fixed charges increase, but the buried terminal structure has better stability and reliability compared with the conventional structure. The magnitude of the reduction of the maximum breakdown voltage is relatively small and the maximum breakdown voltage is significantly increased.
Example 5
As shown in fig. 8, a buried layer type terminal structure of a silicon carbide device includes a device cell and a buried layer type terminal, the device cell includes: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.6 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.6um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 is completely overlapped with the JTE1 dose region 92 to form a buried guard ring-assisted JTE.
In the step 5, the first step of ion implantation is a JTE1 dose region 92, and the second step of ion implantation is a JTE2 dose region 93, wherein the JTE2 dose region 93 is entirely overlapped on the JTE1 dose region 92 to form a JTE1+ JTE2 dose interleaved region 91.
As shown in fig. 8, the final structure is: the JTE1 dose region 92 is connected to the junction termination extension structure 8 formed by the bevel etching process, and a plurality of JTE1+ JTE2 dose interleaving regions 91 are disposed in the JTE1 dose region 92 in an alternating manner.
As shown in fig. 6, the maximum breakdown voltage at different interface fixed charge densities gradually decreases as the fixed charges increase, but the buried terminal structure has better stability and reliability compared with the conventional structure. The magnitude of the reduction of the maximum breakdown voltage is relatively small and the maximum breakdown voltage is significantly increased.
Example 6
As shown in fig. 9, a buried layer type terminal structure of a silicon carbide device includes a device cell and a buried layer type terminal, the device cell includes: an N + SiC substrate 2; a P buffer layer 3 on the N + SiC substrate 2; a P-drift region 4 on the P buffer layer 3; an N base region 6 positioned on the P-drift region 4, a gate region 7 formed by ion implantation on the N base region 6, and a P + anode region 5 positioned on the N base region 6; the depth d of the buried layer type terminal from the upper surface of the P-drift region 4 =0.6 um.
In the present embodiment, the buried type terminal includes a mesa-etched terminal extension structure 8 and a buried type junction terminal extension structure 9 formed by an ion implantation process. The mesa etching terminal extension structure 8 comprises an etching mesa formed in an N base region and an etching plane formed from etching of the N base region to etching of the P-drift region; the buried junction termination extension structure 9 is at a depth d =0.6um from the upper surface of the P-drift region 4.
In this embodiment, the buried junction termination extension structure 9 includes JTE1 dose region 92 and JTE2 dose region 93, and the JTE2 dose region 93 is completely overlapped on the JTE1 dose region 92 to form a buried field limiting ring JTE.
In the step 5, the first ion implantation step is a JTE1 dose region 92, and the second ion implantation step is a JTE2 dose region 93, wherein the JTE2 dose region 93 is entirely overlapped on the JTE1 dose region 92 to form a JTE1+ JTE2 dose interleaved region 91.
As shown in fig. 9, the final structure is: JTE1+ JTE2 dose interleaved region 91 is connected to mesa etch termination extension structure 8 and is entirely JTE1+ JTE2 dose interleaved region 91.
As shown in fig. 6, the maximum breakdown voltage at different interface fixed charge densities gradually decreases as the fixed charges increase, but the buried terminal structure has better stability and reliability compared with the conventional structure. The magnitude of the reduction of the maximum breakdown voltage is relatively small and the maximum breakdown voltage is significantly increased.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts of the present invention. The foregoing is only a preferred embodiment of the present invention, and it should be noted that there are objectively infinite specific structures due to the limited character expressions, and it will be apparent to those skilled in the art that a plurality of modifications, decorations or changes may be made without departing from the principle of the present invention, and the technical features described above may be combined in a suitable manner; such modifications, variations, combinations, or adaptations of the invention using its spirit and scope, as defined by the claims, may be directed to other uses and embodiments.

Claims (10)

1. The buried layer type terminal structure of the silicon carbide device is characterized by comprising a device cell and a buried layer type terminal, wherein the device cell comprises: an N + SiC substrate (2); a P buffer layer (3) on the N + SiC substrate (2); a P-drift region (4) on the P buffer layer (3); an N base region (6) positioned on the P-drift region (4), a gate region (7) formed by ion implantation on the N base region (6), and a P + anode region (5) positioned on the N base region (6); the depth d of the buried layer type terminal from the upper surface of the P-drift region (4) is not less than 0.3 um.
2. A buried terminal structure in a sic device according to claim 1, characterized in that the buried terminal comprises a mesa-etched terminal extension (8) and a buried junction terminal extension (9) formed by an ion implantation process.
3. The buried terminal structure of claim 2, wherein the buried junction extension structure (9) has a depth d ≧ 0.3um from the upper surface of the P-drift region (4).
4. A buried termination structure in a sic device according to claim 3, wherein the buried junction termination extension structure (9) comprises JTE1 dose region (92) and JTE2 dose region (93), the JTE2 dose region (93) partially overlapping the JTE1 dose region (92) to form a buried poly ring modulated JTE or buried tri-region JTE; the JTE2 dosage region (93) is completely overlapped on the JTE1 dosage region (92) to form a buried field limiting ring JTE or a buried guard ring auxiliary JTE.
5. The buried terminal structure of the SiC device as claimed in claim 4, wherein the mesa etched terminal extension structure (8) comprises an etched mesa formed in the N-base region and an etched plane formed from the N-base region to the P-drift region.
6. A preparation method of a buried layer type terminal structure of a silicon carbide device is characterized in that,
(1) cleaning the silicon carbide epitaxial wafer;
(2) depositing a SiO2 oxide layer on the epitaxial wafer, and etching to form an anode table top;
(3) etching a gate electrode mesa;
(4) performing ion implantation in the gate region to form a high-concentration region for forming ohmic contact, and performing high-temperature annealing treatment to activate ions;
(5) preparing a buried layer type terminal;
i) etching the mesa from the N base region to the P-drift region to finally form a mesa etching terminal extension structure (8);
ii) carrying out first ion implantation on the P-drift region, wherein the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, and the distance d between the ion implantation depth and the upper surface is not less than 0.3 um;
iii) carrying out second ion implantation on the P-drift region, wherein the second ion implantation depth is consistent with the first ion implantation depth, and finally forming a buried junction terminal extension structure (9), the ion region is divided into four different implantation energies and implantation doses to form a uniformly distributed region, the first implantation dose is twice of the second implantation dose, and the implantation energies are consistent;
iV) annealing process treatment;
(6) passivating the upper surface of the epitaxial wafer to form two oxide layers;
(7) etching an anode contact area, sputtering metal on the surface of the anode contact area, and annealing to form P + ohmic contact and ohmic contact of an N + gate area;
(8) then passivation and etching are carried out to form a contact window sputtering aluminum metal; and then forming a cathode ohmic contact on the lower surface of the epitaxial wafer.
7. The method for preparing the buried terminal structure of the SiC device as claimed in claim 6, wherein in step 3, the gate mesa is repeatedly etched, and the etching depth is determined by a probe.
8. The method as claimed in claim 6, wherein step 4 comprises implanting nitrogen ions into the gate region to form a high concentration region for ohmic contact, and activating the nitrogen ions by high temperature annealing.
9. The method for preparing the buried terminal structure of the SiC device as claimed in claim 6, wherein the buried junction extension structure (9) is formed by two-step ion implantation with a dosage of 4e12cm-2-1.8e13cm-2The second step implantation dose is 2e12cm-2-9e12cm-2The energy and the dose of the four times of implantation in the first step of ion implantation are sequentially decreased progressively, and the energy and the dose of the four times of implantation in the second step of ion implantation are sequentially decreased progressively.
10. The method as claimed in claim 6, wherein the first step of ion implantation is performed by JTE1 dose region (92), the second step of ion implantation is performed by JTE2 dose region (93), and the overlapping portion of JTE2 dose region (93) and JTE1 dose region (92) forms JTE1+ JTE2 dose interleaved region (91).
CN202011059252.3A 2020-09-30 2020-09-30 Buried layer type terminal structure of silicon carbide device and preparation method thereof Pending CN112349771A (en)

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