CN111863608A - Single-particle-burnout-resistant high-power transistor and manufacturing method thereof - Google Patents
Single-particle-burnout-resistant high-power transistor and manufacturing method thereof Download PDFInfo
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- CN111863608A CN111863608A CN202010735726.5A CN202010735726A CN111863608A CN 111863608 A CN111863608 A CN 111863608A CN 202010735726 A CN202010735726 A CN 202010735726A CN 111863608 A CN111863608 A CN 111863608A
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- 238000004519 manufacturing process Methods 0.000 title description 4
- 229910001385 heavy metal Inorganic materials 0.000 claims abstract description 56
- 150000002500 ions Chemical class 0.000 claims abstract description 55
- 238000005468 ion implantation Methods 0.000 claims abstract description 49
- 238000002513 implantation Methods 0.000 claims abstract description 31
- 230000003647 oxidation Effects 0.000 claims abstract description 27
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000002245 particle Substances 0.000 claims abstract description 15
- 238000002360 preparation method Methods 0.000 claims abstract description 14
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 25
- 230000001590 oxidative effect Effects 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 5
- -1 platinum ions Chemical class 0.000 claims description 5
- 238000009826 distribution Methods 0.000 claims description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 16
- 230000006798 recombination Effects 0.000 abstract description 7
- 238000005215 recombination Methods 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 14
- 239000012535 impurity Substances 0.000 description 11
- 238000000206 photolithography Methods 0.000 description 11
- 230000000694 effects Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000002787 reinforcement Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
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- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Abstract
The invention provides a high-power transistor capable of resisting single event burnout and a preparation method thereof. The preparation method of the high-power transistor comprises the following steps: providing a substrate, and forming an epitaxial layer on the substrate; carrying out oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window; and carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation area formed by implanting the heavy metal ions for the next time is positioned above an ion implantation area formed by implanting the heavy metal ions for the previous time. According to the invention, through carrying out multiple times of heavy metal ion injection on the epitaxial layer, the recombination rate of the epitaxial layer radiation induced electron-hole pairs is increased, the collection efficiency of charges under a high electric field is reduced, the single-particle burnout resistance of the transistor is improved, and meanwhile, the high performance index of the transistor can be ensured. In addition, the preparation method is technically compatible with the conventional preparation method of the transistor, and has simple steps and easy operation.
Description
Technical Field
The invention relates to the technical field of electronic devices, in particular to a single-particle burnout resistant high-power transistor and a preparation method thereof.
Background
Power devices are a widely used class of electronic devices in a radiating environment. However, due to the fact that the power device is made of various materials and has a complex structure, under the action of a radiation environment, various complex radiation damage effects such as a single event effect, an ionization effect, a displacement effect, an ionization/displacement synergistic effect and the like can be generated, so that the power device becomes a damage sensitive part of an electronic system of the equipment, and the service life and the reliability of the equipment are further influenced.
For many years, attention has been paid to how to effectively improve the single-particle burnout resistance of a high-power transistor in a radiation environment, and currently, radiation-resistant reinforcement measures for transistors have limited improvement degree of the single-particle burnout resistance and can reduce the performance index of the transistor to a certain extent.
Disclosure of Invention
The invention solves the problem of how to effectively improve the single-particle burnout resistance of the high-power transistor in the radiation environment and ensure the performance index of the high-power transistor.
In order to solve at least one aspect of the above problems, the present invention provides a method for preparing a high power transistor resistant to single event burnout, including:
providing a substrate, and forming an epitaxial layer on the substrate;
carrying out oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
and carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation area formed by implanting the heavy metal ions for the next time is positioned above an ion implantation area formed by implanting the heavy metal ions for the previous time.
Preferably, the number of times of implantation of the heavy metal ions is 3 to 5.
Preferably, a plurality of ion implantation regions are formed in the epitaxial layer, the ion implantation regions are distributed at intervals along the depth direction of the epitaxial layer, and the distance between adjacent ion implantation regions is 1 μm-3 μm.
Preferably, the concentration of the heavy metal ions injected in each time is 1e17cm-2-1e20cm-2。
Preferably, the distribution form of the heavy metal ions in the epitaxial layer is conical, cylindrical, cubic or cuboid.
Preferably, the cross-sectional shape of the ion implantation region is circular, rectangular, square or trapezoidal.
Preferably, the oxidizing the epitaxial layer includes: oxidizing the surface of the epitaxial layer far away from the substrate to generate an oxide layer, wherein the thickness of the oxide layer is 0.1-3 μm, and the oxidizing atmosphere is N2、O2And H2At least one of the above-mentioned materials, its oxidation temperature is 800 deg.C-1300 deg.C, and its oxidation time is 2min-200 min.
Preferably, the heavy metal ions include at least one of gold ions, copper ions, and platinum ions.
Compared with the prior art, the preparation method of the single-particle burnout resistant high-power transistor has the following beneficial effects:
according to the invention, heavy metal ion implantation is carried out on the epitaxial layer for multiple times, the heavy metal ion impurities are deep-level impurities, a recombination center can be generated, the recombination rate of electron-hole pairs induced by epitaxial layer radiation is increased, the collection efficiency of charges under a high electric field is reduced, and instantaneous large current generated by incident high-energy particles in the transistor is led out of a power device, so that the single-particle burnout resistance of the high-power transistor is improved, and meanwhile, the high-performance index of the transistor can be ensured. In addition, the preparation method is technically compatible with the conventional preparation method of the transistor, and has simple steps and easy operation.
The invention also provides a high-power transistor resistant to single-particle burning, which is prepared by adopting the preparation method of the high-power transistor resistant to single-particle burning.
Preferably, the ion implantation device comprises a substrate, an epitaxial layer formed on the substrate, and a plurality of ion implantation regions formed in the epitaxial layer and distributed at intervals along the depth direction of the epitaxial layer, wherein ions implanted in the ion implantation regions are heavy metal ions.
Compared with the prior art, the high-power transistor capable of resisting single-event burnout has the same beneficial effect as the preparation method of the high-power transistor capable of resisting single-event burnout, and the detailed description is omitted here.
Drawings
FIG. 1 is a schematic cross-sectional view of a high-power transistor according to an embodiment of the present invention, in which a primary oxidation process is performed on the surface of the epitaxial layer;
FIG. 2 is a schematic cross-sectional view of a high-power transistor having a single photolithographic process on the surface of its epitaxial layer according to an embodiment of the present invention;
FIG. 3 is a schematic cross-sectional view illustrating a high-power transistor according to an embodiment of the present invention, in which heavy metal ions are implanted into an epitaxial layer of the high-power transistor at one time;
FIG. 4 is a schematic cross-sectional view of a high-power transistor according to an embodiment of the present invention, in which a second oxidation process is performed on the surface of the epitaxial layer;
FIG. 5 is a schematic cross-sectional view of a high-power transistor having a second photolithography process performed on the surface of the epitaxial layer according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional structure diagram of a high-power transistor in which heavy metal ions are implanted secondarily in its epitaxial layer according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view of a high-power transistor with triple oxidation treatment on the surface of its epitaxial layer according to an embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of a high-power transistor with three photolithographic processes on the surface of its epitaxial layer according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a high-power transistor according to an embodiment of the present invention, in which heavy metal ions are implanted three times into an epitaxial layer of the high-power transistor;
FIG. 10 is a schematic cross-sectional view of a high power transistor having four oxidation processes performed on the surface of the epitaxial layer according to an embodiment of the present invention;
fig. 11 is a schematic cross-sectional structure diagram of a high-power transistor in which four times of photolithography processes are performed on the surface of the epitaxial layer according to the embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
The embodiment of the invention provides a preparation method of a high-power transistor resistant to single event burnout, which comprises the following steps:
step 1, providing a substrate and forming an epitaxial layer on the substrate;
step 2, carrying out oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
and 3, performing multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation region formed by implanting heavy metal ions at the next time is positioned above an ion implantation region formed by implanting heavy metal ions at the previous time, and the up-down direction refers to the depth direction of the epitaxial layer, namely the position of the ion implantation region formed by implanting heavy metal ions at the next time in the epitaxial layer is shallower than the ion implantation region formed by implanting heavy metal ions at the previous time.
It should be understood that, before each implantation of heavy metal ions, oxidation and photolithography processes are performed, i.e. returning to step 2, the implantation window is etched, and then the implantation of heavy metal ions is performed.
Under the action of radiation environment, the power device can generate various complex radiation loss effects, such as single-particle burning effect. This embodiment is when preparing high-power transistor, pour into heavy metal ion into the epitaxial layer, when heavy metal ion impurity gets into the epitaxial layer, can produce new defect energy level in the energy band of epitaxial layer semiconductor, a large amount of defect energy levels become the recombination center of electron hole pair, and the energy level is the deep energy level that is located near forbidden band center, for effectual recombination center, play the combined action to the electron and the hole that the radiation induction produced, reduce the collection influence of electric charge, reduce the irradiation current, derive the device with the high energy particle that incides in the space the heavy current in the twinkling of an eye that produces in the device. The high-performance index of the high-power device is guaranteed, the single-particle burnout resistance of the power device can be effectively improved, and the purpose of relieving radiation damage of the power device is achieved.
The heavy metal ions include at least one of gold ions (Au), copper ions (Cu), platinum ions (Pt) and the like, and the heavy metal ions are used as common metals in the manufacturing of semiconductor devices and have good process compatibility with the manufacturing process of the semiconductor devices.
According to the embodiment, heavy metal ions are injected into the epitaxial layer for multiple times, the recombination rate of the epitaxial layer radiation induced electron hole pairs is effectively increased, the collection efficiency of charges under a high electric field is reduced, and the single-particle burnout resistance of the power device is powerfully improved. And the method is compatible with the conventional preparation method of the power device, has simple steps and is easy to operate. The high-power transistor device prepared by the method provided by the embodiment can greatly improve the radiation resistance of the transistor, has great significance for ground simulation application and research of space and nuclear radiation environmental effect of materials and devices, and has obvious advantages in space and nuclear radiation environmental effect research and radiation-resistant reinforcement technology application.
Further, the substrate provided in this embodiment may be an N-type substrate or a P-type substrate, as shown in fig. 1, taking an N-type substrate as an example, an N-type epitaxial layer is grown on an N-type substrate, an oxidation treatment is performed on the surface of the N-type epitaxial layer, an oxide layer is grown, the thickness of the oxide layer is 0.1 μm to 3 μm, the oxide layer is grown in a manner of one of dry oxygen, wet oxygen and a dry/wet oxygen mixing method, and the oxidation atmosphere is N2、O2And H2At least one of the above-mentioned materials, its oxidation temperature is 800 deg.C-1300 deg.C, and its oxidation time is 2min-200 min.
As shown in fig. 2, a photolithography process is performed on the surface of the oxide layer to etch an injection window, the center of the injection window is aligned with the center of the epitaxial layer, and the etching manner may be dry etching, wet etching, or plasma etching.
As shown in fig. 3, heavy metal ion implantation is performed on the epitaxial layer through the implantation window a plurality of times to form a multi-layered ion implantation region in the epitaxial layer. In this embodiment, the number of times of implantation of the heavy metal ions is 3 to 5, it should be noted that oxidation and photolithography processing need to be performed on the epitaxial layer before the heavy metal ions are implanted each time, according to the number of times of implantation of the heavy metal ions, a plurality of ion implantation regions are formed in the epitaxial layer and are distributed at intervals in the depth direction of the epitaxial layer, and the distance between two adjacent ion implantation regions is 1 μm to 3 μm. Heavy metal ion impurities injected into the ion injection region generate new defect energy levels in the epitaxial layer to form recombination centers of electron-hole pairs so as to reduce charge collection efficiency.
Preferably, the concentration of the heavy metal ions injected in each time is 1e17cm-2-1e20cm-2But of course may be less than 1e17cm-2Or greater than 1e20cm-2This is mainly related to the type of device, the amount of implantation or diffusion per time is relatively large for devices with relatively large currents, and relatively small for devices with relatively small currents, but the embodiment only shows that the amount of implantation or diffusion per time for most devices is 1e17cm-2-1e20cm-2。
The epitaxial layer comprises a plurality of ion implantation regions arranged along the depth direction of the epitaxial layer, and the cross section of each ion implantation region can be circular, rectangular, square or trapezoidal. The overall distribution form of the heavy metal ion impurities in the epitaxial layer can be a cone, a cylinder, a cube or a cuboid, for example, the cross section of each layer of ion implantation area is circular, and the cross section area of each layer of ion implantation area is equal, so that the heavy metal ion impurities are distributed in a cylindrical shape in the epitaxial layer. If the cross-sectional shape of each ion implantation region is circular, but the cross-sectional area of the ion implantation region is gradually reduced from the side close to the substrate to the side far away from the substrate, the heavy metal ion impurities are distributed in the epitaxial layer in a conical shape, wherein the size of the cross-sectional area of the ion implantation region can be controlled by changing the size of the implantation window. The distribution form of heavy metal ion impurities in the epitaxial layer can be changed by adjusting the energy of the implanted heavy metal ions.
The following is a detailed description of the preferred embodiments.
Example 1
As shown in FIG. 1, after forming an N-type epitaxial layer on an N-type substrate, the epitaxial layer is formedPerforming primary oxidation treatment on the upper surface of the layer to grow an oxide layer in an oxidizing atmosphere of N2The oxidation temperature is 1300 ℃, the oxidation time is 40min, the dry oxygen is generated in the oxide layer growth mode, and the thickness of the grown oxide layer is 50 nm;
as shown in fig. 2, performing a photolithography process on the surface of the oxide layer to etch a first injection window, where the cross-sectional area of the first injection window is 4/5 of the epitaxial layer, and the etching manner is dry etching;
as shown in fig. 3, a first heavy metal ion impurity implantation is performed through a first implantation window, the implanted heavy metal ion is Au, the implantation position is located at the bottom of the epitaxial layer, and the implantation concentration is 1e18cm-2Forming a first ion implantation region in the epitaxial layer;
as shown in fig. 4, a secondary oxidation treatment is performed on the upper surface of the epitaxial layer in the same manner as the primary oxidation treatment;
as shown in fig. 5, performing a second photolithography process on the surface of the oxide layer, etching a second implantation window, wherein the cross-sectional area of the second implantation window is 3/5 of the area of the epitaxial layer, and the etching manner is the same as that of the first photolithography process;
as shown in fig. 6, a second heavy metal ion impurity implantation is performed through a second implantation window, the implantation position is 1 μm away from the first ion implantation region, the type and concentration of the implanted ions are the same as those of the first implantation, a second ion implantation region is formed in the epitaxial layer, and the second ion implantation region is located above the first ion implantation region;
as shown in fig. 7, the upper surface of the epitaxial layer is subjected to oxidation treatment three times in the same manner as the primary oxidation;
as shown in fig. 8, three times of photolithography processing is performed on the surface of the oxide layer, a third implantation window is etched, the cross-sectional area of the third implantation window is 2/5 of the area of the epitaxial layer, and the etching manner is the same as that of the one-time photolithography processing;
as shown in fig. 9, a third heavy metal ion impurity implantation is performed through a third implantation window, the implantation position is 1 μm away from the second ion implantation region, the type and concentration of the implanted ions are the same as those of the first implantation, a third ion implantation region is formed in the epitaxial layer, and the third ion implantation region is located above the second ion implantation region;
as shown in fig. 10, four times of oxidation treatment is performed on the upper surface of the epitaxial layer in the same manner as the primary oxidation treatment;
as shown in fig. 11, four times of photolithography processes are performed on the surface of the oxide layer to etch and expose the entire upper surface of the epitaxial layer.
Example 2
The present embodiment is different from embodiment 1 in that the number of times of implanting metal ions is 5.
Example 3
This example is different from example 1 in that the concentration of the implanted heavy metal ions was 1e20cm-2。
Example 4
This example is different from example 1 in that the concentration of the implanted heavy metal ions was 1e17cm-2。
Example 5
This example is different from example 1 in that the concentration of the implanted heavy metal ions is less than 1e17cm-2。
Example 6
The present embodiment is different from embodiment 1 in that the cross-sectional shape and the cross-sectional area of the ion implantation region formed by implanting heavy metal ions each time are equal.
Although the present disclosure has been described above, the scope of the present disclosure is not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the spirit and scope of the present disclosure, and these changes and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. A preparation method of a high-power transistor resistant to single-particle burning is characterized by comprising the following steps:
providing a substrate, and forming an epitaxial layer on the substrate;
carrying out oxidation treatment and photoetching treatment on the epitaxial layer to form an injection window;
and carrying out multiple times of heavy metal ion implantation on the epitaxial layer through the implantation window, wherein an ion implantation area formed by implanting the heavy metal ions for the next time is positioned above an ion implantation area formed by implanting the heavy metal ions for the previous time.
2. The method for preparing a high-power transistor resistant to single event burnout according to claim 1, wherein the number of times of implantation of the heavy metal ions is 3-5.
3. The method for preparing a single-event-burnout-resistant high-power transistor according to claim 1, wherein a plurality of ion implantation regions are formed in the epitaxial layer, the plurality of ion implantation regions are distributed at intervals along the depth direction of the epitaxial layer, and the distance between the adjacent ion implantation regions is 1 μm-3 μm.
4. The method for preparing a high-power transistor capable of resisting single event burnout according to claim 1, wherein the concentration of the heavy metal ions injected each time is 1e17cm-2-1e20cm-2。
5. The method for preparing a single event burnout resistant high-power transistor according to claim 1, wherein the distribution form of the heavy metal ions in the epitaxial layer is conical, cylindrical, cubic or cuboid.
6. The method for preparing a single event burnout resistant high-power transistor according to claim 1, wherein the cross-sectional shape of the ion implantation region is circular, rectangular, square or trapezoidal.
7. The method for preparing a single event burnout resistant high-power transistor according to any one of claims 1 to 6, wherein the step of oxidizing the epitaxial layer comprises the steps of: oxidizing the surface of the epitaxial layer far away from the substrate to generate an oxide layer, wherein the thickness of the oxide layer is 0.1-3 μm, and the oxidizing atmosphere is N2、O2And H2At least one of the above-mentioned materials, its oxidation temperature is 800 deg.C-1300 deg.C, and its oxidation time is 2min-200 min.
8. The method for preparing a single event burnout resistant high power transistor according to any one of claims 1-6, wherein the heavy metal ions include at least one of gold, copper and platinum ions.
9. A high-power transistor resistant to single event burnout, which is prepared by the preparation method of the high-power transistor resistant to single event burnout according to any one of claims 1 to 8.
10. The single event burnout resistant high-power transistor according to claim 9, comprising a substrate, an epitaxial layer formed on the substrate, and a plurality of ion implantation regions formed in the epitaxial layer and distributed at intervals along the depth direction of the epitaxial layer, wherein the ions implanted in the ion implantation regions are heavy metal ions.
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