CN103872101B - A kind of isolated-gate field effect transistor (IGFET) and preparation method thereof - Google Patents
A kind of isolated-gate field effect transistor (IGFET) and preparation method thereof Download PDFInfo
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- CN103872101B CN103872101B CN201210551729.9A CN201210551729A CN103872101B CN 103872101 B CN103872101 B CN 103872101B CN 201210551729 A CN201210551729 A CN 201210551729A CN 103872101 B CN103872101 B CN 103872101B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 29
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The present invention relates to isolated-gate field effect transistor (IGFET) technical field, discloses a kind of isolated-gate field effect transistor (IGFET) and preparation method thereof.The preparation method includes：Using N-type SiC single crystal material as backing material, and go out graphene in SiC surface epitaxial growth, form graphene conductive layer；Graphene is etched, and retains the graphene of the non-channel region between the cellular region below grid；Technological requirement according to isolated-gate field effect transistor (IGFET) is made forms p-type base, N-type launch site, active area metal level and gate metal layer；After isolated-gate field effect transistor (IGFET) metallization, collector electrode metal is generated at the back side of isolated-gate field effect transistor (IGFET).The present invention reduces the overall electrical resistance of chip so that device has smaller saturation conduction pressure drop on the basis of the voltage endurance of device is not reduced.
Description
Technical field
The present invention relates to isolated-gate field effect transistor (IGFET) technical field, be primarily adapted for use in isolated-gate field effect transistor (IGFET) and its
Preparation method.
Background technology
IGBT is widely used in various occasions as a kind of new power electronic devices.It relative to VDMOS and
Speech, there is a bigger current density, lower conduction voltage drop, and higher pressure-resistant；It is for power transistor, tool
There are higher pressure-resistant, simpler control circuit, and higher switching speed.But the lower conduction voltage drops of IGBT are pursued,
Higher switching speed is the tight demand that power electronic system continues to develop.The mode for improving IGBT characteristics mainly can be with
It is divided into two broad aspects：The improvement of device architecture and the selection of device material.First, the improvement to device architecture can be divided into water again
Square to improvement and vertical direction improvement；Horizontal direction can be that planar gate can also be mainly for the structure of grid
Trench gate, the improvement of vertical direction include adding carrier accumulation layer or electric field cutoff layer etc..Secondly, for device material
Choose, what is initially selected is epitaxy single-crystal silicon materials, and subsequent study on floating zone silicon is widely used.With the continuous hair of new material
Exhibition, SiC material start to show up prominently and develop rapidly in IGBT and other power device fields by its excellent characteristic.
And grapheme material has close to perfect electric property, although not having its related application, phase in power device industry
Believe deepening continuously with pilot study, it also can will greatly promote the development of power device.
Resistance under IGBT is in the conduction state includes：Channel resistance, N drift zone resistances, JFET resistance, barrier resistance,
Each contact resistance etc..The important means that these resistance are raising device static characteristics is reduced by various modes.
It is a more typical mode for reducing device saturation conduction pressure drop to reduce device JFET resistance.Wherein, by plane
It is a kind of most commonly seen implementation that grid structure is replaced with trench gate structure, by embedded trench-gate, eliminates JFET
Region.In addition, the method for the grid N doped regions formed below between Yuan Bao, popular to be referred to as JFET injections and common
A kind of method.
But at present there is problems with JFET injection methods：
Although 1.JFET injects the JFET resistance that can reduce device to a certain extent, there is also reduce device simultaneously
Risk that part is pressure-resistant, thus can not be simply reduce JFET resistance by this method.
N drift region injection phosphonium ion of the 2.JFET injections below the grid namely between Yuan Bao forms higher concentration
N-type doping, it is clear that such improvement project can cause the pressure-resistant reduction of device.
3. because there is larger input, output and miller capacitance, the IGBT of the type in existing groove-shaped IGBT
HF switch characteristic it is bad, significantly limit its application occasion.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of isolated-gate field effect transistor (IGFET) and preparation method thereof, it
On the basis of the voltage endurance for not reducing device, the overall electrical resistance of chip is reduced, so that device has smaller saturation
Conduction voltage drop.
In order to solve the above technical problems, the invention provides a kind of isolated-gate field effect transistor (IGFET), including：Graphene conductive
Layer；Between the grid oxic horizon and semiconductor layer of non-channel region of the graphene conductive layer between cellular region.
Present invention also offers a kind of preparation method of isolated-gate field effect transistor (IGFET) to include：
Using N-type SiC single crystal material as backing material, and go out graphene in the surface epitaxial growth of the SiC, formed
Graphene conductive layer；
The graphene is etched, and retains the graphene of the non-channel region between the cellular region below grid；
Technological requirement according to isolated-gate field effect transistor (IGFET) is made forms p-type base, N-type launch site, active area metal
Layer and gate metal layer；
After isolated-gate field effect transistor (IGFET) metallization, colelctor electrode is generated at the back side of the isolated-gate field effect transistor (IGFET)
Metal.
Further, the surface epitaxial growth in SiC, which goes out graphene, includes：By SiC epitaxys the SiC's
Surface epitaxial growth goes out the graphene of one layer or multilayer.
Further, the graphene bag for going out one layer or multilayer in SiC surface epitaxial growth by SiC epitaxys
Include：The SiC single crystal piece crossed through peroxidating or H2 etching processings is placed in ultrahigh vacuum and temperature range at 1800 DEG C -2400 first
Under hot environment between DEG C, SiC single crystal piece described in beam bombardment, the oxide on removing SiC single crystal piece surface are utilized；Then
Under the high temperature conditions by the Si vaporised atoms in SiC single crystal piece superficial layer, make the carbon atom of SiC single crystal piece surface residual that weight occur
Structure, i.e., go out graphene in the surface epitaxial growth of SiC single crystal piece.
Further, the etching graphene includes：Using graphene described in hydrogen plasma etching.
Further, it is described to include according to the technological requirement formation p-type base for making isolated-gate field effect transistor (IGFET)：According to
The technological requirement for making isolated-gate field effect transistor (IGFET) first deposits grid oxic horizon and grid polycrystalline silicon；It is more that the grid is etched again
Crystal silicon and the grid oxic horizon, form the injection window of p-type base；Again high energy is injected to the injection window of the p-type base
Boron ion, and anneal, form p-type base.
Further, it is described to include according to the technological requirement formation N-type launch site for making isolated-gate field effect transistor (IGFET)：Press
According to the technological requirement elder generation deposited oxide layer for making isolated-gate field effect transistor (IGFET) and etch the oxide layer formation N-type emitter stage
Window is injected, then high energy phosphonium ion is injected to the injection window of the N-type emitter stage, and is annealed, forms N-type launch site.
Further, after the technological requirement according to making isolated-gate field effect transistor (IGFET) forms N-type launch site, first
Deposited oxide layer, then etch the oxide layer and form emitter stage contact window.
Further, it is described to form active area metal level and grid according to the technological requirement for making isolated-gate field effect transistor (IGFET)
Pole metal level includes：Metal is first deposited, then etches the metal and forms active area metal level and gate metal layer.
Further, it is described after isolated-gate field effect transistor (IGFET) metallization, at the back side of isolated-gate field effect transistor (IGFET)
Generation collector electrode metal includes：After the front-side metallization of the isolated-gate field effect transistor (IGFET), chip upset, p-type note is carried out
Enter to be formed p-type collecting zone；After the back face metalization of isolated-gate field effect transistor (IGFET), the p-type collecting zone is connect into metal electrode
Form collector electrode metal.
The beneficial effects of the present invention are：
Isolated-gate field effect transistor (IGFET) provided by the invention and preparation method thereof using SiC as original material, cellular region it
Between non-channel region grid oxic horizon and semiconductor layer between add a layer graphene conductive layer, utilize grapheme material
Conductive characteristic can reduce the electricresistance effect of the entozoic junction field effect transistor of device, so as to not reduce the pressure-resistant spy of device
On the basis of property, the overall electrical resistance of chip is reduced so that device has smaller saturation conduction pressure drop.Further, since this hair
It is bright to reduce the overall electrical resistance of device simply by the low graphene of resistivity is increased, big electric capacity is not introduced, thus protect
The HF switch characteristic of device is demonstrate,proved.It is the rational in infrastructure, significant effect of the present invention, practical.
Brief description of the drawings
Fig. 1 is the flow chart of the preparation method of isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention.
Fig. 2 is the preparation method by isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention in N-type SiC single crystal material
The structural representation of obtained isolated-gate field effect transistor (IGFET) is formed after graphene conductive layer on material.
Fig. 3 is to be obtained after etching graphene by the preparation method of isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention
The structural representation of the isolated-gate field effect transistor (IGFET) arrived.
Fig. 4 is to deposit grid oxic horizon by the preparation method of isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention
With the structural representation of isolated-gate field effect transistor (IGFET) obtained after grid polycrystalline silicon.
Fig. 5 is the preparation method etching grid oxide layer by isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention
With the structural representation of isolated-gate field effect transistor (IGFET) obtained after grid polycrystalline silicon.
Fig. 6 be by the preparation method of isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention carry out ion implanting and
Diffusion forms behind p-type base and N-type launch site the structural representation of obtained isolated-gate field effect transistor (IGFET) respectively.
Fig. 7 is the insulated gate field obtained by the preparation method of isolated-gate field effect transistor (IGFET) provided in an embodiment of the present invention
The structure schematic diagram of effect transistor.
1-N type SiC single crystal materials, 2-P type collecting zones, 3-P types base, 4-N types launch site, 5- grid polycrystalline silicons, 6- grid
Pole oxide layer, 7- emitter electrodes, 8- collector electrodes, 10- gate metal electrodes, 11- graphenes.
Embodiment
For the present invention is expanded on further to reach the technological means and effect that predetermined goal of the invention is taken, below in conjunction with attached
Figure and preferred embodiment, to the embodiment according to isolated-gate field effect transistor (IGFET) proposed by the present invention and preparation method thereof
And operation principle is described in detail.
Isolated-gate field effect transistor (IGFET) provided by the invention, including：Graphene conductive layer；Graphene conductive layer is located at cellular
Between the grid oxic horizon and semiconductor layer of non-channel region between area.
As shown in Figure 1, the preparation method of isolated-gate field effect transistor (IGFET) provided by the invention includes：
Using N-type SiC single crystal material as backing material, and go out one by surface epitaxial growth of the SiC epitaxys in SiC
The grapheme material of layer or multilayer, form graphene conductive layer；Specifically, first through peroxidating or H2What etching processing was crossed
SiC single crystal piece is placed in ultrahigh vacuum and temperature range under the hot environment between 1800 DEG C -2400 DEG C, utilizes beam bombardment
SiC single crystal piece, remove the oxide on SiC single crystal piece surface；Then it is under the high temperature conditions that the Si in SiC single crystal piece superficial layer is former
Son evaporation, reconstructs the carbon atom of SiC single crystal piece surface residual, i.e., goes out graphene in the surface epitaxial growth of SiC single crystal piece.
In the present embodiment, hot environment is the environment that temperature is 2200 DEG C.When its technological parameter is regulated and controled, it is possible to achieve individual layer
Or the preparation of multi-layer graphene.Explanation is needed exist for, the crystal formation of SiC single crystal silicon chip includes 6H, 4H and 3C.
Using the grapheme material of hydrogen plasma etching surface of SiC, and retain the non-ditch between the cellular region below grid
The graphene in road region；
Technological requirement according to isolated-gate field effect transistor (IGFET) is made forms p-type base, N-type launch site, active area metal
Layer and gate metal layer；Specifically, according to make isolated-gate field effect transistor (IGFET) technological requirement first deposit grid oxic horizon and
Grid polycrystalline silicon；Etching grid polysilicon and grid oxic horizon again, form the injection window of p-type base；Again to the note of p-type base
Enter window injection high energy boron ion, and anneal, form p-type base.
Deposited oxide layer and etching oxidation layer form the injection window of N-type emitter stage, then the injection window to N-type emitter stage again
Mouth injection high energy phosphonium ion, and anneal, form N-type launch site.
Thick oxide layer is deposited again, then is etched thick oxide layer and formed emitter stage contact window.
Then metal is deposited, then etches metal and forms active area metal level and gate metal layer；Active area metal level is filled
When emitter electrode 7, gate metal layer is served as into gate metal electrode 10.
After isolated-gate field effect transistor (IGFET) metallization, in the back side of isolated-gate field effect transistor (IGFET) generation colelctor electrode gold
Category；Specifically, after the front-side metallization of isolated-gate field effect transistor (IGFET), chip upset, carry out p-type and inject to form p-type current collection
Area；After the back face metalization of isolated-gate field effect transistor (IGFET), p-type collecting zone is connect into metal electrode and forms collector electrode 8.
Isolated-gate field effect transistor (IGFET) is made by the preparation method of isolated-gate field effect transistor (IGFET) provided by the invention, by
Fig. 2 is understood, is used as backing material using N-type SiC single crystal material 1 first, and give birth to by surface extension of the SiC epitaxys in SiC
Graphene 11 is grown, forms graphene conductive layer；From the figure 3, it may be seen that using the graphene 11 of hydrogen plasma etching surface of SiC, and
Retain the graphene 11 of the non-channel region between the cellular region below grid；As shown in Figure 4, according to making insulated-gate field-effect
The technological requirement deposit grid oxic horizon 6 and grid polycrystalline silicon 5 of transistor；From Fig. 5 and Fig. 6, then etching grid polysilicon 5
With grid oxic horizon 6, the injection window of formation p-type base；Injection window injection high energy boron ion to p-type base again, and move back
Fire, form p-type base 3；Then deposited oxide layer and etching oxidation layer form the injection window of N-type emitter stage, then launch to N-type
The injection window injection high energy phosphonium ion of pole, and anneal, form N-type launch site 4.Then thick oxide layer is deposited, then etches thick oxygen
Change layer and form emitter stage contact window.Metal is deposited again, then is etched metal and formed active area metal level and gate metal layer.Exhausted
After the front-side metallization of geo-gate field-effect transistor, chip upset, carry out p-type and inject to form p-type collecting zone 2；As shown in Figure 7,
After the back face metalization of isolated-gate field effect transistor (IGFET), p-type collecting zone 2 is connect into metal electrode and forms collector electrode 8.
Explanation is needed exist for, the grid structure of the isolated-gate field effect transistor (IGFET) made by the present invention can be flat
Face grid；Its vertical structure can add electric field cutoff layer, can also add carrier accumulation layer.
Because the present invention is after graphene conductive layer add, not the structure of change device cellular remaining position and
Dopant profiles, so the voltage endurance capability of device will not be reduced.
Isolated-gate field effect transistor (IGFET) provided by the invention and preparation method thereof using SiC as original material, cellular region it
Between non-channel region grid oxic horizon and semiconductor layer between add a layer graphene conductive layer, utilize grapheme material
Conductive characteristic can reduce the electricresistance effect of the entozoic junction field effect transistor of device, so as to not reduce the pressure-resistant spy of device
On the basis of property, the overall electrical resistance of chip is reduced so that device has smaller saturation conduction pressure drop.Further, since this hair
It is bright to reduce the overall electrical resistance of device simply by the low graphene of resistivity is increased, big electric capacity is not introduced, thus protect
The HF switch characteristic of device is demonstrate,proved.It is the rational in infrastructure, significant effect of the present invention, practical.
It should be noted last that above embodiment is merely illustrative of the technical solution of the present invention and unrestricted,
Although the present invention is described in detail with reference to example, it will be understood by those within the art that, can be to the present invention
Technical scheme modify or equivalent substitution, without departing from the spirit and scope of technical solution of the present invention, it all should cover
Among scope of the presently claimed invention.
Claims (9)
- A kind of 1. preparation method of isolated-gate field effect transistor (IGFET), it is characterised in that including：Using N-type SiC single crystal material as backing material, and go out graphene in the surface epitaxial growth of the SiC, form graphite Alkene conductive layer；The graphene is etched, and retains the graphene of non-channel region below grid；P-type base, N-type launch site, active area metal level and gate metal layer are formed as requested；After isolated-gate field effect transistor (IGFET) metallization, in the back side of isolated-gate field effect transistor (IGFET) generation colelctor electrode gold Category.
- 2. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that in the table of the SiC Face epitaxial growth, which goes out graphene, to be included：Go out the stone of one layer or multilayer in the surface epitaxial growth of the SiC by SiC epitaxys Black alkene.
- 3. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 2, it is characterised in that it is described by SiC outside Prolonging method and going out the graphene of one layer or multilayer in SiC surface epitaxial growth includes：First through peroxidating or H2Etching processing The SiC single crystal piece crossed is placed under ultrahigh vacuum and hot environment, using SiC single crystal piece described in beam bombardment, removes SiC single crystal The oxide on piece surface；Then the Si vaporised atoms in SiC single crystal piece superficial layer are made into SiC single crystal piece table under the high temperature conditions The remaining carbon atom in face reconstructs, i.e., goes out graphene in the surface epitaxial growth of SiC single crystal piece.
- 4. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that the etching graphene Including：Using graphene described in hydrogen plasma etching.
- 5. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that the shape as requested Include into p-type base：Grid oxic horizon and grid polycrystalline silicon are first deposited according to production requirement；Etch again the grid polycrystalline silicon and The grid oxic horizon, form the injection window of p-type base；High energy boron ion is injected to the injection window of the p-type base again, And anneal, form p-type base.
- 6. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that the shape as requested Include into N-type launch site：According to production requirement elder generation deposited oxide layer and etch the injection window that the oxide layer forms N-type emitter stage Mouthful, then high energy phosphonium ion is injected to the injection window of the N-type emitter stage, and anneal, form N-type launch site.
- 7. the preparation method of the isolated-gate field effect transistor (IGFET) as described in claim 1 or 6, it is characterised in that it is described according to It is required that after forming N-type launch site, first deposited oxide layer, then etch the oxide layer and form emitter stage contact window.
- 8. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that the shape as requested Include into active area metal level and gate metal layer：Metal is first deposited, then etches the metal and forms active area metal level and grid Pole metal level.
- 9. the preparation method of isolated-gate field effect transistor (IGFET) as claimed in claim 1, it is characterised in that described in insulated gate field After effect transistor metallization, at the back side of isolated-gate field effect transistor (IGFET), generation collector electrode metal includes：In the insulated gate After the front-side metallization of field-effect transistor, chip upset, carry out p-type and inject to form p-type collecting zone；It is brilliant in insulated-gate field-effect After the back face metalization of body pipe, the p-type collecting zone is connect into metal electrode and forms collector electrode metal.
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| WO2017041268A1 (en) * | 2015-09-10 | 2017-03-16 | 中国科学院微电子研究所 | Silicon carbide mosfet device and manufacturing method therefor |
| CN108231560B (en) * | 2016-12-09 | 2022-02-15 | 全球能源互联网研究院 | Control electrode preparation method and MOSFET power device |
| CN108899369B (en) * | 2018-06-27 | 2020-11-03 | 东南大学 | Graphene channel silicon carbide power semiconductor transistor |
| CN115985888A (en) * | 2023-02-23 | 2023-04-18 | 天津大学 | Integrated vertical device obtained by capacitive coupling interconnection and preparation method thereof |
| CN116682735A (en) * | 2023-08-04 | 2023-09-01 | 深圳基本半导体有限公司 | Preparation method of MOS structure self-alignment process |
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