CN208385412U - Transverse diffusion metal oxide semiconductor device - Google Patents
Transverse diffusion metal oxide semiconductor device Download PDFInfo
- Publication number
- CN208385412U CN208385412U CN201820798923.XU CN201820798923U CN208385412U CN 208385412 U CN208385412 U CN 208385412U CN 201820798923 U CN201820798923 U CN 201820798923U CN 208385412 U CN208385412 U CN 208385412U
- Authority
- CN
- China
- Prior art keywords
- conductor
- layer
- metal oxide
- semiconductor device
- oxide semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model provides a kind of transverse diffusion metal oxide semiconductor device, in the transverse diffusion metal oxide semiconductor device, conductor layer above first medium layer and Withstand voltage layer is divided into the first conductor for being at least partially disposed at the first medium layer, and it is at least partially disposed at the second conductor on the Withstand voltage layer, and first conductor and the second conductor space are isolated, first conductor and the second conductor can connect different current potentials, so that the semiconductor devices is still able to maintain higher breakdown voltage in off state.Furthermore, the source electrode of the semiconductor devices above the source area by extending to above at least partly described second conductor, the phenomenon that can falling to avoid the electric field at first conductor and the second conductor open position, so as to improve the pressure-resistant performance of the semiconductor devices.
Description
Technical field
The utility model relates to semiconductor devices, more particularly, to a kind of lateral diffusion metal oxide semiconductor device
Part.
Background technique
In existing transverse diffusion metal oxide semiconductor device 100 as shown in Figure 1, it generally comprises P type substrate
PSUB, high-pressure N-shaped well region HVNW, the area PXing Ti Pbody and N-type drift region N-drift in P type substrate PSUB are respectively formed
In high-pressure N-shaped well region HVNW, source area N+ and drain region N+ are respectively formed in the area PXing Ti Pbody and N-type drift region N-
In drift, body contact zone P+ is also formed in body area Pbody and is in contact with source area N+, and in the table of semiconductor devices 100
Face is additionally provided with the gate dielectric layer adjacent with source area (unmarked in figure) and the thickness between gate dielectric layer and drain region
Oxygen layer Oxide, grid conductor poly cover the gate dielectric layer and extend on heavy oxygen layer Oxide.
Therefore be in semiconductor devices 100, grid conductor Poly is by extending directly to heavy oxygen layer on gate dielectric layer
On Oxide, entire conductor layer Poly is used as grid conductor, by gate electrode receive control semiconductor devices 100 conducting and
The control voltage of shutdown.Therefore, when semiconductor devices 100 is in an off state, the current potential on heavy oxygen layer Oxdie cannot be assisted
N-type drift region N-drift is exhausted, cannot keep the high pressure resistant breakdown performance of device.In addition, gate electrode extends to N-type drift region
Above N-drift, grid leak area foot fold it is larger so that gate charge Qgd is larger so that the frequency applications of semiconductor devices 100 by
Limit.
Summary of the invention
In view of this, the present invention provides a kind of transverse diffusion metal oxide semiconductor devices, so that laterally expanding
Dispersed metallic oxide semiconductor element was not only with higher breakdown voltage resistant, but have lower conducting resistance, and also have compared with
Low gate charge, so that the device of partly leading is adapted to frequency applications.
A kind of transverse diffusion metal oxide semiconductor device characterized by comprising
Base,
Source area and drain region in the base,
First surface and the first medium layer adjacent with the source area positioned at the base,
Positioned at the Withstand voltage layer of the first surface of the base, the Withstand voltage layer is located at the first medium layer and the drain electrode
Between area,
The first conductor being at least partially disposed on the first medium layer,
The second conductor being at least partially disposed on the Withstand voltage layer,
The source electrode being electrically connected with the source area,
Wherein, first conductor and the isolation of the second conductor space, and the source electrode above the source area by extending
To the top of at least partly described second conductor.
Preferably, the transverse diffusion metal oxide semiconductor device further includes the first surface positioned at the base
On interlayer dielectric layer, the exposed source area of interlayer dielectric layer, the source electrode includes across the interlayer dielectric layer
And the first part with the source region contact, and positioned at the inter-level dielectric layer surface and extend at least partly described
Second part above two conductors.
Preferably, the transverse diffusion metal oxide semiconductor device further includes being electrically connected with first conductor
Gate electrode, and the first field plate electrode with the electrical connection of the second conductor,
The gate electrode connects different current potentials from first field plate electrode.
Preferably, first field plate electrode and the source electrode connect identical current potential.
Preferably, the transverse diffusion metal oxide semiconductor device further includes at least one third conductor, each
The third conductor is respectively positioned on above the Withstand voltage layer, and space is isolated each third conductor each other, and each third
Conductor is isolated with second conductor space.
Preferably, the transverse diffusion metal oxide semiconductor device further includes corresponding with each third conductor
Each second field plate electrode of electrical connection,
In each second field plate electrode, the current potential that the second field plate electrode closer to the drain region is connect is got over
It is high.
Preferably, a part of second conductor and a conductor layer in the first conductor is covered on the first medium
Above the intersection of layer and Withstand voltage layer.
Preferably, the Withstand voltage layer is second dielectric layer, and the thickness of the second dielectric layer is greater than the first medium
Layer.
Preferably, the transverse diffusion metal oxide semiconductor device further includes the drift region in the base
With body area,
The drain region is located in the drift region, and the Withstand voltage layer is at least partially disposed above the drift region,
The source area is located in the body area, and the first medium floor is at least partially disposed above the body area.
Preferably, the transverse diffusion metal oxide semiconductor device further includes the reduction table in the base
Face field-effect layer, the reduction surface field effect floor are located at below the body area and drift region, and with the body area with identical
Doping type, and there is different doping types from the drift region.
Preferably, first spacing reduced between surface field effect layer and the drift region is greater than zero.
Preferably, second spacing reduced between surface field effect floor and the body area is less than or equal to described first
Spacing.
Preferably, the transverse diffusion metal oxide semiconductor device further includes being located in the base, and be located at
The separation layer reduced below surface field effect layer,
The separation layer is isolated by the reduction surface field effect layer with the base.
Preferably, the doping concentration of the drift region is bigger, and first spacing is smaller.
Preferably, the base includes semiconductor substrate and the high-pressure trap area in the semiconductor substrate,
The drift region, body area and reduction surface field effect area are respectively positioned in the high-pressure trap area,
The doping type of the semiconductor substrate is identical as the reduction doping type of surface field effect layer, and the height
Press the doping type of well region different from the reduction doping type of surface field active layer.
Therefore according in transverse diffusion metal oxide semiconductor device provided by the utility model, the will be located at
Conductor layer above one dielectric layer and Withstand voltage layer is divided into the first conductor for being at least partially disposed at the first medium layer, and at least
Part is located at the second conductor on the Withstand voltage layer, and first conductor and the second conductor space are isolated, and described first
Conductor and the second conductor can connect different current potentials, so that the semiconductor devices is still able to maintain higher breakdown in off state
Voltage.In addition, the source electrode of the semiconductor devices above the source area by extending at least partly described second conductor
Side, the phenomenon that can falling to avoid the electric field at first conductor and the second conductor open position, so as to improve institute
State the pressure-resistant performance of semiconductor devices.
Detailed description of the invention
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 is the device schematic diagram of existing transverse diffusion metal oxide semiconductor device；
Fig. 2 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment one
Part schematic diagram；
Fig. 3 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment two
Part schematic diagram；
Fig. 4 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment three
Part schematic diagram；
Fig. 5 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment four
Part schematic diagram；
Fig. 6 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment five
Part schematic diagram；
Fig. 7 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment six
Part schematic diagram；
Fig. 8 is a kind of device of the transverse diffusion metal oxide semiconductor device provided according to the utility model embodiment seven
Part schematic diagram.
Specific embodiment
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical component part uses
Similar appended drawing reference indicates.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to not
Certain well known parts are shown.For brevity, the device obtained after several steps can be described in a width figure.?
Described hereafter is many specific details of the utility model, such as the device of each component part, material, size, processing
Technique and technology, to be more clearly understood that the utility model.But it just as the skilled person will understand, can
Not realize the utility model according to these specific details.
Fig. 2 is a kind of transverse diffusion metal oxide semiconductor device 200 provided according to the utility model embodiment one
Structural schematic diagram.The semiconductor devices provided according to the utility model embodiment one specifically includes that base, is located at base Zhong Yuan
Polar region and drain region, first surface and the first medium layer adjacent with the source area positioned at the base, are located at the base
The Withstand voltage layer of the first surface of layer, the Withstand voltage layer is positioned at the first medium layer and the drain region between, positioned at described the
The first conductor on one dielectric layer, the second conductor on the Withstand voltage layer, the source electrode being electrically connected with the source area,
In, first conductor and the isolation of the second conductor space, and the source electrode above the source area by extending at least partly
The top of second conductor.Wherein, the space isolation is first conductor and the second conductor is not on spatial position
Contact, be spaced apart from each other.
In semiconductor devices 200, the source area and drain region are the region n-type doping N+, in other embodiments,
The source area and drain region can also be the p-type doping region P+.The substrate PSUB and be located at p-type that the base is adulterated by p-type
N-type high-pressure trap area HVNW in substrate PSUB is constituted in other embodiments, and the base can also be only by semiconductor substrate structure
At.The first medium layer (unmarked in figure to come out) is used as gate dielectric layer, and first conductor is grid conductor, to be used for
It is electrically connected with gate electrode Gate (only illustrated with connection terminal in Fig. 2, and be not drawn into specific gate electrode Gate).Described first
Dielectric layer can be oxide skin(coating), and such as SiO2 layers, and first conductor can be polysilicon layer Ploy1, be covered on described
On first medium layer.The Withstand voltage layer can be second dielectric layer, if heavy oxygen layer Oxide, heavy oxygen layer Oxide can be beak
Type, wherein the thickness of the second dielectric layer is greater than the thickness of the first medium layer.Second conductor can be polysilicon
Layer Ploy2, is covered on the Withstand voltage layer.Second conductor and the first field plate electrode Plate1 (only use connecting pin in Fig. 5
Son signal, and it is not drawn into specific field plate electrode Plate1) electrical connection.First field plate electrode Plate1 can be with source electrode
Source connects identical current potential, i.e. the first field plate electrode Plate1 is electrically connected with source electrode Source, the first field plate electrode
Plate1 can also individually connect other current potentials, and the first field plate electrode Plate1 connects different current potentials from gate electrode Gate.Due to
First field plate electrode 1 connects different current potentials from gate electrode Gate, makes semiconductor devices in the current potential that gate electrode Gate is connect
500 it is in an off state when, the first field plate electrode Plate1, still can be to float by receiving certain current potential described in assisted depletion
Area is moved, barotolerance when under keeping semiconductor devices 500 in an off state.Further, since first conductor is whole
On the first medium layer, so that the overlapping part in itself and drain region (region where drain region) becomes smaller, Ke Yi great
Amplitude reduction gate charge Qgd, so that semiconductor devices 200 can be applied to high frequency field.
Source electrode Source is electrically connected with source area, and extends at least partly described second conductor (polysilicon Ploy2)
Top so that the first medium layer and/or pressure resistance that the position place that disconnects of first conductor and the second conductor is exposed
The top of layer cover by the source electrode Source (covering herein, not only the source electrode Source directly with it is exposed
The first medium layer and/or Withstand voltage layer contact covering, but non-contact covering, i.e., it is naked that the described source electrode Source is located at institute
The first medium layer of dew and/or the top of Withstand voltage layer).The electric field of the gap of first conductor and the second conductor may
It will appear and fall, and in semiconductor devices 200, it, can be with by the non-contact covering of source electrode Source at the open position
The phenomenon that avoiding the electric field at the open position from falling, so as to improve the pressure-resistant performance of semiconductor devices 200.
In semiconductor devices 200, further include positioned at the base first surface on interlayer dielectric layer (in Fig. 2 not
Draw), the exposed source area N+ of interlayer dielectric layer, the source electrode Source include across the interlayer dielectric layer and
The first part contacted with the source area N+, and be located at the inter-level dielectric layer surface and extend at least partly described second
Second part above conductor, the second part are electrically connected with the first part, and are extended to by the first part
Above second conductor, a part of the source electrode Source is located at the position that first conductor and the second conductor disconnect
Set place top.
Semiconductor devices 200 further includes the drift region and body area in the base, and the drain region is located at the drift
It moves in area, and the Withstand voltage layer is at least partially disposed above the drift region, the source area is located in the body area, and institute
State being at least partially disposed above the body area for first medium floor.The doping type in the body area and the doping class of the source area
Type is different, and body area Pbody, N+ the type source area of for example, p-type doping is located in the body area Pbody, to be used for source electrode
Source (Fig. 2 is illustrated with connection terminal, is not drawn into specific source electrode Source) electrical connection.The drift region and the drain electrode
Area's doping Class Type having the same is lightly doped, drain region such as the drift region N-drift of n-type doping relative to drain region N+
N+ and drain electrode Drain (Fig. 2 connection terminal is illustrated, and specific drain electrode Drain is not drawn into) electrical connection.Body area Pbody makees
For the channel region of semiconductor devices 200, the first medium floor is at least partly covered on body area Pbody.Drift region N-
The part of drift is located at the Withstand voltage layer, such as Oxide layers of lower section, the area the Bing Xiangti direction Pbody being laterally extended to hinder as far as possible
Horizontal proliferation of the block body area Pbody to the drain region direction N+.
Fig. 3 is a kind of transverse diffusion metal oxide semiconductor device 300 provided according to the utility model embodiment two
Structural schematic diagram.Semiconductor devices 300 the difference is that only with semiconductor devices 200, second conductor, i.e. polycrystalline
A part of silicon Poly2 is also located on the first medium layer, and polysilicon Ploy2 prolongs from the part of the first medium layer
It extends on heavy oxygen layer Oxide, so that polysilicon Poly2's is partially covered on the first medium layer and heavy oxygen layer Oxide
Above intersection, the gate charge Qgd of semiconductor devices 300 is effectively reduced.
Fig. 4 is a kind of transverse diffusion metal oxide semiconductor device 400 provided according to the utility model embodiment three
Structural schematic diagram.Semiconductor devices 400 the difference is that only with semiconductor devices 200, first conductor, i.e. polycrystalline
A part of silicon Poly1 is also located at Withstand voltage layer, i.e. on heavy oxygen layer Oxide, polysilicon Ploy1 covers the first medium layer, and
It is extended to from the first medium layer on the heavy oxygen layer Oxide of part, so that being partially covered on for polysilicon Poly1 is described
Above the intersection of first medium layer and heavy oxygen layer Oxide, the gate charge Qgd of semiconductor devices 400 is effectively reduced.
Fig. 5 is a kind of transverse diffusion metal oxide semiconductor device 500 provided according to the utility model embodiment four
Structural schematic diagram.Semiconductor devices 500 and semiconductor devices 400 are essentially identical, the difference is that only, semiconductor devices
500 further include at least one third conductor, and each third conductor is respectively positioned on the Withstand voltage layer, and space is isolated each other,
And the third conductor adjacent with second conductor is isolated with second conductor space.In semiconductor devices 500
In, the third conductor can be polysilicon Poly3, each polysilicon Ploy3 and each corresponding second field plate electrode (Fig. 5
In be not drawn into) electrical connection, each second field plate electrode is different from the current potential that the first field plate electrode Plate1 is connect, and
In each second field plate electrode, connect with the second field plate being electrically connected of the polysilicon Ploy3 closer to drain region N+
Current potential is higher, can be further improved the pressure-resistant performance of device in this way.In addition, adjacent with the first field plate electrode Plate1
Resistance can be set between one second field plate electrode and between each adjacent second field plate electrode.
Fig. 6 is a kind of transverse diffusion metal oxide semiconductor device 600 provided according to the utility model embodiment five
Structural schematic diagram.Semiconductor devices 600 and semiconductor devices 200 are essentially identical, the difference is that only, semiconductor devices is also
Including the reduction surface field effect layer being located in the base, the reduction surface field effect floor is located at the body area and drift region
Lower section, and there is identical doping type with the body area, and there is different doping types from the drift region.
The reduction surface field effect layer is for drift region described in assisted depletion, so that the drift region is with higher
It when doping concentration, still is able to be drained unnecessarily quickly, to reduce the surface field of semiconductor devices 600, so that semiconductor devices
600 not only have lower conducting resistance Rdson, but also breakdown voltage Bv with higher.For the reduction semiconductor of greater room
The conducting resistance Rdson of device 600, first spacing reduced between surface field effect layer and the drift region are necessary to ensure that
Greater than zero, that is, guarantee there is certain space to flow through for electronics between the reduction surface field effect layer and the drift region.In addition,
In order to preferably adjust the voltage endurance of semiconductor devices 600, need to be adjusted according to the doping concentration of the drift region described
The size of first spacing, wherein the doping concentration of the drift region is bigger, just more needs the reduction surface field effect layer
Assisted depletion, then first spacing is smaller, and vice versa.In semiconductor devices 600, the reduction surface field effect layer can
Think the p type buried layer PBL being formed in N-type high-pressure trap area HVNW.
In order to provide the doping of enough first kind (with first in the position closer to 600 surface of semiconductor devices
Doping type is corresponding, and such as the first doping type is p-type, then the impurity of the first kind is p-type doping), with better auxiliary consumption
Region to the greatest extent near drain region, to reduce the surface field in the region, the reduction surface field effect layer and the body
Between area the second spacing needs be arranged be less than or equal to first spacing, i.e., the described reduction surface field effect layer closer to
The body area.Since in semiconductor devices 600, the body area is that body area Pbody, N+ the type source area of p-type doping is located at institute
In the area Shu Ti Pbody, (only to be illustrated with connection terminal in Fig. 6 for source electrode Source, and be not drawn into specific source electrode
Source it) is electrically connected.In semiconductor devices 600, due to the reduction surface field effect layer be a p type buried layer PBL, then for
Ensure that first spacing is greater than or equal to second spacing, in a first direction, the thickness of the drift region is less than institute
The thickness in the area Shu Ti, wherein the first direction refers to the stacking direction for reducing surface field effect layer and the drift region.
The reduction surface field effect layer in semiconductor devices 600 also can be applied to semiconductor devices 300, semiconductor devices 400
And in semiconductor devices 500.
Fig. 7 is a kind of transverse diffusion metal oxide semiconductor device 700 provided according to the utility model embodiment six
Structural schematic diagram.Semiconductor devices 700 and semiconductor devices 600 are essentially identical, the difference is that only, in semiconductor devices
In 700, first table of the first surface (one side close to the drift region) for reducing surface field effect layer with the base
Spacing between face is not equal, but is located at the first table of the reduction surface field effect floor below the body area
Third spacing between face and the first surface of the base is less than the reduction surface field effect being located at below the drift region
Answer the 4th spacing between the first surface of layer and the first surface of the base, i.e., so that the reduction below the body area
Surface field effect floor improves the breakdown voltage of semiconductor devices 700 as close as possible to body area to reduce surface field as far as possible,
And make the reduction surface field effect layer below the drift region and there are certain spaces between drift region, with amplitude peak
Reduce the conducting resistance of semiconductor devices 700.
In semiconductor devices 700, the surface field effect layer can be in the base and contacting one another by buried layer
The first buried layer and the second buried layer constitute, first buried layer is at least partially disposed at below the body area, second buried layer
Be at least partially disposed at below the drift region, the spacing between first buried layer and the first surface of the base is described
Third spacing, the spacing between second buried layer and the first surface of the base are the 4th spacing.Such as described first
Buried layer is p type buried layer PBL1, and second buried layer is p type buried layer PBL2, wherein making the first buried layer PBL1 as close as possible to p-type body
Area Pbody, if the two can be contacted directly, then source electrode voltage (the usually electricity with reference to zero being applied on Pbody
Pressure) it can be applied on PBL1 by Pbody, with dynamic Rdson generation, and the second buried layer PBL and drift region N-drift are not
Contact, i.e., described first spacing are greater than zero, provide broader current path, the reduction semiconductor devices of greater room with electron
700 Rdson.The reduction surface field effect layer in semiconductor devices 700 also can be applied to semiconductor devices 300, half
In conductor device 400 and semiconductor devices 500.
Fig. 8 is a kind of transverse diffusion metal oxide semiconductor device 800 provided according to the utility model embodiment seven
Structural schematic diagram.Semiconductor devices 800 and semiconductor devices 600 are essentially identical, the difference is that only, semiconductor devices
800 further include being located in the base, and be located at the separation layer below the reduction surface field active layer, and the separation layer will be described
Reduce surface field effect layer be isolated with the base, in favor of semiconductor devices 800 high-voltage applications in this embodiment, it is described every
Absciss layer can be the third buried layer NBL of n-type doping, be located in high pressure trap HVNW, and be located at below buried layer PBL, third buried layer
The doping concentration of NBL is heavy doping for high pressure trap HVNW.Equally, the reduction surface field in semiconductor devices 700
Separation layer described in semiconductor devices 800 also can be set below effect layer.
It is as described above according to the embodiments of the present invention, these embodiments details all there is no detailed descriptionthe,
Also not limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This
These embodiments are chosen and specifically described to specification, be in order to preferably explain the principles of the present invention and practical application, from
And skilled artisan is enable to make well using the utility model and modification on the basis of the utility model
With.The utility model is limited only by the claims and their full scope and equivalents.
Claims (15)
1. a kind of transverse diffusion metal oxide semiconductor device characterized by comprising
Base,
Source area and drain region in the base,
First surface and the first medium layer adjacent with the source area positioned at the base,
Positioned at the Withstand voltage layer of the first surface of the base, the Withstand voltage layer be located at the first medium layer and the drain region it
Between,
The first conductor being at least partially disposed on the first medium layer,
The second conductor being at least partially disposed on the Withstand voltage layer,
The source electrode being electrically connected with the source area,
Wherein, first conductor and the isolation of the second conductor space, and the source electrode by extended to above the source area to
The top of second conductor described in small part.
2. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that further include being located at institute
The interlayer dielectric layer on the first surface of base, the exposed source area of interlayer dielectric layer are stated, the source electrode includes wearing
It crosses the interlayer dielectric layer and the first part with the source region contact, and positioned at the inter-level dielectric layer surface and extends
Second part at least partly described second conductor.
3. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that further include with it is described
The gate electrode of first conductor electrical connection, and the first field plate electrode with the electrical connection of the second conductor,
The gate electrode connects different current potentials from first field plate electrode.
4. transverse diffusion metal oxide semiconductor device according to claim 3, which is characterized in that first field plate
Electrode and the source electrode connect identical current potential.
5. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that further include at least one
A third conductor, each third conductor are respectively positioned on above the Withstand voltage layer, and space is isolated each third conductor each other,
And each third conductor is isolated with second conductor space.
6. transverse diffusion metal oxide semiconductor device according to claim 5, which is characterized in that further include with it is each
Each second field plate electrode of the corresponding electrical connection of the third conductor,
In each second field plate electrode, the current potential that the second field plate electrode closer to the drain region is connect is higher.
7. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that second conductor
It is covered on a part of a conductor layer in the first conductor above the intersection of the first medium layer and Withstand voltage layer.
8. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that the Withstand voltage layer is
Second dielectric layer, and the thickness of the second dielectric layer is greater than the first medium layer.
9. transverse diffusion metal oxide semiconductor device according to claim 1, which is characterized in that further include being located at institute
The drift region and body area in base are stated,
The drain region is located in the drift region, and the Withstand voltage layer is at least partially disposed above the drift region,
The source area is located in the body area, and the first medium floor is at least partially disposed above the body area.
10. transverse diffusion metal oxide semiconductor device according to claim 9, which is characterized in that further include being located at
Reduction surface field effect layer in the base, the reduction surface field effect floor are located at below the body area and drift region, and
There is identical doping type with the body area, and there is different doping types from the drift region.
11. transverse diffusion metal oxide semiconductor device according to claim 10, which is characterized in that the reduction table
The first spacing between face field-effect layer and the drift region is greater than zero.
12. transverse diffusion metal oxide semiconductor device according to claim 11, which is characterized in that the reduction table
The second spacing between face field-effect floor and the body area is less than or equal to first spacing.
13. transverse diffusion metal oxide semiconductor device according to claim 10, which is characterized in that further include being located at
In the base, and it is located at the separation layer below the reduction surface field effect layer,
The separation layer is isolated by the reduction surface field effect layer with the base.
14. transverse diffusion metal oxide semiconductor device according to claim 11, which is characterized in that the drift region
Doping concentration it is bigger, first spacing is smaller.
15. transverse diffusion metal oxide semiconductor device according to claim 10, which is characterized in that base's packet
Semiconductor substrate and the high-pressure trap area in the semiconductor substrate are included,
The drift region, body area and reduction surface field effect area are respectively positioned in the high-pressure trap area,
The doping type of the semiconductor substrate is identical as the reduction doping type of surface field effect layer, and the high pressure trap
The doping type in area is different from the reduction doping type of surface field active layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820798923.XU CN208385412U (en) | 2018-05-25 | 2018-05-25 | Transverse diffusion metal oxide semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820798923.XU CN208385412U (en) | 2018-05-25 | 2018-05-25 | Transverse diffusion metal oxide semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208385412U true CN208385412U (en) | 2019-01-15 |
Family
ID=64969021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820798923.XU Active CN208385412U (en) | 2018-05-25 | 2018-05-25 | Transverse diffusion metal oxide semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208385412U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682690A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacturing method |
| CN111244178A (en) * | 2020-01-15 | 2020-06-05 | 合肥晶合集成电路有限公司 | Diffusion type field effect transistor and forming method thereof |
| CN114242777A (en) * | 2022-02-22 | 2022-03-25 | 北京芯可鉴科技有限公司 | LDMOSFET, preparation method, chip and circuit |
| CN116960183A (en) * | 2023-07-27 | 2023-10-27 | 荣芯半导体(淮安)有限公司 | Semiconductor device including LDMOS transistor |
-
2018
- 2018-05-25 CN CN201820798923.XU patent/CN208385412U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108682690A (en) * | 2018-05-25 | 2018-10-19 | 矽力杰半导体技术(杭州)有限公司 | Transverse diffusion metal oxide semiconductor device and its manufacturing method |
| CN111244178A (en) * | 2020-01-15 | 2020-06-05 | 合肥晶合集成电路有限公司 | Diffusion type field effect transistor and forming method thereof |
| US11024722B1 (en) | 2020-01-15 | 2021-06-01 | Nexchip Semiconductor Corporation | Diffused field-effect transistor and method of fabricating same |
| CN114242777A (en) * | 2022-02-22 | 2022-03-25 | 北京芯可鉴科技有限公司 | LDMOSFET, preparation method, chip and circuit |
| CN116960183A (en) * | 2023-07-27 | 2023-10-27 | 荣芯半导体(淮安)有限公司 | Semiconductor device including LDMOS transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN208385412U (en) | Transverse diffusion metal oxide semiconductor device | |
| CN108682689A (en) | Lateral diffusion metal-oxide-semiconductor structure and its forming method | |
| CN108807543A (en) | Transverse diffusion metal oxide semiconductor device and its manufacturing method | |
| CN108682690A (en) | Transverse diffusion metal oxide semiconductor device and its manufacturing method | |
| US20210028299A1 (en) | LDMOS Device And Method For Forming The Same | |
| TWI455311B (en) | Laterally diffused metal-oxide-semiconductor device | |
| CN101017847A (en) | Semiconductor devices and methods for fabricating the same | |
| CN102867853B (en) | Metal Oxide Half Field Effect Transistor | |
| CN202633320U (en) | Power metal oxide semiconductor field effect transistor | |
| CN208385413U (en) | Lateral diffusion metal-oxide-semiconductor structure | |
| TW201603288A (en) | LDMOS device and resurf structure | |
| CN116581150B (en) | Asymmetric double-groove SiC MOSFET cell structure, device and preparation method | |
| CN108682691A (en) | The manufacturing method and semiconductor devices of transverse diffusion metal oxide semiconductor device | |
| CN208240687U (en) | Transverse diffusion metal oxide semiconductor device | |
| US10665712B2 (en) | LDMOS device with a field plate contact metal layer with a sub-maximum size | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| CN103091533A (en) | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices | |
| CN208240684U (en) | A kind of semiconductor devices | |
| CN103633139A (en) | High-voltage metal oxide semiconductor transistor element | |
| CN107958936A (en) | Semiconductor devices and the method being used for producing the semiconductor devices | |
| US9882043B2 (en) | Semiconductor device with trench termination structure | |
| TW201336071A (en) | Semiconductor structure and method for forming the same | |
| CN102769028B (en) | Semiconductor structure and manufacturing method thereof | |
| US10535765B2 (en) | Power semiconductor device | |
| CN101764153B (en) | Laterally diffused metal oxide semiconductor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder | ||
| CP02 | Change in the address of a patent holder |
Address after: 310051 No. 6 Lianhui Street, Xixing Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd. Address before: 310012 A1501-A1505 and A1509-A1511, building 90, 71 Wensanlu Road, Xihu District, Zhejiang, Hangzhou, China Patentee before: Silergy Semiconductor Technology (Hangzhou ) Co., Ltd. |