US10535765B2 - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- US10535765B2 US10535765B2 US16/118,449 US201816118449A US10535765B2 US 10535765 B2 US10535765 B2 US 10535765B2 US 201816118449 A US201816118449 A US 201816118449A US 10535765 B2 US10535765 B2 US 10535765B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 230000015556 catabolic process Effects 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Definitions
- the invention relates to a semiconductor device. More particularly, the invention relates to a power semiconductor device.
- the power semiconductor device is a semiconductor device widely used in an analog circuit. Since the power semiconductor device has a very low conductance resistance and very fast switching speed, the power semiconductor device can be applied in a power switch circuit to make power management techniques more efficient.
- the invention provides a power semiconductor device in which two epitaxial layers are disposed on a substrate and an outermost trench electrode in a terminal region is electrically connected to a drain, so as to improve electric field distortion at an edge of the trench electrode in the terminal region and to further increase a breakdown voltage of the power semiconductor device.
- a power semiconductor device in an embodiment of the invention, includes a substrate having an active region and a terminal region. The terminal region surrounds the active region.
- a first epitaxial layer is disposed on the substrate in the active region and the terminal region.
- a second epitaxial layer is disposed on the first epitaxial layer.
- the second epitaxial layer includes a first termination trench, a second termination trench, and a third termination trench.
- the first termination trench is disposed in the terminal region and is adjacent to the active region.
- the second termination trench is disposed in the terminal region.
- the third termination trench is disposed in the terminal region.
- the second termination trench is located between the first termination trench and the third termination trench.
- the third termination trench has a third electrode electrically connected to a drain.
- the first termination trench has a first electrode being electrically connected to a source.
- the second termination trench has a second electrode being electrically connected to a source or electrically floating.
- a distance between the first termination trench and the second termination trench is greater than a distance between the second termination trench and the third termination trench.
- the power semiconductor device further includes a plurality of active trenches disposed in the second epitaxial layer in the active region, extending in a first direction, and alternately arranged along a second direction.
- the first direction is different from the second direction.
- the first termination trench and the active trenches are separated from each other.
- the first termination trench and the active trenches are connected to each other.
- a doping concentration of the second epitaxial layer is greater than a doping concentration of the first epitaxial layer.
- the first termination trench, the second termination trench, and the third termination trench are separated from each other.
- the first termination trench, the second termination trench, and the third termination trench further extend into the first epitaxial layer.
- the double epitaxial structure is used in the embodiments of the invention to reduce the conductance resistance of the power semiconductor device.
- the outermost trench electrode in the terminal region is electrically connected to the drain. In this way, the electric field distortion at the edge of the trench electrode in the terminal region is mitigated or even eliminated, and that the breakdown voltage of the power semiconductor device is further improved. Therefore, the power semiconductor device provided by the embodiments of the invention may deliver favorable device properties under a certain device size.
- FIG. 1 is a schematic top view of a power semiconductor device according to a first embodiment of the invention.
- FIG. 2A is a schematic cross-sectional view taken along a line I-I′ of FIG. 1 .
- FIG. 2B is a schematic cross-sectional view taken along the line I-I′ of FIG. 1 .
- FIG. 3 is a schematic top view of a power semiconductor device according to a second embodiment of the invention.
- FIG. 1 is a schematic top view of a power semiconductor device according to a first embodiment of the invention.
- FIG. 2A is a schematic cross-sectional view taken along a line I-I′ of FIG. 1 .
- the first conductivity type is N-type and the second conductivity type is P-type as an example.
- the invention is not limited thereto. Those having ordinary skill in the art should know that the first conductivity type can also be P-type and the second conductivity type can be N-type.
- a power semiconductor device 1 provided by the first embodiment of the invention includes a substrate 100 having an active region R 1 and a terminal region R 2 .
- the terminal region R 2 surrounds the active region R 1 to prevent voltage breakdown from occurring.
- the substrate 100 can be, for example, a semiconductor substrate or a semiconductor compound substrate.
- the substrate 100 may be a semiconductor substrate having the first conductivity type, for example, a N-type heavily doped silicon substrate.
- a first epitaxial layer 102 is disposed on the substrate 100 in the active region R 1 and the terminal region R 2 .
- the first epitaxial layer 102 is an epitaxial layer having the first conductivity type, for example, a N-type lightly doped epitaxial layer, and a forming method thereof includes performing a selective epitaxy growth (SEG) process.
- a second epitaxial 104 layer is disposed on the first epitaxial layer 102 . That is, the first epitaxial layer 102 is disposed between the substrate 100 and the second epitaxial layer 104 .
- the second epitaxial layer 104 is an epitaxial layer having the first conductivity type, for example, a N-type lightly doped epitaxial layer, and a forming method thereof includes performing a selective epitaxy growth process.
- a doping concentration of the second epitaxial layer 104 is greater than a doping concentration of the first epitaxial layer 102 , so as to form a double epitaxial structure.
- the double epitaxial structure is able to reduce conductance resistance of the power semiconductor device 1 .
- the active region R 1 has a plurality of active trenches 10 .
- the active trench 10 is disposed in the second epitaxial layer 104 of the active region R 1 .
- the active trenches 10 extend along a first direction D 1 and are arranged along a second direction D 2 .
- the active trenches 10 are arranged in an equidistant manner and separated from each other.
- at least one terminal face of each of the active trenches 10 is substantially aligned.
- each of the active trenches 10 has a conductive layer 110 , an insulating layer 108 , and a conductive layer 114 to form a trench gate structure.
- the material of the conductive layer 110 and the conductive layer 114 includes doped polysilicon.
- the material of the insulating layer 108 includes silicon oxide.
- the conductive layer 110 can be used as a shield electrode, and the conductive layer 114 can be used as a gate and is electrically connected to a gate pad G, as shown in FIG. 1 .
- the insulating layer 108 can be used as an inter-gate insulation layer between a gate (the conductive layer 114 ) and a shield gate (the conductive layer 110 ) to electrically insulate the conductor layer 110 and the conductive layer 114 .
- a portion of the insulating layer 108 surrounding the conductive layer 110 electrically insulates the conductive layer 110 and the second epitaxial layer 104 .
- Another portion of the insulating layer 108 surrounding the conductive layer 114 electrically insulates the conductive layer 114 , a body layer 106 , and a doped region 116 .
- the conductive layer 110 and the conductive layer 114 are illustrated to be separated from each other in FIG. 2A , but the invention is not limited thereto. In other embodiments, the conductive layer 110 and the conductive layer 114 may be connected to each other to form a single gate.
- the terminal region R 2 has at least three termination trenches 20 .
- the terminal region R 2 has a first termination trench 22 , a second termination trench 24 , and a third termination trench 26 .
- the first termination trench 22 , the second termination trench 24 , and the third termination trench 26 are separated from each other and are not connected.
- the first termination trench 22 is disposed in the second epitaxial layer 104 of the terminal region R 2 .
- the first termination trench 22 extends along the second direction D 2 and surrounds the active trenches 10 in the active region R 1 to form an enclosed annular trench.
- the first termination trench 22 is adjacent to the active trenches 10 of the active region R 1 and are separated from the active trenches 10 and are not connected.
- the first direction D 1 is intersected with the second direction D 2 . In an embodiment, the first direction D 1 is perpendicular to the second direction D 2 .
- a first electrode 122 and an insulating layer 118 are included in the first termination trench 22 to form a terminal structure.
- the insulating layer 118 surrounds the first electrode 122 to electrically insulate the first electrode 122 and the second epitaxial layer 104 .
- the material of the first electrode 122 includes doped polysilicon.
- the material of the insulating layer 118 includes silicon oxide.
- the second termination trench 24 is disposed in the terminal region R 2 and surrounds the first termination trench 22 to form an enclosed annular trench.
- the third termination trench 26 is disposed in the terminal region R 2 and surrounds the second termination trench 24 to form an enclosed annular trench. That is, as shown in FIG. 1 , the second termination trench 24 is disposed between the first termination trench 22 and the third termination trench 26 .
- a distance d 1 between the first termination trench 22 and the second termination trench 24 is greater than a distance d 2 between the second termination trench 24 and the third termination trench 26 to ensure or increase the breakdown voltage.
- a ratio of the distance d 1 to the distance d 2 is designed according to actual device requirements and application conditions and is preferably between 2 and 50 , but is not limited thereto.
- a second electrode 124 and the insulating layer 118 are included in the second termination trench 24 to form a terminal structure.
- the insulating layer 118 surrounds the second electrode 124 to electrically insulate the second electrode 124 and the second epitaxial layer 104 .
- a third electrode 126 and the insulating layer 118 are included in the third termination trench 26 to form a terminal structure.
- the insulating layer 118 surrounds the third electrode 126 to electrically insulate the third electrode 126 and the second epitaxial layer 104 .
- the material of the second electrode 124 and the third electrode 126 includes doped polysilicon.
- the material of the insulating layer 118 includes silicon oxide.
- the first electrode 122 is electrically connected to a source S
- the second electrode 124 is electrically connected to the source S or is electrically floating F
- the third electrode 126 is electrically connected to a drain D. Since the third electrode 126 in the third termination trench 26 is electrically connected to the drain D to act as an isolation trench, a power line is limited to be located at an edge of the third electrode 126 in the third termination trench 26 . Hence, electric field distortion at the edge of the third electrode 126 can be mitigated or even eliminated, and that the breakdown voltage of the power semiconductor device 1 is improved.
- the difference between the doping concentrations of the first epitaxial layer 102 and the second epitaxial layer 104 lead to the electric field distortion.
- the outermost trench electrode is electrically connected to the drain in this embodiment, as such, the breakdown voltage of the power semiconductor device may be increased.
- the power semiconductor device of this embodiment can deliver favorable conductance resistance and breakdown voltage under a certain device size.
- the active trenches 10 can be used as cell trenches to house the trench gate structure, and the first termination trench 22 , the second termination trench 24 , and the third termination trench 26 can all be used to house the terminal structure.
- the power semiconductor device 1 can include a plurality of termination trenches to surround the active trenches 10 .
- a number of the third termination trench 26 may be greater than 1 (i.e., 2, 3, 4, or greater) based on the difference between the doping concentrations of the first epitaxial layer 102 and the second epitaxial layer 104 .
- the third electrodes 126 in the third termination trenches 26 can all be electrically connected to the drain D.
- the third electrode 126 in the third termination trench 26 can be electrically connected to the drain D through a plug 134 , a plug 136 , and a conductive layer 130 .
- the plug 134 extends from a bottom surface of the conductive layer 130 and penetrates a dielectric layer 112 for being in contact with the second epitaxial layer 104 .
- the plug 136 extends from the bottom surface of the conductive layer 130 and penetrates the dielectric layer 112 for being in contact with the third electrode 126 .
- the third electrode 126 in the third termination trench 26 can be electrically connected to the drain D located at a bottom portion of the substrate 100 through the plug 136 , the conductive layer 130 , the plug 134 , the second epitaxial layer 104 , the first epitaxial layer 102 , and the substrate 100 .
- the third electrode 126 in the third termination trench 26 and the drain D have the same electrical potential.
- the material of the plug 134 , the plug 136 , and the conductive layer 130 include a conductive material, and can be a metal, such as aluminum.
- the material of the dielectric layer 112 includes silicon oxide.
- the power semiconductor device 1 of this embodiment further includes the body layer 106 and the doped region 116 .
- the body layer 106 is disposed in the second epitaxial layer 104 between the active trenches 10 , between the active trenches 10 and the first termination trench 22 , and between the first termination trench 22 and the second termination trench 24 . As shown in FIG. 2A , the body layer 106 surrounds the active trench 10 and the first termination trench 22 .
- the body layer 106 has the second conductivity type and is, for example, a P-type body layer.
- the doped region 116 is disposed in the body layer 106 and surrounds upper portions of the active trench 10 and the first termination trench 22 .
- the doped region 116 has the first conductivity type and is, for example, a N-type heavily doped region.
- the doped region 116 can be used as the source.
- the first electrode 122 in the first termination trench 22 or the second electrode 124 in the second termination trench 24 can be electrically connected to the doped region 116 (i.e., the source) through different routing traces, which is not shown in FIG. 2A though. That is, the first electrode 122 or the second electrode 124 and the source may have the same electrical potential.
- FIG. 2B is a schematic cross-sectional view taken along the line I-I′ of FIG. 1 .
- a power semiconductor device 1 b of FIG. 2B and a power semiconductor device 1 a of FIG. 2A are similar.
- a difference between the two power semiconductor devices includes that the active trench 10 , the first termination trench 22 , the second termination trench 24 , and the third termination trench 26 of the power semiconductor device 1 b of FIG. 2B penetrate the second epitaxial layer 104 and extend into the first epitaxial layer 102 .
- a bottom surface of the active trench 10 , a bottom surface of the first termination trench 22 , a bottom surface of the second termination trench 24 , and a bottom surface of the third termination trench 26 are below an interface between the first epitaxial layer 102 and the second epitaxial layer 104 as shown in FIG. 2B .
- a bottom surface of the conductive layer 114 (e.g., the gate) in the active trench 10 can be below a bottom surface of the body layer 106 as shown in FIG. 2B , but the invention is not limited thereto.
- the bottom surface of the conductive layer 114 in the active trench 10 can also be above the bottom surface of the body layer 106 according to design requirements as shown in FIG. 2A .
- FIG. 3 is a schematic top view of a power semiconductor device according to a second embodiment of the invention.
- a power semiconductor device 2 of the second embodiment is similar to the power semiconductor device 1 of the first embodiment.
- a difference between the two power semiconductor devices includes that the first termination trench 22 and the active trenches 10 are connected to each other in the power semiconductor device 2 of the second embodiment.
- the conductive layer 110 (e.g., the shield electrode) in the active trench 10 may be connected to the first electrode 122 in the first termination trench 22 .
- the first electrode 122 in the first termination trench 22 is electrically connected to the source
- the first electrode 122 , the conductive layer 110 e.g., the shield electrode
- the source may have the same electrical potential.
- the double epitaxial structure is used in the embodiments of the invention to reduce the conductance resistance of the power semiconductor device.
- the outermost trench electrode in the terminal region is electrically connected to the drain in the embodiments of the invention. In this way, the electric field distortion at the edge of the trench electrode in the terminal region is mitigated or even eliminated, and that the breakdown voltage of the power semiconductor device is further improved. Therefore, the power semiconductor device provided by the embodiments of the invention may deliver favorable device properties under a certain device size.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (9)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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TW107113161A TW201944596A (en) | 2018-04-18 | 2018-04-18 | Power semiconductor device |
TW107113161 | 2018-04-18 | ||
TW107113161A | 2018-04-18 |
Publications (2)
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US20190326430A1 US20190326430A1 (en) | 2019-10-24 |
US10535765B2 true US10535765B2 (en) | 2020-01-14 |
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US16/118,449 Active US10535765B2 (en) | 2018-04-18 | 2018-08-31 | Power semiconductor device |
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CN (1) | CN110391296A (en) |
TW (1) | TW201944596A (en) |
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2018
- 2018-04-18 TW TW107113161A patent/TW201944596A/en unknown
- 2018-05-25 CN CN201810515442.8A patent/CN110391296A/en active Pending
- 2018-08-31 US US16/118,449 patent/US10535765B2/en active Active
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CN110391296A (en) | 2019-10-29 |
US20190326430A1 (en) | 2019-10-24 |
TW201944596A (en) | 2019-11-16 |
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